CN104916545A - 一种半导体器件的制作方法 - Google Patents
一种半导体器件的制作方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- -1 carbon ions Chemical class 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims description 68
- 238000000034 method Methods 0.000 claims description 54
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
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- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
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- 239000010937 tungsten Substances 0.000 claims description 4
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- 238000000137 annealing Methods 0.000 claims description 3
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- 229910004129 HfSiO Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- 229910001449 indium ion Inorganic materials 0.000 description 1
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- 230000001360 synchronised effect Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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Abstract
本发明提供一种半导体器件的制作方法,在栅极、源极和漏极表面形成金属硅化物之前,采用纯碳离子或者锗碳离子或者硅离子对所述栅极、源极和漏极的表面进行预非晶化处理,以减小器件的阈值电压的失配,来提高器件性能。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体器件的制作方法。
背景技术
随着集成电路技术的不断发展,在单一芯片中集成的半导体器件的数量不断增多,在进行集成电路设计时,通常要使用若干相同电学参数的半导体器件。例如,静态随机存储器(SRAM)作为挥发性存储器中的一员,具有高速度、低功耗与标准工艺相兼容等优点,广泛应用于PC、个人通信、消费电子产品(智能卡、数码相机、多媒体播放器)等领域。特别是,高速同步SRAM用于诸如工作站等超高速缓存器的应用,超高速缓存为再利用的数据或指令提供高速的存储。在设计静态随机存储器(SRAM)的存储单元时,需要有若干相同电学参数的MOS晶体管,然而,在SRAM器件设计和生产过程中,由于不确定、随机误差、梯度误差等原因,一些设计时完全相同的MOS晶体管在生产后却存在误差,即名义上相同的MOS晶体管的电学参数常常会发生漂移,造成原本应相同的MOS晶体管的电学参数失配(mismatch),即匹配特性下降,从而会引起SRAM存储速度变缓、功耗增加、时钟混乱等问题。
其中,造成这种晶体管电学参数失配的具体原因很多,其中主要包括:器件附近的图案密度的高低不一致而造成的研磨抛光速率不同,离子注入过程中的工艺偏差造成的注入剂量不同,工艺偏差造成的一些应力层引起的应力不均匀等。针对这些原因,一些专利例如CN 102683169 A等做了相关的改进。
随着集成电路技术的不断发展,SRAM器件集成度更高,其内部的MOS晶体管的尺寸也会不断降低,由于晶体管尺寸的进一步降低,阈值电压失配(Vt Mismatch)方面对于SRAM良率的提高的影响变的尤为重要。
因此,需要一种半导体器件的制作方法,能够降低CMOS器件的阈值电压的失配,改善CMOS器件的性能。
发明内容
本发明的目的在于提供一种半导体器件的制作方法,能够降低CMOS器件的阈值电压的失配,改善CMOS器件的性能。
为解决上述问题,本发明提出一种半导体器件的制作方法,包括:
提供一半导体衬底,在所述半导体衬底的各个有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙;
在栅极两侧的有源区中形成源极和漏极;
采用纯碳离子或者锗碳混合离子或者硅离子对所述栅极、源极和漏极的表面进行预非晶化处理;
采用金属硅化物工艺处理所述栅极、源极和漏极表面形成金属硅化物。
进一步的,提供所述半导体衬底的步骤包括:
提供一基底,通过隔离结构隔离出多个有源区;
对所述基底进行阱离子注入,形成阱,并进行退火。
进一步的,在所述半导体衬底的有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙的步骤包括:
在所述半导体衬底上依次形成栅介质层、多晶硅层;
光刻并刻蚀所述多晶硅层、栅介质层,在所述有源区表面上形成栅极;
在所述有源区表面上形成围绕所述栅极和栅介质层的第一侧墙;
以所述第一侧墙和栅极为掩膜,对所述栅极的两侧有源区进行轻掺杂源/漏区离子注入,形成轻掺杂源/漏结构;
在所述有源区表面上形成围绕所述第一侧墙的第二侧墙;
以所述第二侧墙、第一侧墙和栅极为掩膜,对所述栅极的两侧有源区的进行源/漏极离子注入,形成源极和漏极。
进一步的,在所述半导体衬底的有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙的步骤包括:
在所述半导体衬底上依次形成栅介质层、多晶硅层;
光刻并刻蚀所述多晶硅层、栅介质层,在所述有源区表面上形成栅极;
在所述有源区表面上形成围绕所述栅极和栅介质层的侧墙;
以所述侧墙和栅极为掩膜,对所述栅极两侧的有源区依次进行轻掺杂源/漏区离子注入和源/漏极离子注入,形成源极和漏极。
进一步的,进行轻掺杂源/漏区离子注入之前或之后,还对所述栅极两侧的有源区进行HALO离子注入。
进一步的,所述轻掺杂源/漏区离子注入和/或源/漏极离子注入之后,对所述栅极两侧的有源区进行退火处理。
进一步的,所述各个有源区包括用于形成NMOS区和PMOS区;进行轻掺杂源/漏区离子注入和源/漏极离子注入时,先对NMOS区进行离子注入,再对PMOS区进行离子注入。
进一步的,所述金属硅化物中的金属包括钨、钛、钽、钯、锆、钴、铂和镍中的至少一种。
进一步的,所述预非晶化处理时,离子注入能量为2KeV~7KeV,离子注入剂量为2E14~2E15/cm2,离子注入温度为-60℃~0℃。
进一步的,所述制作方法还包括:
在形成所述金属硅化物的器件表面形成金属前介质层;
在所述金属前介质层中形成通孔;
在所述通孔中形成与金属硅化物接触的金属插塞;
在形成金属插塞的器件表面形成金属层。
与现有技术相比,本发明提供的半导体器件的制作方法,在栅极、源极和漏极表面形成金属硅化物之前,采用纯碳离子或者锗碳离子或者硅离子对所述栅极、源极和漏极的表面进行预非晶化处理,以减小器件的阈值电压的失配,来提高器件性能。
附图说明
图1是本发明具体实施例的半导体器件的制作方法流程图;
图2A至2D是图1所示的制作方法中的器件剖面结构示意图。
具体实施方式
为使本发明的目的、特征更明显易懂,下面结合附图对本发明的具体实施方式作进一步的说明,然而,本发明可以用不同的形式实现,不应只是局限在所述的实施例。
请参考图1,本发明提供一种半导体器件制作方法,包括:
S1,提供一半导体衬底,在所述半导体衬底的各个有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙;
S2,在栅极两侧的有源区中形成源极和漏极;
S3,采用纯碳离子或者锗碳混合离子或者硅离子对所述栅极、源极和漏极的表面进行预非晶化处理;
S4,采用金属硅化物工艺处理所述栅极、源极和漏极表面形成金属硅化物。
请参考图2A,在步骤S1中,提供的半导体衬底100可以为以下所提到的材料中的至少一种:硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)以及绝缘体上锗化硅(SiGeOI)等。在所述衬底中可以形成有阱(即阱离子掺杂区域)102和用于隔离有源区的隔离结构101,所述隔离结构101为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构101。
其中,步骤S1提供所述半导体衬底的过程包括:首先,提供一基底,通过隔离结构101隔离出多个用作有源区I、II的区域;接着,对所述基底进行阱离子注入,形成N型阱和P型阱(102),然后进行退火,目的是对阱离子注入的掺杂离子进行激活以及对阱离子注入造成的缺陷进行修复。在本实施例中,通过磷掺杂形成N阱,通过硼掺杂形成P阱,以用于形成NMOS有源区和PMOS有源区。所述有源区包括核心器件区域和外围电路区域,所述核心器件区域和围电路区域均包括PMOS区域和NMOS区域。
优选的,在步骤S1中,继续对半导体衬底100表面进行多次阈值电压注入,形成多个梯度的阈值电压注入层。具体形成过程为:采用图案化的光刻胶覆盖半导体衬底100,以露出有源区I、II,然后对有源区进行多次阈值电压离子注入,在有源区I、II形多个成离子密度梯度分布的阈值电压注入层。其中,PMOS区注入的阈值电压离子为磷离子或砷离子,NMOS区注入的成阈值电压离子为硼离子或铟离子。并且,PMOS区和NMOS区的阈值电压离子注入先后分开进行,且离子注入量相等。阈值电压离子注入可以调节后续形成器件的阈值电压值。本实施例中,在半导体衬底100上形成的每个晶体管的阈值电压离子注入量相等,可以保证后续形成的各个器件的阈值电压并为减少后续形成的各个器件的阈值电压失配做出贡献。
其中,请继续参考图2A,步骤S1在所述半导体衬底100的有源区I、II表面上依次形成栅介质层103、栅极104以及围绕所述栅极的侧墙105a、105b的过程包括:
首先,采用原子层沉积(ALD)或快速氧化生长(RTO)工艺在所述半导体衬底表面上形成栅介质层,所述栅介质层可以为氧化硅层、氮氧化硅层、或者高k介质层,所述高k介质的材料为HfO2、Al2O3、ZrO2、HfSiO、HfSiON、HfTaO或HfZrO。
接着,在栅介质层103的上面形成栅极材料层,例如,掺杂多晶硅、金属(例如,钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如,硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如,氮化钛、氮化钽)、其他导电材料、或者其组合。本实施例的栅极材料层为多晶硅层;接着通过光刻工艺在栅极材料层的表面形成图形化的掩膜层(未图示),定义栅极的位置和分布,然后,以所述掩膜层为掩膜,依次对栅极材料层和栅介质层103进行刻蚀,分别形成栅介质层103和栅极104。本实施例中,栅介质层103的材料为氧化硅。栅介质层103与其上的栅极104组成栅极结构。
然后,在形成栅极后,在栅极104和栅介质层103的周围形成第一侧墙105a,即偏移侧墙(Offset Spacer)105a。第一侧墙105a的作用是:可以提高形成的晶体管的沟道长度,减小短沟道效应和由于短沟道效应引起的热载流子效应,同时作为后续LDD轻掺杂源/漏区离子注入的掩膜。本实施例中,第一侧墙105a可以是由氧化硅、氮化硅或氮氧化硅等绝缘材料构成的单层结构,也可以是ONO(氧化硅-氮化硅-氧化硅)等多层结构。形成第一侧墙105a的方法包括材料的淀积以及刻蚀,为本领域技术人员公知技术,在此不再赘述。
接着,在形成第一侧墙105a后,对有源区I、II进行HALO离子注入、轻掺杂(LDD)源/漏区离子注入。其中,可以按照栅极的尺寸由小到大的顺序依次对相应的器件区域进行HALO离子注入、LDD离子注入,由此减小离子注入轨迹的偏移现象,降低后续形成的半导体器件中各晶体管间的阈值电压失配;也可以按照先对NMOS区进行离子注入、再对PMOS区进行离子注入的顺序,进行HALO离子注入、LDD离子注入。具体地:以栅极104和周围的第一侧墙105a为掩膜,进行HALO离子注入、LDD离子注入,以形成未激活的HALO区域和LDD区域,需要说明的是,可以先进行了HALO离子注入、后进行LDD离子注入。HALO离子注入、轻掺杂(LDD)源/漏区离子注入后,可以对器件进行退火,以对注入的掺杂离子进行激活以及对离子注入造成的缺陷进行修复。HALO离子注入、LDD离子掺杂的目的是改善短沟道效应,防止载流子迁移率下降。其中合适的P型掺杂材料有In、B10H14或B18H22或BF3;N型掺杂材料为Sb、As2、P2或As4。
然后,进行HALO离子注入、LDD离子注入后,在所述第一侧墙105a的周围形成第二侧墙105b以作为主侧墙。本实施例中,第二侧墙105b可以是单层结构,其材料可以为氧化硅、氮化硅或氮氧化硅等绝缘材料,还可以为多层结构,例如为ONO(氧化硅-氮化硅-氧化硅)结构。本实施例中,第二侧墙的形成方法为本领域技术人员公知技术,在此不再赘述。
请继续参考图2A,在步骤S2中,以所述第二侧墙105b、第一侧墙105a和栅极104为掩膜,对所述第二侧墙105b两侧的衬底内进行源/漏极离子注入,形成源极和漏极。本实施例中,形成源极和漏极的方法为本领域技术人员公知技术,在此不再赘述。源/漏极离子注入之后通过尖峰脉冲退火实施源/漏极的退火。
其他实施例中,在步骤S1中,也可以不在栅极104和栅介质层103的周围形成第一侧墙,具体地:
在所述半导体衬底100上依次形成栅介质层103、多晶硅层104;
光刻并刻蚀所述多晶硅层、栅介质层103,在所述有源区表面上形成栅极104;
在所述有源区表面上形成围绕所述栅极104和栅介质层103的侧墙。
因此在步骤S2中,以所述侧墙和栅极为掩膜,对所述栅极两侧的有源区进行轻掺杂源/漏区离子注入和源/漏极离子注入,形成源极和漏极。
请参考图2B,步骤S3的目的是在源极、漏极和栅极的金属硅化物生长前,对源/漏极和栅极进行预非晶化处理,使源极、漏极和栅极的表面晶向打乱,有利于后续低电阻率的金属硅化物的形成,减少缺陷,降低后续形成的半导体器件中各晶体管间的阈值电压失配。本步骤的预非晶化处理106可以采用纯碳或者锗碳Ge/C或者Si的低温离子注入工艺完成,纯碳或者锗碳Ge/C或者Si离子注入相比现有技术中的纯Ge或者锗硅混合离子,可以更好的打乱源极、漏极和栅极的表面晶向,减少源极、漏极和栅极的表面硅与金属反应形成金属硅化物的障碍,获得晶片横向的不同区域上均匀一致的金属硅化物的。其中预非晶化离子注入的能量、剂量以及温度都非常关键,因为太高太低可能起不到预非晶化的作用或者增加了镍硅化物的缺陷生长,优选的,预非晶化离子注入工艺的注入能量为2KeV~7KeV,注入剂量为2E14~2E15/cm2,注入温度为-60℃~0℃。
请参考图2C,在步骤S4中,采用金属硅化物自对准工艺在预非晶化处理后的器件表面淀积金属,进行金属硅化,以在栅极104、源极和漏极表面形成所述金属硅化物107。较佳为所淀积的金属为钨、钛、钽、钯、锆、钴、铂和镍中的至少一种。本实施例中,所述金属硅化物107为镍硅化物。金属硅化物107可以形成欧姆接触,降低寄生电阻,调控阈值电压,保证了半导体器件中各晶体管的阈值电压的一致性。
请参考图2D,在本发明的其实施例中,可以继续进行后续的金属互连工艺,具体地,所述制作方法还包括:
在形成所述金属硅化物107的器件表面形成金属前介质层108;
在所述金属前介质层108中形成通孔(或称接触孔),通孔位置根据器件中各晶体管的电连接的要求选定,可以形成在栅极上方,也可以形成在源极、漏极上方;
在所述通孔中形成与金属硅化物接触的金属插塞109,金属插塞底部与金属硅化物107接触;
在形成金属插塞的器件表面形成金属层110。
上述的金属互连工艺为本领域技术人员公知技术,在此不再详述。
综上所述,本发明提供的半导体器件的制作方法,在栅极、源极和漏极表面形成金属硅化物之前,采用纯碳离子或者锗碳离子或者硅离子对所述栅极、源极和漏极的表面进行预非晶化处理,以减小器件的阈值电压的失配,来提高器件性能,适用于SRAM等CMOS器件的制作。
显然,本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种半导体器件的制作方法,其特征在于,包括:
提供一半导体衬底,在所述半导体衬底的各个有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙;
在栅极两侧的有源区中形成源极和漏极;
采用纯碳离子或者锗碳混合离子或者硅离子对所述栅极、源极和漏极的表面进行预非晶化处理;
采用金属硅化物工艺处理所述栅极、源极和漏极表面形成金属硅化物。
2.如权利要求1所述的制作方法,其特征在于,提供所述半导体衬底的步骤包括:
提供一基底,通过隔离结构隔离出多个有源区;
对所述基底进行阱离子注入,形成阱,并进行退火。
3.如权利要求1所述的制作方法,其特征在于,在所述半导体衬底的有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙的步骤包括:
在所述半导体衬底上依次形成栅介质层、多晶硅层;
光刻并刻蚀所述多晶硅层、栅介质层,在所述有源区表面上形成栅极;
在所述有源区表面上形成围绕所述栅极和栅介质层的第一侧墙;
以所述第一侧墙和栅极为掩膜,对所述栅极的两侧有源区进行轻掺杂源/漏区离子注入,形成轻掺杂源/漏结构;
在所述有源区表面上形成围绕所述第一侧墙的第二侧墙;
以所述第二侧墙、第一侧墙和栅极为掩膜,对所述栅极的两侧有源区的进行源/漏极离子注入,形成源极和漏极。
4.如权利要求1所述的制作方法,其特征在于,在所述半导体衬底的有源区表面上依次形成栅介质层、栅极以及围绕所述栅极的侧墙的步骤包括:
在所述半导体衬底上依次形成栅介质层、多晶硅层;
光刻并刻蚀所述多晶硅层、栅介质层,在所述有源区表面上形成栅极;
在所述有源区表面上形成围绕所述栅极和栅介质层的侧墙;
以所述侧墙和栅极为掩膜,对所述栅极两侧的有源区依次进行轻掺杂源/漏区离子注入和源/漏极离子注入,形成源极和漏极。
5.如权利要求3或4所述的制作方法,其特征在于,进行轻掺杂源/漏区离子注入之前或之后,还对所述栅极两侧的有源区进行HALO离子注入。
6.如权利要求3或4所述的制作方法,其特征在于,所述轻掺杂源/漏区离子注入和/或源/漏极离子注入之后,对所述栅极两侧的有源区进行退火处理。
7.如权利要求3或4所述的制作方法,其特征在于,所述各个有源区包括用于形成NMOS区和PMOS区;进行轻掺杂源/漏区离子注入和源/漏极离子注入时,先对NMOS区进行离子注入,再对PMOS区进行离子注入。
8.如权利要求1所述的制作方法,其特征在于,所述金属硅化物中的金属包括钨、钛、钽、钯、锆、钴、铂和镍中的至少一种。
9.如权利要求1所述的制作方法,其特征在于,所述预非晶化处理时,离子注入能量为2KeV~7KeV,离子注入剂量为2E14~2E15/cm2,离子注入温度为-60℃~0℃。
10.如权利要求1所述的制作方法,其特征在于,所述制作方法还包括:
在形成所述金属硅化物的器件表面形成金属前介质层;
在所述金属前介质层中形成通孔;
在所述通孔中形成与金属硅化物接触的金属插塞;
在形成金属插塞的器件表面形成金属层。
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