CN103794502A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
本发明公开了一种半导体器件制造方法,包括:在衬底上形成伪栅极堆叠结构;在衬底中伪栅极堆叠结构两侧形成源漏区,并且在衬底上伪栅极堆叠结构两侧形成栅极侧墙;去除伪栅极堆叠结构,形成栅极沟槽;在栅极沟槽中依次形成界面层、栅极绝缘层、盖帽层、栅极导电层、阻挡盖帽层;采用ALD法,在阻挡盖帽层上形成金属钨层。依照本发明的半导体器件及其制造方法,采用ALD法在金属栅极顶部沉积W层,有效改善了金属栅极薄膜台阶覆盖性,提升了器件的可靠性。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,特别是涉及一种采用原子层沉积(ALD)制备的金属钨(W)作为栅极盖帽层的半导体器件及其制造方法。
背景技术
MOSFET器件等比例缩减至45nm之后,器件需要高介电常数(高k)作为栅极绝缘层以及金属作为栅极导电层的堆叠结构以抑制由于多晶硅栅极耗尽问题带来的高栅极泄漏以及栅极电容减小。
后栅工艺目前广泛应用于先进IC制造,其通常是先去除假栅极,随后在留下的栅极沟槽中填充高k/金属栅(HK/MG)膜层的堆叠。HK和MK膜层的堆叠类型和厚度对于器件参数的确定是重要的,诸如阈值电压(Vt)、等效栅氧厚度(EOT)、平带电压(Vfb),此外对于高深宽比(AR)结构孔隙填充率也有影响。
现有技术中金属栅(MG)顶部通常是CVD、PVD等常规方法制备的AL、Mo等金属,然而其台阶覆盖性能较差,而且后续的CMP工艺较难控制对于小尺寸器件的超薄金属层厚度而言,CVD、PVD法制备的MG质量较差,无法适用于40nm以下的工艺。
发明内容
因此,本发明的目的在于克服上述困难,提供一种能有效提高金属栅可靠性的半导体器件及其制造方法。
本发明提供了一种半导体器件制造方法,包括:在衬底上形成伪栅极堆叠结构;在衬底中伪栅极堆叠结构两侧形成源漏区,并且在衬底上伪栅极堆叠结构两侧形成栅极侧墙;去除伪栅极堆叠结构,形成栅极沟槽;在栅极沟槽中依次形成界面层、栅极绝缘层、盖帽层、栅极导电层、阻挡盖帽层;采用ALD法,在阻挡盖帽层上形成金属钨层。
其中,去除伪栅极堆叠结构之前,还进一步包括形成应力衬层,覆盖源漏区、栅极侧墙、伪栅极堆叠结构。
其中,应力衬层为DLC、氮化硅及其组合,厚度为10~1000nm。
其中,去除伪栅极堆叠结构的步骤进一步包括:在整个器件上形成层间介质层;去除部分应力衬层,露出伪栅极堆叠结构顶部;去除伪栅极堆叠结构。
其中,形成界面层的方法是化学氧化法。
其中,在含有10ppm臭氧的去离子水中浸泡20s。
其中,栅极绝缘层为CVD、PVD、ALD法制备的高k材料,并且执行沉积后退火。
其中,盖帽层、阻挡盖帽层为TiN、TaN及其组合,栅极导电层为Al、TiAl、Ti、TiN、TaN、Ta及其组合。
依照上述方法制造的一种半导体器件,包括衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、栅极堆叠结构两侧衬底上的栅极侧墙,其特征在于:栅极堆叠结构依次包括界面层、高k的栅极绝缘层、盖帽层、栅极导电层、阻挡盖帽层以及金属钨层,其中金属钨层采用ALD法制备。
依照本发明的半导体器件及其制造方法,采用ALD法在金属栅极顶部沉积W层,有效改善了金属栅极薄膜台阶覆盖性,提升了器件的可靠性。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1至图13分别显示了依照本发明的半导体器件制作方法各步骤的剖面示意图;以及
图14为依照本发明的ALD法沉积W的示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果,公开了能有效提高金属栅可靠性的半导体器件及其制造方法。需要指出的是,类似的附图标记表示类似的结构,本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或工艺步骤。这些修饰除非特别说明并非暗示所修饰器件结构或工艺步骤的空间、次序或层级关系。
首先,参照图1,形成基础结构,也即在衬底上形成伪栅极堆叠结构、在伪栅极堆叠结构两侧的衬底中形成源漏区、在伪栅极堆叠结构两侧的衬底上形成栅极侧墙。提供衬底1,衬底1可以是体Si、绝缘层上Si(SOI)等常用的半导体硅基衬底,或者体Ge、绝缘体上Ge(GeOI),也可以是SiGe、GaAs、GaN、InSb、InAs等化合物半导体衬底,衬底的选择依据其上要制作的具体半导体器件的电学性能需要而设定。在本发明中,实施例所举的半导体器件例如为场效应晶体管(MOSFET),因此从与其他工艺兼容以及成本控制的角度考虑,优选体硅或SOI作为衬底1的材料。优选地,衬底1具有掺杂以形成阱区(未示出),例如PMOS器件中n衬底中的P-阱区。在衬底1上通过LPCVD、PECVD、HDPCVD、RTO等常规工艺沉积形成衬垫层2,其材质包括氮化物(例如Si3N4或SiNx,其中x为1~2)、氧化物(例如SiO或SiO2)或氮氧化物(例如SiON),并优选SiO2。衬垫层2用于稍后刻蚀的停止层,以保护衬底1,其厚度依照刻蚀工艺需要而设定。随后在衬垫层2上通过LPCVD、PECVD、HDPCVD、MBE、ALD、蒸发、溅射等常规工艺沉积形成伪栅极层3,其材质包括多晶硅、非晶硅、微晶硅、非晶碳、非晶锗等及其组合,用在后栅工艺中以便控制栅极形状。刻蚀衬垫层2与伪栅极层3,余下的堆叠结构构成伪栅极堆叠结构2/3。以伪栅极堆叠结构2/3为掩模,进行第一次源漏离子注入,在伪栅极堆叠结构两侧的衬底1中形成轻掺杂、浅pn结的源漏扩展区4L(也即LDD结构)。随后在整个器件表面沉积绝缘隔离材料并刻蚀,仅在伪栅极堆叠结构周围的衬底1上形成栅极侧墙5。栅极侧墙5的材质包括氮化物、氧化物、氮氧化物、DLC及其组合,其与衬垫层2和伪栅极层3材质均不同,便于选择性刻蚀。特别地,栅极侧墙5可以包括多层结构(未示出),例如具有垂直部分以及水平部分的剖面为L形的第一栅极侧墙,以及位于第一栅极侧墙水平部分上的高应力的第二栅极侧墙,第二栅极侧墙的材质可包括SiN或类金刚石无定形碳(DLC),应力优选大于2GPa。以栅极侧墙5为掩模,进行第二次源漏离子注入,在栅极侧墙5两侧的衬底1中形成重掺杂、深pn结的源漏重掺杂区4H。源漏扩展区4L与源漏重掺杂区4H共同构成MOSFET的源漏区4,其掺杂类型和浓度、深度依照MOSFET器件电学特性需要而定。
其次,参照图2,在整个器件上形成应力衬层。通过LPCVD、PECVD、HDPCVD、MBE、ALD、磁控溅射、磁过滤脉冲阴极真空弧放电(FCVA)技术等常规工艺,形成应力衬层6,覆盖了源漏区4、栅极侧墙5以及伪栅极层3。应力衬层6的材质可以是氧化硅、氮化硅、氮氧化硅、DLC及其组合。优选地,应力衬层6的材质是氮化硅,并且更优选地具有应力,其绝对值例如大于1GPa。对于PMOS而言,应力衬层6可以具有压应力,绝对值例如大于3GPa;对于NMOS而言,应力衬层6可以具有张应力,其绝对值例如大于2GPa。应力衬层6的厚度例如是10~1000nm。此外,层6还可以是DLC与氮化硅的组合,或者是掺杂有其他元素的氮化硅(例如掺杂C、F、S、P等其他元素以便提高氮化硅应力)。
参照图3,在整个器件上形成层间介质层(ILD)并且刻蚀露出应力衬层。通过旋涂、喷涂、丝网印刷、CVD等常规方法形成低k材料的ILD 7,其材质包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如二氧化硅、无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。采用回刻(湿法和/或干法刻蚀)、CMP等技术平坦化ILD 7和应力衬层6,直至暴露出伪栅极层3。
参照图4,去除伪栅极层3,留下栅极沟槽3T。对于多晶硅、非晶硅、微晶硅等Si基材质的伪栅极层3而言,可以采用TMAH湿法腐蚀,或者碳氟基气体等离子体干法刻蚀,去除伪栅极层3,直至露出衬垫层2,留下栅极侧墙5、应力衬层6和ILD 7包围的栅极沟槽3T。
参照图5,在栅极沟槽3T中沉积形成界面层8。优选地,通过HF基湿法腐蚀液去除氧化硅材质的衬垫层2,并清洗、干燥暴露出的衬底1表面,以减小沟道区表面缺陷。随后,在衬底1上栅极沟槽3T中形成界面层8。界面层8材质是氧化硅,其形成方法可以是PECVD、HDPCVD、MBE、ALD等常规方法,还可以是化学氧化方法,例如在含有10ppm臭氧的去离子水中浸泡20s,使得硅材质的衬底1表面被氧化形成氧化硅的界面层8。该薄层界面层用于降低衬底1与未来高k材料的栅极绝缘层之间的界面态密度。
参照图6,在ILD 7上以及栅极沟槽3T中形成高k材料的栅极绝缘层9。高k材料包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物,例如Al2O3、Ta2O5、Ti O2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))。形成方法可以是CVD、PVD、ALD等常规方法。随后,采用沉积后退火(PDA),例如在450℃下退火15s,以提高HK材料的质量。
参照图7,在栅极绝缘层9上沉积盖帽层10。沉积方法例如是CVD、PVD、ALD等,材质例如是TiN、TaN及其组合。盖帽层10可以阻挡上层的金属扩散到HK层9中。
参照图8,在盖帽层10上形成栅极导电层11。栅极导电层11用于调整栅极功函数,对于NMOS而言可以选用Al、TiAl、对于PMOS而言可以选用Ti、TiN、Ta、TaN。沉积方法例如是CVD、PVD、ALD等。
参照图9,在栅极导电层11上形成阻挡盖帽层12。形成方法例如是CVD、PVD、ALD等,其材质可以是TiN、TaN,用于调整金属栅极功函数以及势垒阻挡层。
参照图10,采用ALD法,在阻挡盖帽层12上形成金属W层13。
可选地,预热晶片,将晶片送入CVD反应室,加热至约200℃,提高整个晶片热量以促进分子运动,利于稍后的反应和沉积。
可选地,在晶片上沉积薄硅层(未示出)。通入硅烷(SiH4)等含硅气体,分解从而在晶片表面沉积形成了薄硅层,例如为单原子Si层,该单原子层Si可以保护其下方的Ti、Ta、TiN、TaN等材质的阻挡层/粘附层免受稍后WF6的侵蚀。
采用原子层沉积(ALD)工艺,在晶片上形成W层13。ALD工艺的前驱物包括硼烷(B2H6)与氟化钨(WF6),工艺温度为250~350℃并且优选300℃。具体地,参照图2所示,在ALD沉积的循环周期内:WF6最先沉积在晶片表面(优选地包括薄Si层)形成第一层W单原子层,并且W-F链上F一侧朝向上;随后停止通入WF6转而通入B2H6,B和H取代了W-F链上的F;接着停止通入B2H6转而继续通入WF6,第一层W上方的B和H还原了通入的WF6从而形成了第二层W单原子层;然后停止WF6转而通入B2H6,B和H再次取代了第二层W单原子层顶部的F,此后周而复始,间歇地交替通入WF6和B2H6,最终形成了多个W单原子层,构成最终的W层。ALD工艺中,沉积速率例如是/周期至/周期并且优选为/周期,最终沉积得到的W层13的厚度例如是10~并且优选是
在此ALD法步骤中形成的W层13,不同于以往CVD法制备的W层,台阶覆盖性有了显著提升,填洞的能力有效增强,有利于提高器件的可靠性。
参照图11,采用CMP等方法,平坦化层9~13,直至暴露ILD 7。
参照图12,形成源漏接触硅化物。在ILD 7中刻蚀形成源漏接触孔7C,直至暴露源漏区4(4H)。在接触孔7C中沉积Ni、Pt、Co、Ti等金属及其组合,退火使得金属薄层与源漏区中的Si反应形成源漏接触金属硅化物14。随后湿法刻蚀去除未反应的金属薄层。
参照图13,填充接触孔形成源漏接触。在接触孔7C中沉积1~7nm厚的TiN、TaN的阻挡层15,随后采用CVD或者ALD法沉积金属W、Al、Mo、Cu及其组合,形成源漏接触16。最后CMP或者回刻,直至暴露ILD7。
最终形成的器件结构如图13所示,包括衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区4、栅极堆叠结构两侧衬底上的栅极侧墙5,其特征在于栅极堆叠结构依次包括界面层8、高k的栅极绝缘层9、盖帽层10、栅极导电层11、阻挡盖帽层12以及金属W层13,其中金属W层13采用ALD法制备。对其余各个部件及其材料、几何参数在制造方法中已详细描述,在此不再赘述。
依照本发明的半导体器件及其制造方法,采用ALD法在金属栅极顶部沉积W层,有效改善了金属栅极薄膜台阶覆盖性,提升了器件的可靠性。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构和/或工艺流程做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (10)
1.一种半导体器件制造方法,包括:
在衬底上形成伪栅极堆叠结构;
在衬底中伪栅极堆叠结构两侧形成源漏区,并且在衬底上伪栅极堆叠结构两侧形成栅极侧墙;
去除伪栅极堆叠结构,形成栅极沟槽;
在栅极沟槽中依次形成界面层、栅极绝缘层、盖帽层、栅极导电层、阻挡盖帽层;
采用ALD法,在阻挡盖帽层上形成金属钨层。
2.如权利要求1的半导体器件制造方法,其中,去除伪栅极堆叠结构之前,还进一步包括形成应力衬层,覆盖源漏区、栅极侧墙、伪栅极堆叠结构。
3.如权利要求2的半导体器件制造方法,其中,应力衬层为DLC、氮化硅及其组合,厚度为10~1000nm。
4.如权利要求2的半导体器件制造方法,其中,去除伪栅极堆叠结构的步骤进一步包括:在整个器件上形成层间介质层;去除部分应力衬层,露出伪栅极堆叠结构顶部;去除伪栅极堆叠结构。
5.如权利要求1的半导体器件制造方法,其中,形成界面层的方法是化学氧化法。
6.如权利要求5的半导体器件制造方法,其中,在含有10ppm臭氧的去离子水中浸泡20s。
7.如权利要求1的半导体器件制造方法,其中,栅极绝缘层为CVD、PVD、ALD法制备的高k材料,并且执行沉积后退火。
8.如权利要求1的半导体器件制造方法,其中,盖帽层、阻挡盖帽层为TiN、TaN及其组合,栅极导电层为Al、TiAl、Ti、TiN、TaN、Ta及其组合。
10.一种半导体器件,包括衬底上的栅极堆叠结构、栅极堆叠结构两侧衬底中的源漏区、栅极堆叠结构两侧衬底上的栅极侧墙,其特征在于:栅极堆叠结构依次包括界面层、高k的栅极绝缘层、盖帽层、栅极导电层、阻挡盖帽层以及金属钨层,其中金属钨层采用ALD法制备。
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