TWI643342B - 用於ｐｍｏｓ整合之第ｉｖ族電晶體 - Google Patents

用於ｐｍｏｓ整合之第ｉｖ族電晶體 Download PDF

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TWI643342B
TWI643342B TW105122618A TW105122618A TWI643342B TW I643342 B TWI643342 B TW I643342B TW 105122618 A TW105122618 A TW 105122618A TW 105122618 A TW105122618 A TW 105122618A TW I643342 B TWI643342 B TW I643342B
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type
germanium
source
concentration
item
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TW105122618A
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TW201701481A (zh
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葛蘭 葛雷斯
Glenn Glass
安拿 莫希
Anand Murthy
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英特爾股份有限公司
Intel Corporation
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

所揭露之技術係用以形成第IV族電晶體裝置，其具有高鍺濃度之源極/汲極區域，且相對傳統裝置表現出降低的寄生電阻。在某些範例具體實施例中，源極/汲極區域之每一者包括薄的p型矽或鍺或矽鍺沉積，且源極/汲極材料沉積的剩餘物為p型鍺或鍺合金(例如鍺：錫或其他適合的應變誘導物，且具有至少80原子百分比的鍺含量及20原子百分比或更低的其他成分)。在某些情況中，應變鬆弛的證據可於富含鍺的蓋層中觀察到，包括錯位差排及/或穿透差排及/或雙晶。可使用許多電晶體組態，包括平面及非平面電晶體結構兩者(例如鰭式場效電晶體及奈米線電晶體)、以及應變及非應變通道結構。

Description

用於PMOS整合之第IV族電晶體
本發明係關於用於PMOS整合之第IV族電晶體。
電路裝置(包括電晶體、二極體、電阻、電容、及形成於半導體基板上的其他被動或主動電子裝置)增加的效能一般為在設計、製造、及操作這些裝置的過程中所要考量的主要因素。舉例來說，在金屬氧化物半導體(MOS)電晶體半導體裝置(例如在互補式金屬氧化物半導體(CMOS)中所使用者)的設計及製造或形成過程中，通常欲最小化關聯於接觸(亦稱作外部電阻Rext)的寄生電阻。降低的Rext能使相同電晶體的設計有更高的電流。
300‧‧‧基板
302‧‧‧閘極介電層
304‧‧‧閘極電極
306‧‧‧選擇性硬式遮罩
310‧‧‧間隙壁
312‧‧‧凹洞
312A‧‧‧頂端區域
313‧‧‧襯層
314‧‧‧凹洞
314A‧‧‧頂端區域
315‧‧‧襯層
318‧‧‧蓋層
318A‧‧‧源極頂端
320‧‧‧蓋層
320A‧‧‧汲極頂端
322‧‧‧絕緣體層
324‧‧‧高k閘極介電質層
325‧‧‧接觸電阻降低金屬
326‧‧‧金屬閘極電極
329‧‧‧接觸插塞金屬
400‧‧‧基板
410‧‧‧鰭
420‧‧‧STI層
430‧‧‧閘極介電質材料
440‧‧‧閘極電極
450‧‧‧硬式遮罩
460‧‧‧間隙壁
470‧‧‧凹槽
480‧‧‧磊晶襯層
490‧‧‧磊晶源極/汲極蓋層
510‧‧‧奈米線
511‧‧‧材料
580‧‧‧襯層
590‧‧‧蓋層
1000‧‧‧計算系統
1002‧‧‧主機板
1004‧‧‧處理器
1006‧‧‧通訊晶片
圖1示意地描述包括源極及汲極頂端區域之一典型MOS電晶體之電阻的構件；圖2為根據本發明之一具體實施例之用以形成第IV族電晶體之方法； 圖3A至3F根據本發明之各種具體實施例描述實施圖2之方法所形成之結構；圖4A至4G之每一者顯示根據本發明之一具體實施例所形成之FinFET電晶體結構的透視圖；圖5A及5B之每一者顯示根據本發明之一具體實施例所形成之奈米線電晶體結構的透視圖；以及圖6描述根據本發明之一具體實施例之以一或多個電晶體結構所實施之計算系統。
應理解，圖式未必是以等比例繪出或是意圖限制本發明於所示的特定組態。舉例來說，雖然某些圖式一般係顯示直線、直角、及平滑表面，但鑒於真實世界對所使用之處理設備及技術的限制，電晶體結構的實際實作可能具有較不完美的直線及/或直角，且某些特徵可能具有表面拓撲或是不平滑。簡言之，圖式僅被提供來顯示範例結構。
【發明內容及實施方式】
所揭露之技術係用以形成第IV族電晶體裝置，其具有高鍺濃度之源極/汲極區域，且相對傳統裝置表現出降低的寄生電阻。在某些範例具體實施例中，所產生之電晶體結構之源極/汲極區域之每一者包括薄的p型矽或鍺或矽鍺(SiGe)襯層，且源極/汲極材料的剩餘物為p型鍺或鍺合金，其包括例如鍺及錫，且具有至少80原子百分比的鍺含量(及20原子百分比或更低的其他成分，例如錫及/或其他適合的應變誘導物。在某些情況中，應變鬆 弛的證據可於此富含鍺之層中觀察到，其包括錯位差排及/或穿透差排。根據本發明，許多電晶體組態以及合適的製造程序將為顯而易見，其包括平面及非平面電晶體結構兩者(例如鰭式場效電晶體及奈米線電晶體)、以及應變及非應變通道結構。本發明技術特別適於實現p型MOS(PMOS)裝置，然而其他電晶體組態亦可受益。
概述
如前文所解釋，一般可藉由降低裝置外部電阻(Rext)而達成電晶體中增加的驅動電流。然而，PMOS電晶體效能為裝置內各種構件電阻的函數，如參照圖1所示。通道電阻R1可經由載子遷移率(其為通道內壓縮應變的函數)而調節。裝置的外部電阻Rext包括頂端電阻R2(頂端區域亦稱作源極/汲極延伸)、源極/汲極電阻R3、及接觸電阻R4(金屬至半導體)。所有這些分段電阻具有一材料構件(例如橫跨介面的能量屏障、載子濃度及遷移率)、幾何構件(例如長度、寬度等)、及動態電性負載構件(電流擁擠)。
因此，根據本發明某些具體實施例，以p型薄襯層及高含量的鍺(具有非常高的p型摻雜物濃度)來取代源極/汲極區域中的一般矽或SiGe合金材料係最小化外部電阻構件(R2、R3、及R4)。此外，藉由引入高度壓縮應變的材料，通道電洞遷移率係最大化或增加，因而降低通道電阻(R1)。降低的通道、頂端、源極/汲極及接觸電阻 的靜影響為在一給定電壓下(相對臨界電壓Vt，即V-Vt)之改善的電晶體電流。
在某些範例情況中，薄襯層為p型摻雜矽或鍺或SiGe合金，且一般小於總源極/汲極沉積層厚度的50%。剩餘的源極/汲極沉積層厚度一般大於總源極/汲極沉積層厚度的50%，且可例如為p型摻雜鍺或鍺合金，例如鍺：錫或鍺：錫：x(其中x例如為矽或其他微量的成分或基於製程/擴散的人為產物)，具有至少80原子百分比的鍺及20原子百分比或更少的其他成分(例如錫及/或任何其他合適的應變誘導物及/或其他微量無意的成分)。在某些特殊的此類範例具體實施例中，源極/汲極襯層與高濃度鍺蓋層的厚度比為約1：5或更低(其中襯層構成總源極/汲極沉積層厚度之約20%或更低)。在某些此類範例情況中，襯層的厚度為一到數個單分子層。
本技術可用以形成電晶體裝置於任何數量的裝置及系統。在某些具體實施例中，例如具有n型MOS(NMOS)及PMOS電晶體兩者的CMOS裝置，可由各種方式來達成選擇性。在一具體實施例中，舉例來說，在NMOS源極/汲極位置上的沉積可藉由在PMOS沉積過程中將NMOS區域屏蔽而避免。在其他具體實施例中，選擇性可包括自然選擇。舉例來說，雖然硼摻雜鍺生成於p型SiGe(或矽)源極/汲極上，但其並不生成於絕緣體表面(例如二氧化矽(SiO2)或氮化矽(SiN))上；其亦不生成於例如n型區域中的暴露重度磷摻雜矽上。
本文中所提供的技術可用以改善在任何數量的電晶體結構及組態中的裝置電阻，其包括平面、平齊式或抬升式源極/汲極、非平面(例如奈米線電晶體及鰭式電晶體，例如雙閘極及三閘極電晶體結構)、以及應變及非應變通道結構。源極/汲極區域可為凹陷(例如使用蝕刻製程)或非凹陷(例如形成於基板的頂表面)。此外，電晶體裝置可選擇性地包括源極及汲極頂端區域，其係設計以例如降低電晶體的整體電阻，同時改善短通道效應(SCE)，但此類頂端區域並非必需。電晶體裝置可更包括任何數量的閘極組態，例如多晶閘極、高k介電質金屬閘極、替換性金屬閘極(RMG)製程閘極、或任何其他閘極結構。任何數量的結構特徵可與本文所述的低電阻電晶體技術一同使用。
根據某些具體實施例，垂直於閘極線或二次離子質譜儀(SIMS)輪廓的穿透式電子顯微鏡(TEM)橫截面可用以顯示結構中的鍺濃度，因為矽及SiGe的磊晶合金的輪廓可容易地與高鍺濃度輪廓區別。在某些此類含矽基板的情況中，藉由捨棄用以維持應變(無差排)源極/汲極區域的一般需求，源極/汲極填充材料及矽通道之間的晶格維度不匹配對純鍺而言可增加至少2X，鍺-錫合金可增加更多。在差排出現於富含鍺之蓋層的情況中，雖然不是100%的應變都能夠轉移至通道，但後沉積熱處理可用以提供明確的電晶體效能(在給定V-Vt處的電流)增益，即使是鬆弛薄膜(如本文所述)，其係相對應變SiGe控 制。將理解到，鬆弛一般係表示薄膜可能具有錯位差排，但也可指包括差排形成及傳播的可塑鬆弛機制。彈性鬆弛的程序在非平面組態(例如FinFET(如三閘極)及奈米結構中變得可能，其中應變材料並未完全受到基板的限制。因此，平面內晶格常數具有更大的彈性來擴張或縮小，而不受基板的影響，且此程序不需錯位差排的形成及傳播。在本文中，鬆弛一詞係用於可塑鬆弛的意義上而非用於彈性鬆弛的意義上。使用錫或其他合適應變誘導物以形成本文所述之高濃度鍺蓋層的合金可選擇性地用以增加通道區域中的應變，藉此透過圖1中電阻R1的降低而更降低整體的裝置電阻。將理解到，雖然無缺陷的純鍺為理想的，但對例如矽基板或甚至具有50原子百分比鍺之SiGe基板上的沉積通常難以無缺陷地成長。然而，意外地，若比較一般完全應變SiGe層與具有某些缺陷(例如具有錯位及/或穿透差排)之此類富含鍺層的效能，則有缺陷的富含鍺層將表現較佳。將理解到，此結果一般並不直觀，因為其違背了傳統對薄膜的了解。無論如何，雖然本發明的某些具體實施例可能包括缺少晶格特徵(例如錯位差排、穿透差排及雙晶(缺陷係源於橫跨雙晶平面之晶格方位中的改變))的富含鍺蓋層，但其他具體實施例可包括具有一或多個此類特徵的富含鍺蓋層。
結構及方法學
圖2為根據本發明之一具體實施例之用以形成第IV 族電晶體之方法。圖3A至3F根據本發明之各種具體實施例描述實施圖2之方法所形成之範例結構。一或多個此類電晶體可形成於例如處理器、通訊晶片或記憶體晶片的製造中。此類積體電路可接著用於各種電子裝置及系統中。
範例方法包括形成一或多個閘極堆疊於半導體基板上，其中MOS裝置可形成於基板上(202)。MOS裝置可包含例如PMOS電晶體、或NMOS及PMOS電晶體兩者(例如CMOS裝置)。圖3A顯示所產生的一範例結構，其在此情況中包括形成於基板300上之PMOS電晶體。可看出閘極堆疊係形成於通道區域之上，且包括閘極介電層302、閘極電極304、及選擇性硬式遮罩306。間隙壁310係鄰接閘極堆疊而形成。
閘極介電質302可例如為任何適合的氧化物，例如二氧化矽(SiO2)或高k閘極介電質材料。舉例來說，高k閘極介電質材料的範例包括氧化鉿、氧化矽鉿、氧化鑭、氧化鋁鑭、氧化鋯、氧化矽鋯、氧化鉭、氧化鈦、氧化鈦鍶鋇、氧化鈦鋇、氧化鈦鍶、氧化釔、氧化鋁、氧化鉭鈧鉛、及鈮酸鋅鉛。在某些具體實施例中，當使用高k材料時，可在閘極介電層302上實行退火程序以改善其品質。在某些特定範例具體實施例中，高k閘極介電質302可具有範圍在5Å至100Å厚的厚度(例如10Å)。在其他具體實施例中，閘極介電質302可具有一單分子層氧化材料的厚度。一般來說，閘極介電質302的厚度應足以將閘極 電極304與源極及汲極接觸電性地隔離。在某些具體實施例中，可於高k閘極介電質302上執行額外的程序，例如退火程序，以改善高k材料的品質。
閘極電極304的材料可例如為多晶矽、氮化矽、碳化物、或金屬層(例如鎢、氮化鈦、鉭、氮化鉭)，然而也可使用其他合適的閘極電極材料。在某些具體實施例中，閘極電極304材料可為稍後在替換性金屬閘極(RMG)製程移除的一犧牲層，其厚度在約10Å至500Å(例如100Å)的範圍。
選擇性閘極硬式遮罩層306可用以在製造過程中提供某些益處或使用，例如保護閘極電極304免於後續的蝕刻及/或佈植製程。硬式遮罩層306可使用一般的硬式遮罩材料形成，例如二氧化矽、氮化矽、及/或習知的絕緣體材料。
閘極堆疊可由習知方式形成或使用任何合適的客製化技術形成(例如習知的圖案化製程以蝕刻除去部份的閘極電極及閘極介電質層，以形成圖2A所示的閘極堆疊)。閘極介電質302及閘極電極304材料之每一者可例如使用習知的沉積製程而形成，例如化學汽相沉積(CVD)、分子層沉積(ALD)、旋塗沉積(SOD)、或物理汽相沉積(PVD)。也可使用其他沉積技術，舉例來說，閘極介電質302及閘極電極304材料可為熱成長。根據本說明書內容可理解到，可使用任何數量的其他合適材料、幾何、或形成製程來實施本發明的具體實施例，以提供本文所述的 低電阻電晶體裝置或結構。
間隙壁310可例如使用習知的材料而形成，例如氧化矽、氮化矽、或其他合適的間隙壁材料。間隙壁310的寬度一般可基於所形成電晶體的設計需求而選擇。然而，根據某些具體實施例，間隙壁310的寬度並不受到源極及汲極頂端區域之形成所造成的設計限制，其假設在源極/汲極頂端區域有足夠高的p型摻雜鍺含量(例如摻雜硼的鍺)或SiGe合金襯層。
可使用任何數量的合適基板來實施基板300，包括塊狀基板、絕緣層上半導體基板(XOI，其中X為半導體材料，例如矽、鍺、或富含鍺的矽)、及多層結構，包括在隨後閘極圖案化製程之前可形成鰭式或奈米線於其上的那些基板。在某些特定範例情況中，基板300為鍺或矽或SiGe塊狀基板、或是鍺或矽或SiGe於氧化物基板上。雖然本文描述了可形成基板300之材料的幾個範例，但可作為建立低電阻電晶體裝置於其上之基礎的其他合適材料也在所主張之本發明的精神及範疇。
再參考圖3A，在形成一或多個閘極堆疊後，方法繼續某些選擇性的處理，在此範例具體實施例中包括蝕刻電晶體結構的源極/汲極區域(204)，以及去除結構之任何NMOS源極/汲極區域的遮罩(若有的話)(206)。將理解到，源極/汲極區域不需為凹陷或以其他方式蝕刻。在此情況中，源極/汲極材料可形成於基板300上而不需任何蝕刻。根據某些具體實施例，雖然此非凹陷源極/汲極 區域將不影響通道電阻，仍可實施具有薄襯層及高鍺含量蓋層的雙層源極/汲極結構，以提供低接觸電阻。更將理解到，並非所有具體實施例都包括n型區域。在某些範例情況中，舉例來說，所製造的電路可僅包括PMOS裝置。在此類範例情況中，無n型源極/汲極區域要被去除遮罩。當出現n型區域，可使用任何適合的遮罩技術，以在p型處理過程中保護n型區域。
在源極/汲極區域被蝕刻的範例具體實施例中，產生源極/汲極凹洞312/314，如圖3A所示。凹洞有效地定義源極/汲極區域的位置。可進一步看出，基板300不僅已被蝕刻而產生源極/汲極凹洞312/314，也產生了底切閘極介電質302之其個別的頂端區域312A/314A。凹洞312/314及其個別的頂端區域312A/314A可使用任何數量的合適製程而以習知方式形成。在某些範例情況中，這包括離子佈植以高度地摻雜鄰接閘極堆疊之部份的基板300，接著退火以驅使摻雜物更進入基板300，以改善預期源極/汲極區域的蝕刻速率。接著，可使用乾蝕刻製程來蝕刻基板300的摻雜區域，以形成凹洞312/314及其個別的頂端區域312A/314A。在完成乾蝕刻製程後，可例如使用濕蝕刻以清潔及進一步地蝕刻凹洞312/314及其個別的頂端區域312A/314A。此類濕蝕刻可使用習知或客製的濕蝕刻化學劑而實行，其可用以移除污染物，例如碳、氟、氟氯碳、及氧化物(例如氧化矽)，以提供後續製程可實施於其上的乾淨表面。此外，假設一單晶矽表面，濕 蝕刻也可用以沿<111>及<001>結晶面來移除薄的部份基板300，以提供平滑表面，其中高品質磊晶沉積可發生於其上。在某些範例情況中，被蝕刻移除之薄的部份基板300可例如高達5奈米厚，且可移除殘留的污染物。濕蝕刻一般會造成凹洞312/314及其個別頂端區域312A/314A的邊緣沿著<111>及<001>結晶面。
進一步參考圖2，方法繼續沉積p型矽或鍺或SiGe襯層313/315於p型源極/汲極區域(208)，且接著在襯層313/315之上沉積p型鍺或鍺合金於p型源極/汲極區域中(210)。這些沉積之每一者可例如使用選擇性磊晶沉積而實現，然而可使用任何合適的沉積製程。參考圖3B可看出，p型矽或鍺或SiGe襯層313/315係沉積於凹洞312/314及其個別頂端區域312A/314A中。此外，如圖3C所示，凹洞312/314及其個別頂端區域312A/314A係進一步地填充以提供p型鍺或鍺合金的厚蓋層318/320於p型襯層313/315之上。將理解到，p型摻雜物的範例包括例如硼、鎵、或任何其他合適的p型摻雜物，且所主張之本發明並不意欲受限於任何特定一種。
根據基板300為矽或SiGe塊狀基板、或絕緣層上半導體基板(XOI，其中X為矽或SiGe)之某些特定範例具體實施例，源極及汲極凹洞312/314及其個別頂端區域312A/314A係以原位硼摻雜之矽或SiGe填充，藉以形成對應的襯層313/315，並接著以原位硼摻雜之鍺或富含鍺的合金進一步填充，以形成蓋層318/320。在基板300為 鍺塊狀基板或絕緣層上鍺基板的其他範例具體實施例中，源極及汲極凹洞312/314及其個別頂端區域312A/314A可以原位硼摻雜之富含鍺的合金(例如鍺：錫)填充，藉以形成對應的襯層313/315，並接著以原位硼摻雜之富含鍺合金進一步填充，以形成蓋層318/320。根據本說明書內容可理解到，襯層313/315及蓋層318/320的個別鍺或p型摻雜物濃度可根據例如以下因素而變化：基板300的組成、晶格匹配/相容性之漸次變化的使用、以及總源極/汲極沉積的整體理想厚度。根據本說明書內容可理解到，可實施許多材料系統及p型摻雜組態。
舉例來說，在具有矽或鍺或SiGe基板的某些範例具體實施例中，襯層313/315的鍺含量可在20原子百分比至100原子百分比的範圍中，且硼濃度在1E20cm-3至2E21cm-3的範圍中。根據某些具體實施例，為避免晶格與底下的含矽基板不匹配，襯層313/315的鍺濃度可漸次變化。舉例來說，在一此類具體實施例中，襯層313/315可為一漸次變化的硼摻雜SiGe層，其具有從相容於底下矽或SiGe基板300之一基準濃度漸次變化至100原子百分比(或接近100原子百分比，例如超過90原子百分比或95原子百分比或98原子百分比)的鍺濃度。在一特定的此類具體實施例中，鍺濃度的範圍從40原子百分比或更低到超過98原子百分比。襯層313/315內的硼濃度可例如固定在一高位準或者可漸次變化。舉例來說，襯層313/315內的硼濃度可從等於或相容於底下基板300之一 基準濃度漸次變化到一理想高濃度(例如，超過1E20cm-3、2E20cm-3、或5E20cm-3)而。在某些此類具體實施例中，硼摻雜鍺蓋層318/320具有超過1E20cm-3(例如超過2E20cm-3或2E21cm-3或更高)的硼濃度。此蓋層318/320中的硼濃度可以類似於參照襯層313/315所描述的方式漸次變化。更一般地來說，硼濃度可依需要調整，以提供所需的傳導率等級，其可根據本說明書內容而理解。舉例來說，蓋層318/320的鍺濃度可固定於100原子百分比。或者，根據本說明書內容可理解到，蓋層318/320的鍺濃度可從低至高濃度(例如從20原子百分比至100原子百分比)漸次變化，以考量到襯層313/315與蓋層318/320之理想峰值鍺濃度之間的晶格不匹配。在其他具體實施例中，蓋層318/320可由鍺合金來實施，其中混合物可例如為高達80原子百分比的鍺以及高達20原子百分比的合金材料(其在某些具體實施例中為錫)。需注意，將理解到，錫濃度(或其他合金材料)也可漸次變化。在一此情況中，當蓋層318/320中的錫濃度範圍在3至8原子百分比，通道應變將增加(蓋層318/320之平衡原子百分比實質為鍺及任何梯度材料)。儘管鬆弛，晶格常數仍舊相對為大，且能夠施予足夠的應變於鄰接的通道。其他合適的錫濃度為顯而易見，其他合適的應變誘導物亦是。
需注意，使用純鍺基板下，襯層313/315可由鍺來實現且不需漸次變化。在某些此類情況中，襯層313/315的鍺濃度可為固定(例如100原子百分比)且蓋層318/320 可由鍺合金(例如鍺：錫、或前述之其他合適的鍺合金)來實現。如前文所解釋，蓋層318/320中的鍺濃度(或錫或其他合金材料濃度)可漸次變化以產生理想的通道應變。在某些此類的情況中，需進一步注意，鍺襯層313/315可有效地與鍺合金蓋層318/320整合或可為源極/汲極區域沉積之一無法偵測的組件。
有關漸次變化，需注意到本文中所使用的相容性並不需要在濃度等級上重疊(舉例來說，底下基板300的鍺濃度可為0至20原子百分比，且襯層313/315的初始鍺濃度可為30至40原子百分比)。此外，如本文所使用，有關濃度等級的「固定」一詞意指相對不變的濃度等級(例如層中最低濃度等級為在該層內之最高濃度等級的10%)。在更一般的意義上，固定的濃度等級係意指缺乏故意的漸次變化濃度等級。
襯層313/315及蓋層318/320的厚度也可隨以下因素而變化：基板300的組成、晶格匹配/相容性之漸次變化的使用、以及總源極/汲極沉積的整體理想厚度。一般來說，在襯層313/315組態為具有漸次變化的鍺含量以提供與不具有或具有低鍺含量之基板300的相容性的情況下，襯層313/315可較厚。在其他情況中，當基板300為鍺基板或者含有相對高濃度的鍺，襯層313/315不需漸次變化，因此可相對較薄(例如一至數個單分子層)。在其他情況中，當基板300不含或具有相對低的鍺含量，襯層313/315可由相對薄的矽層或低鍺含量材料層來實施，且 蓋層318/320的鍺含量可依相容性所需而漸次變化。在任何此類情況中，襯層313/315一般構成少於50%的總源極/汲極沉積層厚度，且剩餘的源極/汲極沉積層厚度一般大於50%的總源極/汲極沉積層厚度。根據某些此類範例具體實施例，當襯層313/315未漸次變化，襯層313/315對蓋層318/320的厚度比為約2：5或更低(即襯層構成總源極/汲極沉積層厚度的約40%或更低)。在某些特定的此類具體實施例中，襯層313/315對蓋層318/320的厚度比為約1：5或更低(即襯層構成總源極/汲極沉積層厚度的約20%或更低)。在一此類特定範例情況中，襯層313/315的厚度在1至數個單分子層到約10奈米的範圍中，且總源極/汲極沉積層厚度在50至500奈米的範圍。根據本說明內容可清楚有許多源極/汲極襯層及蓋層幾何及材料組態。
根據本說明書內容將理解到，本發明具體實施例可實施任何數量的其他電晶體特徵。舉例來說，通道可為應變或非應變，且源極/汲極區域可包括或不包括形成於對應源極/汲極區域及通道區域之間的頂端區域。從這個意義來說，不論電晶體結構具有應變或非應變通道、或具有源極/汲極頂端區域或不具源極/汲極頂端區域，都與本發明各種具體實施例不特別相關，且所主張之本發明並不意欲受限於任何特定之此類結構特徵。相反地，任何數量的電晶體結構及種類，特別是那些具有p型或n型及p型兩者之源極/汲極電晶體區域的結構，將從使用具有本文所述 之襯層及高鍺濃度蓋層之雙層源極/汲極組態而受益。
可使用CVD製程或其他合適的沉積技術來進行沉積(208及210)。舉例來說，208及210的沉積可於CVD反應器、LPCVD反應器、或超高真空CVD(UHVCVD)中實行。在某些範例情況中，反應器溫度可例如落於600℃至800℃之間，且反應器壓力可例如落於1至760托耳之間。載子氣體可例如包括氫或氦，其具有適當的流速，例如在10至50SLM之間。在某些特定具體實施例中，可使用鍺源前驅物氣體(例如在H2中稀釋的GeH4(舉例來說，GeH4可稀釋為1-20%))來實行沉積。舉例來說，稀釋的GeH4可在1%濃度及流速範圍在50至300SCCM之間使用。針對硼的原位摻雜，可使用稀釋的B2H6(例如B2H6可在H2中稀釋為1-20%)。舉例來說，稀釋的B2H6可在3%濃度及流速範圍在10至100SCCM之間使用。在某些範例情況中，可加入蝕刻劑，以增加沉積的選擇性。舉例來說，可加入流速範圍在例如50至300SCCM之間的HCI或Cl2。
根據本說明書內容，源極/汲極雙層結構上的各種變化將為顯而易見。舉例來說，在某些具體實施例中，襯層313/315係由磊晶沉積的硼摻雜SiGe所實施，其可為一或多層且具有範圍在30至70原子百分比或更高的鍺濃度。如前文所解釋，此SiGe襯層的鍺濃度可為固定或漸次變化，以從基準(接近基板300)增加至高位準(例如超過50原子百分比，接近蓋層318/320之鍺濃度的基準濃度， 鍺持續漸次變化至100原子百分比)。在某些此類具體實施例中的硼濃度可超過1E20 cm-3，例如高於5E20 cm-3或2E21 cm-3，且亦可漸次變化以從接近基板300的基準增加至高位準(例如超過1E20 cm-3或2E20 cm-3或3E20 cm-3等，接近蓋層318/320)。在硼摻雜SiGe襯層313/315的鍺濃度為固定的具體實施例中，可使用薄的漸次變化緩衝以較佳地連接襯層313/315與硼摻雜蓋層318/320。需注意，此緩衝可為一中間層或整合至蓋層318/320的成分中。為了此揭露的目的，此緩衝可視為蓋層318/320的部份。根據某些特定範例具體實施例，硼摻雜SiGe沉積層(或層的集合)313/315的厚度可例如在數單分子層至50奈米的範圍，而層(或層的集合)318/320可具有範圍在例如51至500奈米的厚度，然而其他具體實施例可具有其他的襯層及蓋層厚度，其根據本說明書內容將為顯而易見的。在某些具體實施例中，需注意到凹洞312/314可在循環的沉積-蝕刻製程過程中產生於間隙壁底下，且這些凹洞312/314也可由磊晶蓋層回填(其可例如具有與硼摻雜鍺蓋層318/320相同的成分)。
鑒於本說明書內容將更理解到，高鍺濃度(例如超過50原子百分比且高達純鍺)及高硼濃度(例如超過1E20cm-3)的組合(如本文所討論)可用以主要地實現在PMOS電晶體裝置中之源極及汲極區域(圖1中的R3)以及其個別的頂端區域(圖1中的R2)中較高的傳導率。此外，如前文所解釋，因為相對於低鍺成分層，硼擴散在 高鍺成分層中係足夠地被抑制，儘管在沉積應力源薄膜中的高摻雜濃度，當相較於具有相同p型摻雜物種類及摻雜等級之較低鍺成分層，可以後續的熱退火實現較少不利的SCE退化。在接觸表面的較高鍺濃度(其造成圖1中的較低接觸電阻R4)也致能了阻障高度降低。在某些範例具體實施例中，可使用超過80原子百分比以及高達純鍺(100原子百分比)的鍺濃度來達成此益處。然而，需注意到純鍺並非必須。舉例來說，某些具體實施例可具有超過90或95原子百分比(但不是純的)的鍺濃度。
參考圖3C可進一步看出，在相對靠近通道區域中形成源極/汲極頂端318A/320A亦施予較大的流體靜力應力於通道上。此應力增加通道內的應變，藉此而增加通道中的遷移率並增加驅動電流。在含矽基板的情況中，此應力可進一步藉由增加源極/汲極頂端318A/320A的鍺濃度而放大，而在鍺基板的情況中可藉由增加錫濃度而放大。這是對擴散為基礎的製程的改善，其中頂端區域一般不包括應變於通道區域上。
一旦根據本發明具體實施例填充源極及汲極區域，可實行各種習知的MOS製程以完成MOS電晶體的製造，例如替代性閘極氧化物製程、替代性金屬閘極製程、退火、及矽化金屬沉積製程，其可進一步更改電晶體及/或提供必需的電性互連。舉例來說，在源極/汲極區域與其個別頂端的磊晶沉積後，進一步參考圖2，方法可繼續從n型區域移除任何遮罩並依所需處理這些區域(若可應用，例 如在CMOS製程)(212)，且沉積絕緣體於電晶體之上(214)，且接著以一般的做法平面化該絕緣體層。絕緣體層可使用習知適用於積體電路結構之絕緣體層的材料，例如低k介電質(絕緣體)材料。此絕緣體材料包括例如氧化物(如二氧化矽(SiO2)及碳摻雜氧化物(CDO))、氮化矽、有機聚合物(例如八氟環丁烷、聚四氟乙烯)、氟矽玻璃(FSG)、及有機矽酸鹽(例如半矽氧烷、矽氧烷、或有機矽酸鹽玻璃)。在某些範例組態中，絕緣體層可包括細孔或其他孔洞，以進一步降低其介電質常數。圖3D描述沉積絕緣體層322並接著將其平面化至硬式遮罩306的一範例。
參考圖3D'可進一步看出，本發明的某些具體實施例使用一替代性金屬閘極製程，且方法可包括使用習知的蝕刻製程移除閘極堆疊(包括高k閘極介電質層302、犧牲閘極電極304、及硬式遮罩層306)。在另一實施中，僅移除犧牲閘極304。若移除閘極介電質302，則方法可包括沉積新的閘極介電質層至溝渠開口。在此可使用任何合適的高k介電質材料(如前文所描述)，例如氧化鉿。也可使用相同的沉積製程。可使用閘極介電質302的取代，以例如解決在乾式及濕式蝕刻製程的應用過程中發生在最初閘極介電質層的任何損壞，及/或以高k或其他理想的閘極介電質材料來取代低k或犧牲介電質材料。方法接著可繼續沉積金屬閘極電極層至溝渠中及閘極介電質層之上。可使用習知的金屬沉積製程以形成金屬閘極電極層， 例如CVD、ALD、PVD、無電電鍍、或電鍍。金屬閘極電極層可包括例如p型功函數金屬，例如釕、鈀、鈷、鎳、及導電金屬氧化物(例如氧化釕)。在某些範例組態中，可沉積二或更多金屬閘極電極層。舉例來說，可沉積功函數金屬，接著沉積合適的金屬閘極電極填充金屬，例如鋁。圖3D'描述根據本發明一具體實施例之一範例高k閘極介電質層324以及金屬閘極電極326，其已沉積至溝渠開口中。需注意，若需要的話，此RMG程序可在製程中的不同時間點實行。
進一步參考圖2，在形成絕緣體層322後(及任何所需的預先接觸形成RMG製程)，方法繼續蝕刻以形成源極/汲極接觸溝渠(216)。可使用任何合適的乾式及/或濕式蝕刻製程。圖3E顯示根據一範例具體實施例之在完成蝕刻後的源極/汲極接觸溝渠。
接著，方法繼續沉積接觸電阻降低金屬及退火(218)，接著沉積源極/汲極接觸插塞(220)。圖3F顯示接觸電阻降低金屬325，其在某些具體實施例中包括銀、鎳、鋁、鈦、金、金-鍺、鎳-鉑、或鎳-鋁、及/或其他此類電阻降低金屬或合金。圖3F更顯示接觸插塞金屬329，其在某些具體實施例中包括鋁或鎢，然而可使用任何合適的導電接觸金屬或合金，例如銀、鎳-鉑或鎳-鋁或鎳及鋁的其他合金、或鈦，其使用習知的沉積製程。源極/汲極接觸的金屬化可例如使用鍺化製程(一般來說，接觸金屬的沉積及後續的退火)。舉例來說，可使用具有 鎳、鋁、鎳-鉑或鎳-鋁或鎳及鋁的其他合金、或鈦的鍺化(包含或不包含鍺預非晶佈植)來形成低電阻鍺化物。硼摻雜鍺蓋層318/320允許金屬-鍺化物形成(例如鎳-鍺)。鍺化物允許比傳統金屬-矽化物系統明顯較低的蕭特基-阻障高度及改善的接觸電阻。舉例來說，傳統的電晶體一般使用源極/汲極SiGe磊晶製程，其鍺濃度的範圍在30至40原子百分比。此傳統的系統展現約140歐姆-微米的Rext值，受限於磊晶/矽化物介面電阻，其為高且可能阻礙未來的閘極節距縮放。本發明的某些具體實施例允許PMOS裝置中Rext的顯著改善(例如2x或更佳的改善，例如約70歐姆-微米或更低的Rext)，其可較佳地支援PMOS裝置縮放。因此，相較於傳統的電晶體，具有組態為如本文所述之雙層源極/汲極結構之源極/汲極的電晶體可展現相對較低的Rext值。
非平面組態
非平面架構可例如使用鰭式電晶體或奈米線組態而實施。FinFET為圍繞一半導體材料薄條(一般稱作鰭)而建立的電晶體。電晶體包括標準場效電晶體(FET)節點，包括閘極、閘極介電質、源極區域、及汲極區域。裝置的傳導通道位在閘極介電質底下、鰭的外側之上/之內。特別地，電流沿鰭的兩側壁(垂直基板平面之側)流動，也沿鰭的頂部(平行基板平面之側)流動。因為此組態的傳導通道主要位在沿鰭的三個不同的外部、平面區 域，此一FinFET設計有時稱作三閘極FinFET。其他類型的FinFET組態也可使用，例如所謂的雙閘極FinFETs，其中傳導通道主要僅位於沿鰭的兩側壁(沒有沿著鰭的頂部)。
圖4A至4G之每一者顯示根據本發明一具體實施例形成之FinFET電晶體結構的透視圖。將理解到，前文有關圖2至圖3F的討論同樣可用於此處。可看出，圖4A所示之範例非平面組態係以鰭式結構來實施，包括基板400，其具有半導體本體或鰭410從基板400延伸通過淺溝渠隔離(STI)層420。基板可例如為矽、鍺、或SiGe。
圖4B顯示形成於鰭410之三個表面之上的閘極電極440，以形成三個閘極(因此為三閘極裝置)。閘極介電質材料430係形成於鰭410與閘極電極440之間，且硬式遮罩450係形成於閘極電極440的頂部。圖4C描述在沉積絕緣材料及後續蝕刻(其留下絕緣體材料之覆層於所有垂直表面上，以形成間隙壁460)後所產生的結構。
圖4D描述在額外蝕刻處理後所產生的結構，其從鰭410的側壁消除了多餘的絕緣/間隙壁材料，而僅留下間隙壁460在閘極電極440的相對側壁。圖4E描述在凹槽蝕刻後所產生的結構，其移除了基板400之源極/汲極區域中的鰭410，從而形成凹槽470。需注意，其他具體實施例可無凹槽(例如源極/汲極區域與STI層420對齊)。
圖4F描述在磊晶襯層480生長後所產生的結構，其 可為薄、p型並含相當大部份的矽(例如矽或具有70原子百分比矽的SiGe)、或為純鍺(例如鍺的分隔層、或整合至或包含於蓋層318/320的成分中之不可偵測層)。圖4G描述在成長磊晶源極/汲極蓋層490後所產生的結構，其可為p型且主要包含鍺，但可包含少於20原子百分比的錫或其他合適的合金材料，如前文所解釋。根據本說明書內容將可理解到，可使用習知的製程及形成技術以製造本文所述之具有雙層源極/汲極結構FinFET電晶體結構。
將進一步理解到，需注意，所示三閘極組態的替代物為雙閘極架構，其包括介電質/隔離層於鰭410的頂部。更需注意，構成圖4G所示之源極/汲極區域之襯層480及蓋層490的範例外形並不意欲限制所主張之本發明於任何特定的源極/汲極種類或形成製程，且根據本說明書內容，其他源極/汲極外形為顯而易知的(例如可實施圓形、方形或矩形源極/汲極區域)。
圖5A顯示根據本發明一具體實施例而形成之奈米線電晶體結構的透視圖。奈米線電晶體(有時稱作環繞式閘極FET)係類似地組態為以鰭為基礎的電晶體，但使用奈米線來代替鰭，且閘極材料一般圍繞通道區域的所有側。根據特定的設計，某些奈米線電晶體具有例如四個等效閘極。圖5A描述具有兩個奈米線510的奈米線通道架構，然而其他具體實施例可具有任何數量的線。奈米線510可由例如p型矽或鍺或SiGe奈米線來實施。可看出，一奈 米線510係形成或提供於基板400的凹陷處，且其他奈米線510係等效地漂浮在包含襯層580及蓋層590的源極/汲極材料雙層結構中。如同鰭式組態，需注意可由本文所述之源極/汲極材料的雙層結構取代源極/汲極中的奈米線510(例如相對薄的矽或鍺或SiGe襯層以及相對厚的高濃度鍺蓋層)。或者，雙層結構可形成於最初所形成之奈米線510周圍，如圖所示(其中襯層580係形成於奈米線510周圍，且蓋層590接著形成於襯層580的周圍)。圖5B也描述具有多個奈米線510的奈米線組態，但在此範例中，根據本說明書內容可理解，在奈米線形成過程中，非活性材料511沒有從個別的奈米線之間移除，其可使用各種習知的技術來實行。因此，一奈米線510係形成於基板400的凹陷處，而另一奈米線510係等效地位於材料511的頂部。需注意，奈米線510通過通道而作用，但511材料則無。可看出，襯層580及蓋層590的雙層源極/汲極結構係圍繞奈米線510的所有其他暴露表面。
範例系統
圖6描述一計算系統1000，其係以根據本發明範例具體實施例而組態之一或多個電晶體結構而實施。可看出，計算系統1000內含一主機板1002。主機板1002可包括一些組件，其包括但不限於處理器1004及至少一通訊晶片1006，其每一者可物理地及電性地耦合至主機板1002，或是整合於其中。將理解到，主機板1002可例如 為任何印刷電路板，不論是主板、架設於主板上的子板、或僅系統1000的板等。根據其應用，計算系統1000可包括一或多個其他組件，其可或可不物理及電性地耦合至主機板1002。這些其他組件可包括但不限於揮發性記憶體(如DRAM)、非揮發性記憶體(如ROM)、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編解碼器、視頻編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速度計、陀螺儀、揚聲器、相機、大量儲存裝置(如硬碟驅動、光碟(CD)、數位多功能光碟(DVD)等)。計算系統1000所包括的任何組件可包括一或更多本文所述的電晶體結構(例如具有雙層源極/汲極結構，其包含相對薄的p型矽或鍺或SiGe襯層及相對較厚的p型高鍺含量蓋層)。這些電晶體結構可用以例如實施機載處理器快取或記憶體陣列。在某些具體實施例中，多重函數可整合至一或多個晶片(例如，需注意通訊晶片1006可為處理器1004的部份或整合至處理器1004)。
通訊晶片1006係致能往返計算系統1000之資料轉移的無線通訊。「無線」及其衍生物可用以描述電路、裝置、系統、方法、技術、通訊通道等，其可透過經由非固態媒體之調節電磁輻射的使用來通訊資料。此術語不表示相關裝置不含任何電線，然而其在某些具體實施例中可能不含。通訊晶片1006可實現任何數量的無線標準或協 定，包括但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期進化(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生物、以及指定為3G、4G、5G或更高之任何其他無線協定。計算系統1000可包括複數個通訊晶片1006。舉例來說，第一通訊晶片1006可專用於較短範圍的無線通訊，例如Wi-Fi及藍芽，而第二通訊晶片1006可專用於較長範圍無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
計算系統1000的處理器1004包括封裝於處理器1004之內的積體電路晶粒。在本發明某些具體實施例中，處理器的積體電路晶粒包括內建記憶體電路，其以一或多個本文所述之電晶體結構(如PMOS或CMOS)所實施。「處理器」一詞可指任何裝置或一裝置的部份，其處理例如來自暫存器及/或記憶體的電子資料並轉換電子資料為可儲存於暫存器及/或記憶體的其他電子資料。
通訊晶片1006也可包括封裝於通訊晶片1006內的積體電路晶粒。根據某些此類範例具體實施例，通訊晶片的積體電路晶粒包括以一或多個本文所述之電晶體結構所實施的一或多個電路(例如晶片上處理器或記憶體)。根據本說明書內容將理解到，需注意，多重標準無線能力可直接整合至處理器1004(例如任何晶片1006的功能係整合至處理器1004中，而非具有獨立的通訊晶片)。此外， 需注意，處理器1004可為具有此無線能力的晶片組。簡言之，可使用任何數量的處理器1004及/或通訊晶片1006。同樣地，任一晶片或晶片組可具有多個功能整合於其中。
在各種實施中，計算系統1000可為膝上型電腦、輕省筆電、筆記型電腦、智慧型手機、平板電腦、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、行動音樂播放器、或數位視頻記錄器。在進一步的實施中，系統1000可為處理資料或使用本文所述之低電阻電晶體裝置(如PMOS及CMOS電路)的任何其他電子裝置。
許多具體實施例將為明顯的，且本文所述的特徵可結合於任何數量的組態中。本發明一範例具體實施例提供一電晶體裝置。裝置包括具有通道區域的基板、在通道區域之上的閘極電極、及形成於基板之上或之中且鄰接通道區域的源極/汲極區域。源極及汲極區域之每一者具有一總厚度，其包含矽或鍺或矽鍺的一p型襯層以及具有鍺濃度超過80原子百分比的一p型蓋層，其中襯層小於總厚度的50%。在某些情況中，裝置為平面、FinFET、或奈米線PMOS電晶體之其中一者。在某些情況中，裝置更包括金屬-鍺化物源極/汲極接觸。在某些情況中，襯層厚度對蓋層厚度的厚度比為2：5或更低(襯層為總厚度的40%或更低)。在某些情況中，襯層厚度對蓋層厚度的厚度比為 1：5或更低(襯層為總厚度的20%或更低)。在某些情況中，襯層之每一者具有範圍在約1單分子層至10奈米的一厚度，且蓋層之每一者具有範圍在約50奈米至500奈米的一厚度。在某些情況中，襯層及/或蓋層之其中至少一者具有鍺及/或p型摻雜物之一漸次變化濃度之至少一者。舉例來說，在某些情況中，襯層之其中至少一者具有一鍺濃度，其從相容於基板之一基準濃度至超過50原子百分比之一高濃度而漸次變化。在一此類情況中，高濃度係超過90原子百分比。在某些情況中，襯層之其中至少一者具有一p型摻雜物濃度，其從相容於基板之一基準濃度至超過1E20cm-3之一高濃度而漸次變化。在一此類情況中，一或多個襯層之p型摻雜物為硼。在某些情況中，蓋層之其中至少一者具有超過95原子百分比之一鍺濃度。在某些情況中，蓋層之其中至少一者具有從相容於對應襯層之一基準濃度至超過80原子百分比之一高濃度而漸次變化的一鍺濃度。在某些情況中，蓋層之其中至少一者具有從相容於對應襯層之一基準濃度至超過1E20cm-3之一高濃度而漸次變化的一p型摻雜物濃度。在某些情況中，一或多個蓋層之p型摻雜物為硼。在某些情況中，蓋層之其中至少一者更包含錫。許多變化將為顯而易見的。舉例來說，在某些範例情況中，基板為含矽基板。在某些此類情況中，p型襯層包含矽或矽鍺。在其他範例情況中，基板為鍺基板。在某些此類情況中，p型襯層為p型鍺。在某些範例的此類情況中，每一襯層係包括在對應蓋 層的成分中(使得不同及獨立的襯層可能無法與不同及獨立的蓋層區別)。在某些情況中，蓋層之其中至少一者更包含錯位差排及/或穿透差排及/或雙晶，而在其他情況中，蓋層無錯位差排、穿透差排、及雙晶。本發明的另一具體實施例包括具有一印刷電路板的一電子裝置，其中印刷電路板具有包括此段落中各種不同定義之一或多個電晶體裝置的一積體電路。在一此類情況中，積體電路包含一通訊晶片及/或一處理器之其中至少一者。在某些情況中，電子裝置為一計算裝置。
本發明的其他具體實施例提供一積體電路。電路包括一基板(如矽、SiGe、或鍺)，其具有通道區域、於通道區域之上的閘極電極、形成於基板之上或之中且鄰接通道區域的源極/汲極區域、以及金屬鍺化物源極及汲極接觸。源極及汲極區域之每一者具有一總厚度，其包含矽或鍺或矽鍺的一p型襯層以及具有鍺濃度超過80原子百分比的一p型蓋層，其中襯層為總厚度的40%或更低。在某些情況中，襯層厚度對蓋層厚度的厚度比為1：5或更低。在某些情況中，蓋層之其中至少一者更包含錫。
本發明的另一具體實施例提供用以形成電晶體裝置的一方法。方法包括提供具有一通道區域的一基板、提供在通道區域之上的一閘極電極、以及提供形成於基板之上或之中且鄰近通道區域的源極及汲極區域。源極及汲極區域之每一者具有一總厚度，其包含矽或鍺或矽鍺的一p型襯層以及具有鍺濃度超過80原子百分比的一p型蓋層，其 中襯層小於總厚度的50%。在某些情況中，方法包括提供金屬鍺化物之源極及汲極接觸。在某些情況中，襯層厚度對蓋層厚度的厚度比為2：5或更低。在某些情況中，襯層及/或蓋層之其中至少一者具有鍺及/或p型摻雜物之一漸次變化濃度之至少一者。在某些情況中，蓋層之其中至少一者更包含錫(或其他合適的應變誘導物)。
前文中已提出本發明範例具體實施例的描述作為說明及描述目的。這並不意圖為詳盡的或限制本發明於所揭露的精確形式。根據本說明書內容，許多修改及變化是可能的。舉例來說，雖然本發明某些具體實施例利用鍺的原位硼摻雜，但其他具體實施例可使用本質鍺，其在沉積後係接著受到p型摻雜物佈植及退火製程以提供所需的p型摻雜濃度。此外，某些具體實施例可包括如本文所述而製造的源極及汲極區域，但仍使用傳統製程(例如佈植及退火)來形成源極及汲極區域的頂端。在此具體實施例中，頂端可具有比主要源極及汲極區域低的鍺及/或p型摻雜物濃度，其在某些應用中是可接受的。在其他具體實施例中，只有源極及汲極區域的頂端可組態為具有高鍺及p型摻雜物濃度，而源極及汲極區域的主要部份可具有傳統或較低的鍺/摻雜物濃度。本發明的範疇並不意欲受限於此詳細的說明內容，而是由後附之申請專利範圍所限制。

Claims (20)

  1. 一種積體電路裝置，包含：包括矽的鰭；在該鰭之一部分之上的一閘極電極；以及源極區域及汲極區域，該鰭之該部分在該源極及汲極區域之間，該源極及汲極區域之各者具有一總厚度，該總厚度包含包括矽或鍺之其中一者或兩者的一p型襯層以及具有鍺濃度超過80原子百分比的一p型蓋層，其中該p型襯層小於該總厚度的50%，該p型襯層在該p型蓋層及該鰭之該部分之間，且該源極及汲極區域之各者的該p型蓋層包括一或多個差排，該一或多個差排包括錯位差排或穿透差排之其中至少一者。
  2. 如申請專利範圍第1項所述之裝置，其中該鰭之該部分包括一或多個奈米線。
  3. 如申請專利範圍第1項所述之裝置，更包含在該等p型蓋層之上的金屬鍺化物之源極及汲極接觸。
  4. 如申請專利範圍第1項所述之裝置，其中p型襯層厚度對p型蓋層厚度的厚度比為2：5或更低。
  5. 如申請專利範圍第1項所述之裝置，其中該鰭之該部分也在該閘極電極之部分之間。
  6. 如申請專利範圍第1項所述之裝置，其中該等p型襯層之每一者具有範圍在約1單層(monolayer)至10奈米的一厚度，且該等p型蓋層之每一者具有範圍在約50奈米至500奈米的一厚度。
  7. 如申請專利範圍第1項所述之裝置，其中該等p型襯層或p型蓋層之其中至少一者具有鍺或p型摻雜物之一漸次變化濃度之至少一者。
  8. 如申請專利範圍第7項所述之裝置，其中該等p型襯層之其中至少一者具有一鍺濃度，該鍺濃度從相容於該鰭之該部分之一基準濃度至超過50原子百分比之一高濃度而漸次變化。
  9. 如申請專利範圍第8項所述之裝置，其中該高濃度係超過90原子百分比。
  10. 如申請專利範圍第7項所述之裝置，其中該等p型襯層之其中至少一者具有一p型摻雜物濃度，該p型摻雜物濃度從相容於該鰭之該部分之一基準濃度至超過1E20cm-3之一高濃度而漸次變化。
  11. 如申請專利範圍第10項所述之裝置，其中該等p型襯層之該其中至少一者之該p型摻雜物為硼。
  12. 如申請專利範圍第7項所述之裝置，其中該等p型蓋層之其中至少一者具有超過95原子百分比之一鍺濃度。
  13. 如申請專利範圍第7項所述之裝置，其中該等p型蓋層之其中至少一者具有從相容於該對應p型襯層之一基準濃度至超過80原子百分比之一高濃度而漸次變化的一鍺濃度。
  14. 如申請專利範圍第7項所述之裝置，其中該等p型蓋層之其中至少一者具有從相容於該對應p型襯層之一基準濃度至超過1E20cm-3之一高濃度而漸次變化的一p型摻雜物濃度。
  15. 如申請專利範圍第14項所述之裝置，其中該等p型蓋層之該其中至少一者之該p型摻雜物為硼。
  16. 如申請專利範圍第1項所述之裝置，其中該等p型蓋層之其中至少一者更包含錫。
  17. 一種積體電路，包含：包括矽的鰭；在該鰭之一部分之上的閘極電極；以及源極區域及汲極區域，該鰭之該部分在該源極及汲極區域之間，該源極及汲極區域之各者包含一或多個奈米線，每個奈米線包括具有一總厚度的雙層結構，該總厚度包含具有矽或鍺之其中一者或兩者的一p型襯層以及具有鍺濃度超過80原子百分比的一p型蓋層，其中該p型襯層小於該總厚度的40%，該p型襯層在該p型蓋層及該鰭之該部分之間，且該源極及汲極區域之各者的該p型蓋層包括一或多個差排，該一或多個差排包括錯位差排或穿透差排之其中至少一者，且其中該鰭之該部分包括壓縮應變。
  18. 如申請專利範圍第17項所述之電路，其中p型襯層厚度對p型蓋層厚度的厚度比為1：5或更低。
  19. 如申請專利範圍第17項所述之電路，其中該等p型蓋層之其中至少一者更包含20%或更低濃度的錫。
  20. 如申請專利範圍第17項所述之電路，更包含在該等p型蓋層之上的金屬鍺化物之源極及汲極接觸。
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