CN105826390A - 晶体管器件、电子设备以及形成晶体管器件的方法 - Google Patents

晶体管器件、电子设备以及形成晶体管器件的方法 Download PDF

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CN105826390A
CN105826390A CN201610313170.4A CN201610313170A CN105826390A CN 105826390 A CN105826390 A CN 105826390A CN 201610313170 A CN201610313170 A CN 201610313170A CN 105826390 A CN105826390 A CN 105826390A
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concentration
boron
drain region
sige layer
germanium
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CN105826390B (zh
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G·A·格拉斯
A·S·默西
T·加尼
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Intel Corp
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Intel Corp
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

本发明涉及一种晶体管器件、电子设备以及形成晶体管器件的方法。公开了用于形成晶体管器件的技术，其相对于常规器件具有减小的寄生接触电阻。该技术例如可以使用标准接触部堆叠体来实现，所述标准接触部堆叠体例如为在硅或硅锗(SiGe)源极/漏极区上的一系列金属。根据一个示例性的此类实施例，在源极/漏极与接触部金属之间提供中间硼掺杂锗层，以显著减小接触电阻。根据本公开内容，多种晶体管结构和适合的制造工艺会是显而易见的，包括平面和非平面晶体管结构(例如，FinFET)，以及应变的和未应变的沟道结构。分级的缓冲部可以用于减小错配位错。这些技术尤其适合于实现p型器件，但如有需要也可以用于n型器件。

Description

晶体管器件、电子设备以及形成晶体管器件的方法
本申请为分案申请，其原申请是于2013年6月21日(国际申请日为2011年9月30日)向中国专利局提交的专利申请，申请号为201180062116.2，发明名称为“晶体管器件、电子设备以及形成晶体管器件的方法”。
相关申请
本申请是2010年12月21日提交的美国申请No.12/975278的部分继续申请。
技术领域
本发明涉及一种晶体管器件、电子设备以及形成晶体管器件的方法。
背景技术
包括形成于半导体衬底上的晶体管、二极管、电阻器、电容器及其他无源和有源电子器件的电路器件的提高的性能，通常是在这些器件的设计、制造和操作过程中考虑的主要因素。例如，在金属氧化物半导体(MOS)晶体管半导体器件(例如在互补金属氧化物半导体(CMOS)中所使用的那些)的设计和制造或形成的过程中，常常希望使得与接触部相关的寄生电阻(或者称为外电阻Rext)最小化。减小的Rext能够由相等的晶体管设计实现较高的电流。
发明内容
根据本发明的一个方面，提供了一种晶体管器件，包括：
具有沟道区的衬底；
与所述沟道区相邻的源极区和漏极区；以及
在所述源极区和所述漏极区的至少一部分上的硼掺杂锗层，该硼掺杂锗层具有超过90原子％的锗浓度和超过1E20cm-3的硼浓度。
根据本发明的另一方面，提供了一种晶体管器件，包括：
具有沟道区的衬底；
在所述沟道区上方的栅极电极，其中，在所述栅极电极与所述沟道区之间提供了栅极电介质层，在所述栅极电极的侧面上提供了间隔体；
与所述沟道区相邻的源极区和漏极区，所述源极区和所述漏极区中的每一个都包括尖端区，所述尖端区在所述栅极电介质层和/或对应的一个所述间隔体下方延伸；
在所述源极区和所述漏极区的至少一部分上的硼掺杂锗层，所述硼掺杂锗层具有超过95原子％的锗浓度和超过2E20cm-3的硼浓度；以及
在所述硼掺杂锗层上的第一金属-锗化物接触部和第二金属-锗化物接触部，所述第一金属-锗化物接触部和所述第二金属-锗化物接触部分别位于所述源极区和所述漏极区中的对应的一个之上；
其中，所述器件是平面晶体管或FinFET晶体管中的一种。
根据本发明的另一方面，提供了一种电子设备，包括：
印刷电路板，其具有一个或多个集成电路，其中，所述一个或多个集成电路中的至少一个集成电路包括根据本发明所述的晶体管器件。
根据本发明的另一方面，提供了一种用于形成晶体管器件的方法，包括：
提供具有沟道区的衬底；
在所述沟道区上方提供栅极电极，其中，在所述栅极电极与所述沟道区之间提供了栅极电介质层；以及
与所述沟道区相邻地提供源极区和漏极区；
在所述源极区和所述漏极区中的至少一部分上提供硼掺杂锗层，所述硼掺杂锗层具有超过90原子％的锗浓度和超过1E20cm-3的硼浓度；
在所述硼掺杂锗层上且在所述源极区之上提供第一金属-锗化物接触部；以及
在所述硼掺杂锗层上且在所述漏极区之上提供第二金属-锗化物接触部。
附图说明
图1A示出了根据本发明一个实施例的在源极/漏极层与接触部金属之间配置有硼掺杂锗层的MOS器件。
图1B示出了根据本发明另一个实施例的在源极/漏极层与接触部金属之间配置有硼掺杂锗层的MOS器件。
图1C示出了根据本发明另一个实施例的在源极/漏极层与接触部金属之间配置有硼掺杂锗层的MOS器件。
图2是根据本发明实施例的用于形成具有低接触电阻的晶体管结构的方法。
图3A到3I示出了根据本发明多个实施例的在实施图2的方法时形成的结构。
图4是根据本发明另一个实施例的用于形成具有低接触电阻的晶体管结构的方法。
图5A到5F示出了根据本发明多个实施例的在实施图4的方法时形成的结构。
图6示出了根据本发明一个实施例配置的FinFET晶体管架构的透视图。
图7示出了分批图(plotofasplitlot)，该分批图示出根据本发明实施例配置的晶体管结构和没有配置帽层的标准晶体管结构的接触电阻。
图8示出了根据本发明的示例性实施例的实现有一个或多个晶体管结构的计算系统。
可以理解，附图不一定按照比例绘制，或者旨在将所要求保护的发明局限于所示出的特定结构。例如，尽管一些图形总体上表示直线、直角和平滑表面，但考虑到所用的处理设备和技术的现实世界的限制，晶体管结构的实际实施方式可以具有不太完美的直线、直角，一些特征可以具有表面拓扑，或者是非平滑的。总之，提供附图仅用于示出示例性结构。
具体实施方式
公开了用于形成晶体管器件的技术，其相对于常规器件具有减小的寄生接触电阻。所述技术例如可以使用标准接触部堆叠体来实现，所述标准接触部堆叠体例如为在硅或硅锗(SiGe)源极/漏极区上的一系列金属。根据一个示例性的此类实施例，在源极/漏极与接触部金属之间提供中间硼掺杂锗层，以显著减小接触电阻。根据本公开内容，多种晶体管结构和适合的制造工艺会是显而易见的，包括平面和非平面晶体管结构(例如，FinFET)，以及应变的和未应变的沟道结构。所述技术尤其适合于实现p型器件，但如有需要也可以用于n型器件。
概述
如前解释的，可以通过减小器件电阻来实现晶体管中增大的驱动电流。接触电阻是器件的总电阻的一个分量。标准晶体管接触部堆叠体通常包括例如硅或SiGe源极/漏极层、硅化镍层、氮化钛粘附层、和钨接触部/焊盘。在这种结构中，接触电阻受到相对于金属中钉扎能级的硅或SiGe价带配准(alignment)的有效限制。通常，使用诸如镍的工业标准硅化物(或其他适合的硅化物，诸如钛、钴、或铂等)，这会导致约0.5eV的带失配。这样，根据本发明的一个示例性实施例，在源极/漏极与接触部金属之间提供中间硼掺杂锗层，以显著减小带失配值与接触电阻。
在一个特定示例性实施例中，配置有中间硼掺杂锗层的接触部呈现了带失配值减小到小于0.2eV，以及接触电阻约3倍的对应减小(相对于类似配置的常规接触部堆叠体，但在源极/漏极区与接触部金属之间不具有中间硼掺杂锗层)。透射电子显微镜法(TEM)横截面或次级离子质谱法(SIMS)分布图(profile)可以用于示出遍及薄膜结构的垂直堆叠体的锗浓度，因为可以易于区分SiGe和硅的外延合金的分布图与锗浓度分布图。
这样，根据本发明实施例配置的晶体管结构就较低的接触电阻而言提供了对传统结构的改进。一些此类实施例有效地将锗的优异接触特性与Si和SiGe的优异半导体晶体管特性相融合，以提供下一代的低电阻接触部。
根据本公开内容，多种晶体管结构和适合的制造工艺会是显而易见的，包括平面和非平面晶体管结构(例如，双栅极和三栅极晶体管结构)，以及应变的和未应变的沟道结构。许多这种结构特征和材料系统都可以结合如本文所述的锗覆盖层来使用。晶体管结构可以包括p型源极/漏极区、n型源极/漏极区，或者n型和p型源极/漏极区。在一些示例性实施例中，晶体管结构包括MOS结构中的硅、SiGe合金或名义上纯的锗膜(例如，具有小于10％硅的锗膜)的外延(或多晶)置换源极/漏极区或者掺杂剂-注入的源极/漏极区或。在任何此类实施方式中，根据本发明的实施例，可以直接在源极/漏极区上形成硼掺杂锗的覆盖层或帽层。随后可以沉积接触部金属(或一系列金属)，并可以执行后续反应(退火)，以形成金属锗化物源极和漏极接触部。如会理解的，接触部可以实现为堆叠体，包括一个或多个硅化物层、粘附层、和/或金属焊盘层。如果希望，也可以在晶体管结构的其他部分上直接形成硼掺杂锗覆盖层，例如多晶栅极和/或接地接头(tap)区。
众所周知，MOS晶体管可以包括源极和漏极尖端区，将其设计为减小晶体管的总体电阻，同时改善短沟道效应(SCE)。传统上，这些尖端区是衬底的使用注入和扩散技术注入诸如硼或碳的掺杂剂的部分。在源极区与沟道区之间的区域中形成源极尖端区。类似地，在漏极区与沟道区之间的区域中形成漏极尖端区。本发明的一些实施例配置有这种常规形成的尖端区。在其他示例性实施例中，使用制造技术来延伸自对准外延尖端(SET)晶体管，以实现极为接近单轴向应变的理论极限。例如，这可以通过以下方式来完成：在源极和漏极区以及其相应的尖端区中进行选择性外延沉积，以形成覆盖有硼掺杂锗层的覆盖层的硼掺杂硅或SiGe(用于源极/漏极区)的双层结构。锗和硼浓度可以改变，但在一些示例性实施例中，锗浓度在20原子％到100原子％范围中，硼浓度在1E20cm-3到2E21cm-3范围中(例如，锗浓度超过50原子％，硼浓度超过2E20cm-3)。注意，可以在尖端区中提供硼掺杂锗层，但在其他实施例中，仅在源极/漏极区之上(不在尖端区中)提供硼掺杂锗层。
在其他的示例性实施例中，可任选的具有分级的锗浓度和/或硼浓度的薄缓冲部可以用作下层衬底与源极/漏极层(例如，硅或SiGe)之间的分界面层。类似地，具有分级的锗浓度和/或硼浓度的薄缓冲部可以用作在源极/漏极层与硼掺杂锗帽层之间的分界面层。在其他的实施例中，以类似于可任选的缓冲部的方式，硼掺杂锗覆盖层或源极/漏极层自身可以具有分级的锗和/或硼浓度。在任何此类情况下，由于硼扩散在锗中受到抑制(浓度越高，相对抑制越大)，高浓度的硼可以掺杂在锗中，这又导致较低的寄生电阻，且不会使尖端陡度(abruptness)降级。另外，通过降低肖特基势垒高度减小了接触电阻。
架构和方法
图1A示出了根据本发明的实施例的，形成在衬底102上且在源极/漏极层和接触部金属之间配置有硼掺杂锗层的MOS器件100A。具体地，在源极层110与接触部金属125之间提供硼掺杂锗层117，在漏极层112与接触部金属127之间提供硼掺杂锗层119。可以使用许多传统技术来形成源极区110与漏极区112。在该示例性实施例中，例如，通过蚀刻衬底，随后外延沉积硅或硅锗材料(例如，锗浓度范围为10到70原子％)来形成源极区110与漏极区112。
在晶体管100A的沟道区120之上形成栅极堆叠体122。如可以进一步看出的，栅极堆叠体122包括栅极电介质层106和栅极电极104，相邻于栅极堆叠体122形成间隔体108。在一些示例性情况下，并且根据技术节点，间隔体108在栅极电介质层106的边缘与源极和漏极区110/112中的每一个的边缘之间产生约10到20纳米(nm)的距离。在这个间隔内可以形成源极尖端区110A和漏极尖端区112A。在这个示例性实施例中，借助典型的基于注入-扩散的工艺来形成尖端区110A/112A，所述尖端区110A/112A与间隔体108重叠，且还可以在例如小于10nm的距离上与栅极电介质层106重叠或在栅极电介质层106下扩散。在形成基于注入-扩散的尖端区110A/112A的过程中，将诸如硼或碳的掺杂剂注入源极区110和漏极区112中。随后对晶体管100A进行退火，以使得掺杂剂向沟道区120扩散。成角度的离子注入技术也可以用于将掺杂剂进一步注入在栅极电介质层106与源极/漏极区110/112之间的这些区域中。这种基于注入-扩散的尖端形成工艺通常不会引起沟道区上的应变。
总之，根据本公开内容会理解的是，无论晶体管结构具有应变或未应变的沟道，还是具有源极-漏极尖端区或不具有源极-漏极尖端区并不特别地与本发明的各实施例相关，这种实施例并非旨在局限于任何特定的此类结构特征。相反，许多晶体管结构和类型都可以得益于使用本文所述的硼掺杂锗覆盖层。本文提供的技术适合于例如传统掺杂剂注入的硅、隆起的源极/漏极、应变的SiGe(或其他适合的材料)、及在栅极电极电介质下延伸的或与由栅极电极电介质定义的垂线间隔开的任何沉积的外延尖端(有时称为源极-漏极延伸部)。
通常在形成源极/漏极区110/112后且在形成接触部125/127前提供锗覆盖层117/119。该覆盖层117/119的厚度在实施例之间可以变化，但在一个示例性实施例中在50到150埃范围中。覆盖层117/119的硼浓度也可以变化，但在一个示例性实施例中在1E20cm-3到2E21cm-3范围中(例如超过2E20cm-3)。可以选择性地在源极/漏极区110/112(和/或所希望的其他区域，例如多晶栅极或接地接头区)上沉积覆盖层117/119。许多适合的沉积技术可以用于提供覆盖层117/119(例如，化学气相沉积、分子束外延等)。根据一个示例性实施例，接触部金属125和127均包括硅化镍层、氮化钛粘附层、和钨接触部/焊盘的堆叠体，但根据本公开内容会理解，可以使用许多接触部金属结构。标准沉积技术可以用于提供接触部金属125/127。
图1B示出了根据本发明另一个实施例的形成于衬底102上的示例性MOS器件100B，该MOS器件100B在源极/漏极层110/112与接触部金属125/127之间配置有硼掺杂锗层117/119。该示例性结构包括源极和漏极外延尖端(本文中通常称为外延尖端(epi-tip))。更具体地，MOS晶体管100B使用底切蚀刻，以允许源极区110和漏极区112在间隔体108下方延伸，在一些情况下，是在栅极电介质层106下方延伸。将在间隔体108(有可能在栅极电介质层106)下方延伸的源极/漏极区110/112的部分分别统称为源极外延尖端110B和漏极外延尖端112B。源极和漏极外延尖端110B/112B代替针对图1A所述的基于注入/扩散的尖端区110A/112A。根据一个实施例，如图1B所示，例如可以通过蚀刻衬底102，这包括底切间隔体108(有可能是栅极电介质层106)，随后使用选择性外延沉积来例如提供原位掺杂硅、锗或SiGe，以填充源极/漏极区110/112和源极/漏极外延尖端110B/112B，来形成源极/漏极区110/112和源极/漏极外延尖端110B/112B。注意，外延填充部可以相对于衬底102的表面隆起，如图1B中进一步所示的，尽管也可以使用不隆起的结构。例如，如前针对图1A所述的，可以实现锗覆盖层117/119和接触部金属125/127。
图1C示出了根据本发明另一个实施例的形成于衬底102上且在相应的源极/漏极层110/112与接触部金属125/127之间配置有硼掺杂锗层117/119的MOS器件100C。通过将诸如硼的掺杂剂注入到衬底中来形成该示例性实施例中的源极区110和漏极区112。栅极堆叠体122在晶体管100C的沟道区120上形成，且在该示例性情况下不包括侧壁108。这个示例性晶体管结构也不包括类似于图1A和1B所示实施例的底切或尖端区。例如，如前针对图1A所述的，可以实现锗覆盖层117/119和接触部金属125/127。
可以针对根据本发明配置的晶体管结构实现许多其他变化和特征。例如，分级的缓冲部可以用于结构的一个或多个位置。例如，衬底102可以是硅衬底，或者绝缘体上硅(SOI)的硅膜衬底，或者多层衬底，其包括硅、硅锗、锗、和/或III-V族化合物半导体。因此，示例性地，在具有硅或硅锗衬底102，且原位硼掺杂SiGe填充源极/漏极区110/112和源/漏外延尖端110B/112B的实施例中，可以在下层衬底102与源极/漏极材料之间提供缓冲部。在一个此类实施例中，缓冲部可以是分级的硼掺杂的(或本征的)硅锗层，其具有从与下层衬底相容的基准级别(baselevel)到高达100原子％(或接近100原子％，诸如超过90原子％或95原子％或98原子％)分级的锗浓度。这个缓冲部内的硼浓度可以是固定的(例如在高级别)或分级的，例如从处于下层衬底的或与其相容的基准浓度到预期的高浓度(例如，超过2E20cm-3)。注意，本文所用的“相容性”并非必须要求浓度级别重叠(例如，下层衬底的锗浓度可以是0到20原子％，缓冲部的初始锗浓度可以是30到40原子％)。另外，本文所用的相对于浓度级别的词语“固定”旨在表示相对恒定的浓度级别(例如，层中最低浓度级别在该层内最高浓度级别的10％以内)。在更普遍的意义上，固定的浓度级别旨在表示缺少有意分级的浓度级别。缓冲部的厚度可以根据诸如缓冲的浓度的范围之类的因素而改变，但在一些实施例中，其在30到范围中，诸如50到 (例如，或)。根据本公开内容将会意识到，这种分级的缓冲部有益地降低了肖特基势垒高度。
可替换地，不是使用在衬底102与源极/漏极区110/112和源极/漏极外延尖端110B/112B之间的薄缓冲部，可以以类似的方式将源极/漏极材料自身分级。例如，根据一个示例性实施例，可以以从与下层衬底相容的基准级别浓度(例如，在30到70原子％范围中)到高达100原子％分级的锗浓度来配置硼掺杂SiGe源极/漏极区110/112和源极/漏极外延尖端110B/112B。在一些这种实施例中，该硼掺杂锗层内的硼浓度范围例如可以是从处于下层衬底的或与之相容的基准浓度到预期的高浓度(例如，超过2E20cm-3)。
在其他实施例中，可以在源极/漏极材料与硼掺杂的锗覆盖层117/119之间提供缓冲部。在一个这种实施例中，源极/漏极材料是硼掺杂的SiGe层，具有固定的锗浓度(例如，在30到70原子％范围中)；缓冲部可以是薄SiGe层(例如，30到诸如50到)，具有从与下层硼掺杂的SiGe层相容的基准级别浓度到高达100原子％(或接近100原子％，诸如超过90原子％或95原子％或98原子％)分级的锗浓度。在一些这种情况下，该缓冲部内的硼浓度例如可以固定在预期的高级别，或者范围例如可以是从处于下层SiGe层的或与之相容的基准浓度到预期的高浓度(例如，超过1E20cm-3、2E20cm-3、3E20cm-3)。可替换地，不是使用在源极/漏极材料与硼掺杂的锗覆盖层117/119之间的缓冲部，可以以类似的方式对覆盖层117/119自身分级。例如，根据一个示例性实施例，可以以从与下层衬底和/或源极/漏极区相容的基准级别浓度(例如，在30到70原子％范围中)到高达100原子％(或者接近100原子％)分级的锗浓度来配置硼掺杂的覆盖层117/119。在这个覆盖层117/119内的硼浓度例如可以固定在高级别或者例如可以在从处于下层衬底和/或源极/漏极区的或与之相容的基准浓度到预期的高浓度(例如，超过2E20cm-3)的范围中。
因此，提供了用于多种晶体管器件的低接触电阻架构。可以部分地使用许多传统工艺来形成器件，例如通过源极/漏极区中的栅极氧化物、多晶栅极电极、薄间隔体、及各向同性底切蚀刻(或者氨蚀刻以在单晶衬底中形成有小面的(faceted)鳍凹槽，或者用以形成鳍凹槽的其他适合的蚀刻)来形成器件。根据一些实施例，选择性外延沉积可以用于提供原位掺杂硅，或者可替换地，充分应变的硅锗层，以形成具有或不具有尖端的源极/漏极区。可以如前所解释的那样使用可任选的缓冲部。也可以使用任何适合的高-k置换金属栅极(RMG)工艺流程，其中高-k电介质代替了传统的栅极氧化物。例如，利用镍、镍-铂、或者进行了或没有进行锗的预先非晶化注入的钛的硅化(silicidation)可以用于形成低电阻锗化物。本文提供的技术例如可应用以有益于任何技术节点(例如，90nm、65nm、45nm、32nm、22nm、14nm和10nm晶体管，及更低的)，所要求保护的本发明并非旨在局限于器件几何尺寸的任何特定的此类节点或范围。根据本公开内容，其他优点将会是显而易见的。
图2是根据本发明实施例的用于形成具有低接触电阻的晶体管结构的方法。图3A到3I示出了根据本发明一些实施例的随着实施该方法而形成的示例性结构。
如图所示，方法以在半导体衬底上形成202栅极堆叠体开始，在该半导体衬底上可以形成诸如PMOS晶体管的MOS器件。例如可以以块硅或绝缘体上硅结构来实现半导体衬底。在其他实施方式中，可以使用可以结合或不结合硅的替换的材料来形成半导体衬底，所述替换的材料诸如锗、硅锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。在更普遍的意义上，根据本发明的实施例，可以使用可以充当在其上可以构造半导体器件的基础的任何材料。可以如传统所实施的那样或者使用任何适合的定制技术来形成栅极堆叠体。在本发明的一些实施例中，可以通过沉积，随后对栅极电介质层和栅极电极层进行构图来形成栅极堆叠体。例如，在一个示例性情况下，可以使用传统沉积工艺在半导体衬底上均厚沉积栅极电介质层，所述传统沉积工艺例如为化学气相沉积(CVD)、原子层沉积(ALD)、旋涂沉积(SOD)、或物理气相沉积(PVD)。也可以使用替换的沉积技术，例如，可以热生长栅极电介质层。例如，可以由诸如氧化硅或高-k电介质材料的材料形成栅极电介质材料。高-k栅极电介质材料的实例例如包括二氧化铪、铪硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、氧化钛、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铌锌酸铅。在一些特定的示例性实施例中，高-k栅极电介质层的厚度可以在约到约之间(例如，到)。通常，栅极电介质层的厚度应足以使得栅极电极与相邻的源极和漏极接触部电隔离。在进一步的实施例中，可以在高-k栅极电介质层上执行额外的处理，诸如退火工艺以改进高-k材料的质量。接下来，可以使用诸如ALD、CVD、或PVD的类似沉积技术在栅极电介质层上沉积栅极电极材料。在一些这种特定实施例中，栅极电极材料是多晶硅或金属层，尽管也可以使用其他适合的栅极电极材料。栅极电极材料可以是牺牲材料，稍后针对置换金属栅极(RMG)工艺将其去除，其在一些实施例中具有到范围中(例如)的厚度。随后可以实施传统的构图工艺，以蚀刻掉栅极电极层和栅极电介质层的部分，从而形成栅极叠置体，如图3A所示。可以看出，图3A示出了衬底300，在其上形成栅极堆叠体。在这个示例性实施例中，栅极堆叠体包括栅极电介质层302(其可以是高-k栅极电介质材料)和牺牲栅极电极304。在一个特定示例性情况下，栅极堆叠体包括氧化硅栅极电介质层302和多晶硅栅极电极304。栅极堆叠体还可以包括栅极硬掩模层306，其在处理过程中提供某些益处或用途，诸如保护栅极电极304使其免于随后的离子注入工艺。可以使用诸如氧化硅、氮化硅、和/或其他常规电介质材料等典型的硬掩模材料来形成硬掩模层306。图3A进一步示出了形成于堆叠体任一侧上的间隔体310。例如可以使用诸如氧化硅、氮化硅或其他适合的间隔体材料的常规材料来形成间隔体310。通常可以基于对所形成晶体管的设计要求来选择间隔体310的宽度。然而根据一些实施例，间隔体310的宽度不受形成源极和漏极外延尖端所施加的设计约束的支配，只要如本文所述的那样，源极/漏极尖端区中有足够高的硼掺杂锗含量(硼不会扩散到沟道中)。
进一步参考图2，在形成栅极堆叠体后，方法继续进行定义204晶体管结构的源极/漏极区。如前解释的，可以以许多适合的工艺和结构来实现源极/漏极区。例如，可以注入、蚀刻和外延填充、升高源极/漏极区，所述源极/漏极区可以是硅或SiGe合金、p型或n型的，具有平面或鳍形扩散区。在图3A所示的示例性实施例中，蚀刻了衬底300以提供空腔312/314以及相应的尖端区域312A/314A，其底切栅极电介质302。图3B示出了填充空腔312/314和尖端区312A/314A以提供源极/漏极区318/320和尖端区318A/320A后的衬底300。根据一些示例性实施例，以原位掺杂的硅或SiGe填充源极和漏极区空腔312/314连同其相应的尖端区312A/314A，从而形成源极区318(连同外延尖端318A)和漏极区320(连同漏极外延尖端320A)。在此就材料(例如硅、SiGe、III-V族材料)、掺杂剂(例如，超过2E21cm-3的硼，或其他适合的掺杂剂/浓度)以及尺寸(例如，源极/漏极层的厚度范围例如可以在50到500nm之间，以便提供平齐的或隆起的源极/漏极区)而言，可以使用许多源极/漏极层配置。
如前解释的，一些这种实施例可以包括在源极/漏极层与衬底或源极/漏极与硼掺杂锗覆盖层之间的薄缓冲部。例如，可以进一步在图3B所示的示例性实施例中看出，在沉积源极/漏极材料之前沉积源极缓冲部313和漏极缓冲部315。在一些实施例中，缓冲部313和315可以是分级的硼掺杂硅锗层，具有从与下层衬底300材料相容的基准级别浓度到高达100原子％(或如前所述的接近100原子％)分级的锗成分。硼浓度也可以适当地分级。根据本公开内容，许多缓冲部方案会是显而易见的。
进一步参考图2，在定义了源极/漏极区后，该方法继续进行在晶体管结构的源极/漏极区上沉积206硼掺杂锗。图3C示出了硼掺杂锗层317/319。在一些示例性实施例中，硼掺杂锗层317/319可以外延沉积在一个或多个层中，其具有超过90原子％的锗浓度，尽管根据本公开内容会理解也可以使用其他适合的浓度级别(例如，超过91原子％，或92原子％，......，或98原子％或99原子％，或者真正的纯锗)。如前解释的，该锗浓度可以是固定的或者分级的，以便从基准级别(接近衬底300)增大到高级别(例如，超过90原子％)。在一些这种实施例中，硼浓度可以超过1E20cm-3，例如高于2E20cm-3或2E21cm-3，也可以是分级的，以便从接近衬底300的基准级别增大到高级别(例如，超过1E20cm-3，或2E20cm-3，或3E20cm-3，……，2E21cm-3)。如前解释的，在下层源极/漏极区318/320的锗浓度是固定的或者相对低的实施例中，分级的缓冲部可以用于更好地连接源极/漏极区318/320与硼掺杂锗层317/319。根据一些特定的示例性实施例，硼掺杂锗帽层317/319的厚度可以具有例如在到范围中的厚度，尽管如根据本公开内容会是显而易见的，可替换的实施例可以具有其它层厚度。
在一些实施例中，CVD工艺或其它适合的沉积技术可以用于沉积206或形成硼掺杂锗层317/319。例如，可以使用包含诸如锗烷(GeH4)或乙锗烷(Ge2H6)和乙硼烷(B2H6)或二氟化甲氧硼(BF2)的前驱气体的锗和硼，在CVD、或速热CVD(RT-CVD)、或低压CVD(LP-CVD)、或超高真空CVD(UHV-CVD)、或气源分子束外延(GS-MBE)设备中执行沉积206。在一些这种实施例中，例如，可以存在诸如氢气、氮气或惰性气体的载运气体(例如，以载运气体1-5％的浓度稀释前驱气体)。也可以存在蚀刻剂气体，例如基于卤素的气体，诸如氯化氢(HCl)、氯(Cl)、或溴化氢(HBr)。锗以及硼掺杂锗的基础沉积在使用例如300℃到800℃范围(例如300-500℃)中的沉积温度，和例如1Torr到760Torr范围中的反应器压力的宽泛条件下也是可能的。锗是天然选择性的，因为它沉积在硅或硅锗合金上，不沉积在诸如氧化硅和氮化硅的其它材料上。如以前注意到的，由于该天然选择性并非完全完美的，小流量的蚀刻剂可以用于增大沉积的选择性。载体和蚀刻剂中的每一个都可以具有10到300SCCM范围中的流速(通常，需要不大于100SCCM的流速，但一些实施例可能需要更高的流速)。在一个特定的示例性实施例中，使用在氢气中稀释为1％浓度的GeH4，并以100到1000SCCM范围的流速执行沉积206。对于硼的原位掺杂，可以使用稀释的B2H6(例如，B2H6可以在H2中稀释为3％浓度，并且流速范围为100到600SCCM)。在一些这种特定的示例性情况下，以例如10到100SCCM范围的流速添加HCl或Cl2的蚀刻剂，以增大沉积的选择性。
如根据本公开内容会理解的，可以根据需要改变沉积硼掺杂锗层317/319的选择性。例如在一些情况下，仅在源极/漏极区318/320或一部分源极/漏极区318/320上(而不是跨越整个结构)沉积硼掺杂锗层317/319。许多掩蔽/构图技术可以用于选择性沉积层317/319。此外，其他实施例可以得益于覆盖例如多晶栅极区或接地接头区的层317/319。如根据本公开内容会进一步理解的，根据一些示例性实施例，高锗浓度(例如，超过90原子％，并高达纯锗)与高硼浓度(例如，超过2E20cm-3)的组合可以用于在源极和漏极区(及希望得到低接触电阻的其他区域，诸如接地接头区)中实现明显低得多的接触电阻。此外，如前解释的，由于硼扩散受到纯锗的充分抑制，随后的热退火没有获得任何不利的SCE降级，尽管有接近沟道的高硼浓度(如果适用的话)。由在接触表面的较高浓度的锗还实现了势垒高度的降低。在一些示例性实施例中，超过95原子％并高达纯锗(100原子％)的锗浓度可以用于实现这种益处。
进一步参考图2，在提供了硼掺杂锗层317/319后，该方法继续进行在层317/319上沉积208电介质。图3D示出了电介质322与栅极堆叠体的硬掩模306平齐，但其不必如此。可以用多种方式配置电介质。在一些实施例中，以氧化硅(SiO2)或其他低-k电介质材料来实现电介质322。在其他实施例中，以氮化硅(SiN)衬里，之后是一个或多个SiO2层，或者氮化物、氧化物、氧氮化物、碳化物、碳氧化物、或其他适合的电介质材料的任意组合来实现电介质322。可以称为层间电介质(ILD)的电介质322可以按通常所实施的那样的进行平面化。其他示例性电介质材料例如包括碳掺杂氧化物(CDO)、诸如八氟环丁烷或聚四氟乙烯之类的有机聚合物、氟硅酸盐玻璃(FSG)、和诸如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃之类的有机硅酸盐。在一些示例性结构中，ILD层可以包括小孔或其他孔隙，以进一步减小其介电常数。
接下来，在使用了置换金属栅极(RMG)工艺的本发明的一些实施例中，并如图3E最佳示出的，该方法可以进一步包括使用如传统所实施的那样的蚀刻工艺来去除栅极堆叠体(包括高-k栅极电介质层302、牺牲栅极电极304和硬掩膜层306)。在替换的实施方式中，仅去除牺牲栅极304和硬掩模层306。图3E示出了根据一个这种实施例的在蚀刻掉栅极堆叠体时形成的沟槽开口。如果去除栅极电介质层，该方法就可以继续进行在沟槽开口(在图3F中标记为324)中沉积新的栅极电介质层。在此可以使用如前所述的任何适合的高-k电介质材料，例如二氧化铪。也可以使用相同的沉积工艺。栅极电介质层的置换例如可以用于应对在干法和湿法蚀刻工艺实施过程中会对原始栅极电介质层造成的任何损害，和/或以高-k或其他预期的栅极电介质材料来代替低-k或牺牲电介质材料。如图3F进一步示出的，该方法进一步继续进行将金属栅极电极层326沉积到沟槽中和栅极电介质层324上。传统金属沉积工艺可以用于形成金属栅极电极层，例如CVD、ALD、PVD、无电镀覆或电镀。金属栅极电极层例如可以包括P型功函数金属，例如钌、钯、铂、钴、镍，和导电金属氧化物，例如氧化钌。在一些示例性结构中，可以沉积两个或更多个金属栅极电极层。例如，可以在栅极沟槽中沉积功函数金属，之后是诸如铝或银的适合的金属栅极电极填料金属。
进一步参考图2，在层317/319上提供了电介质层322(和任何所希望的RMG工艺)后，该方法继续进行蚀刻210以形成源极/漏极接触沟槽。可以使用任何适合的干法和/或湿法蚀刻工艺。图3G示出了根据一个示例性实施例的在完成蚀刻后的源极/漏极接触沟槽。该方法继续进行沉积212接触电阻减小金属和退火，以形成硅化物/锗化物，随后沉积214源极/漏极接触插塞。图3H示出了接触部金属325/327，在一些实施例中，其包括硅化物/锗化物，尽管其他实施例可以包括额外的层(例如，粘附层)。图3I示出了接触插塞金属329/331，在一些实施例中，其包括铝，尽管使用常规沉积工艺任何适合的导电接触部金属或合金也可以用于接触插塞329/331，诸如银、镍-铂或镍-铝或镍与铝的其他合金、或钛。例如可以借助以镍、铝、镍-铂或镍-铝或镍和铝的其他合金、或者进行或没有进行锗的预先非晶化注入的钛进行的用以形成低电阻锗化物的硅化来实现源极和漏极接触部的锗化物/金属化212。硼掺杂锗层317/319允许金属-锗化物形成(例如，镍-锗)。锗化物允许比传统金属硅化物系统低得多的肖特基势垒高度及改善的接触电阻(包括Rext)。例如，传统晶体管通常使用源极/漏极SiGe外延工艺，其中锗浓度在30-40原子％范围中。受到外延/硅化物分界面电阻的限制，这种传统系统呈现了约140Ohm*um的Rext值，其较高并且将来会阻碍栅极间距缩放。本发明的一些实施例允许PMOS器件中Rext的相当大的改善(例如，约2倍的改善或更佳，例如约70Ohm*um的Rext)，这可以更好地支持PMOS器件缩放。因此，具有以根据本发明实施例的硼掺杂锗帽层317/319配置的源极/漏极的晶体管可以呈现出小于100Ohm*um的Rext值，在一些情况下小于90Ohm*um，在一些情况下小于80Ohm*um，在一些情况下小于75Ohm*um或者更低，其中在源极/漏极区318/320与接触部金属325/327之间的分界面具有超过1E20cm-3的硼浓度、超过90原子％并高达或者接近纯锗(100原子％)的锗浓度。
图4是根据本发明的另一个实施例的用于形成具有低接触电阻的晶体管结构的方法。图5A到5F示出了根据一些实施例的在实施该方法时形成的示例性结构。总体上，这个方法类似于参考图2和3A-H所述的方法，除了在沉积电介质322并对其进行蚀刻以形成接触沟槽之后实施在源极/漏极区上沉积硼掺杂锗层317/319以外。因此，该方法包括直接在源极/漏极区318/320上沉积406电介质322，随后继续进行蚀刻408，以形成源极/漏极接触沟槽，随后在沟槽中(及直接在源极/漏极区318/320上)选择性沉积410硼掺杂锗层317/319，如图5C到5E最佳示出的。可以使用任何适合的沉积工艺来实施沉积410，诸如选择性外延生长。一旦提供了层317/319，可以在层317/319的顶上提供接触部金属325/327，如图5F所示。这个替换的方法提供了相同的改善接触电阻的益处，但在沉积硼掺杂锗的位置处更具有选择性。根据本公开内容，使用掩模/图案化和选择性沉积技术的任何适当的组合，其它这种选择性沉积工艺会是显而易见的。
如会进一步理解的，在前针对方法的类似部分进行的相关论述也同等地适用于此。具体地，可以如先前参照参考图2在前论述的形成202和定义204论述的那样来实施：形成402栅极堆叠体和定义404晶体管结构的源极/漏极区。类似地，可以如先前参照参考图2在前论述的形成212和定义214论述的那样来实施：沉积412接触电阻减小金属和退火，以形成硅化物/锗化物，及随后沉积414源极/漏极接触插塞。
FinFET结构
众所周知，FinFET是围绕半导体材料的薄带(通常称为鳍)构造的晶体管。晶体管包括标准场效应晶体管(FET)节点，包括栅极、栅极电介质、源极区和漏极区。器件的导电沟道位于栅极电介质下方鳍的外侧上。具体地，电流沿鳍的两个侧壁(垂直于衬底表面的侧面)以及鳍的顶部(平行于衬底表面的侧面)流动。因为这种结构的导电沟道的位置基本上沿着鳍的三个不同的外部平面区，这种FinFET设计有时称为三栅极FinFET。其他类型的FinFET结构也是可用的，诸如所谓的双栅极FinFET，在其中导电沟道的位置主要仅沿着鳍的两个侧壁(而不沿鳍的顶部)。
图6示出了根据本发明的一个实施例配置的示例性三栅极架构的透视图。如图所示，三栅极器件包括具有半导体主体或鳍660(由虚线表示)的衬底600，半导体主体或鳍660从衬底600通过隔离区610、620延伸。在鳍660的3个表面上形成栅极电极640以形成3个栅极。在栅极电极640的顶部上形成硬掩膜690。在栅极电极640的相反侧壁上形成栅极间隔体670、680。
源极区包括外延区631，其形成于凹陷的源极分界面650和一个鳍660侧壁上；漏极区包括外延区631，其形成于凹陷的源极分界面650和相反的鳍660侧壁(未示出)上。帽层641沉积在外延区631上。注意，可以在凹陷的(尖端)区中提供硼帽层641，但在其它实施例中，仅在源极/漏极区之上(不在凹陷区中)提供硼帽层641。在一个实施例中，隔离区610、620是使用传统技术形成的浅槽隔离(STI)区，所述传统技术诸如蚀刻衬底600以形成沟槽，随后将氧化物材料沉积在沟槽上，以形成STI区。隔离区610、620可以由诸如SiO2的任何适合的电介质/绝缘材料制成。先前针对衬底102的论述在此也是同等适用的(例如，衬底800可以是硅衬底，或SOI衬底，或多层衬底)。
如根据本公开内容会理解的，传统工艺和形成技术可以用于制造FinFET晶体管结构。但根据本发明的一个示例性实施例，例如可以使用以硼掺杂锗覆盖的原位掺杂硅或SiGe(对于631)来实现外延区631和帽层641的双层结构，在两个双层之间具有可任选的锗和/或硼的分级的缓冲部。如前解释的，这种缓冲部可以用于从与外延区631相容的基准级别锗/硼浓度过渡到硼掺杂锗帽层641。可替换地，可以直接在外延区631和/或帽层641中而不是在居间的分级缓冲部布置中实现锗和/或硼浓度分级。如会进一步理解的，注意到三栅极结构的可替换方式是双栅极架构，其包括在鳍660顶部上的电介质/隔离层。
图7示出了分批图，该分批图示出根据本发明实施例配置的晶体管结构和没有配置帽层的标准晶体管结构的接触电阻。与超过0.18的高电阻值相关的晶体管结构全部以标准SiGe合金抬高的PMOS源极/漏极区实现，所述PMOS源极/漏极区具有直接沉积在其上的接触部金属。根据本发明的多个实施例，类似地实现全部与0.107及更低的电阻值相关的晶体管结构，但增加了在源极/漏极区与接触部金属之间的硼掺杂锗帽层。表1示出了由对具有或不具有本文所述的硼掺杂锗帽层的示例性结构的测试得到的原始数据分位数。
Ge帽层 最小 10％ 25％ 中值 75％ 90％ 最大
是 0.032 0.032 0.033 0.040 0.078 0.105 0.107
否 0.183 0.183 0.192 0.239 0.250 0.265 0.265
表1
可以看出，这个示例性批次实际显示了对传统晶体管结构的约三到六倍(3X到6X)的接触电阻的改善(减小)。单位是Ohm/任意区。
根据本公开内容，通过使用根据本发明的实施例的硼掺杂锗帽层而实现的其它改进会是显而易见的。具体地，根据本发明的一些示例性实施例，所得到的锗化物材料和肖特基势垒高度改进相对于传统SiGe源极/漏极PMOS器件实现了大于2倍的Rext的改善。众所周知，肖特基势垒高度是横跨半导体-金属结的电传导的势垒。肖特基势垒高度的量值反应了金属的费米能级的势能与横跨半导体-金属分界面的半导体的多数载流子能带边缘的不匹配。对于p型半导体-金属分界面，肖特基势垒高度是金属费米能级与半导体的价带最大值之间的差。
示例性系统
图8示出了根据本发明的一个实施例配置的计算设备1000。如图所示，计算设备1000容纳母板1002。母板1002可以包括多个部件，包括但不限于处理器1004和至少一个通信芯片1006，其每一个都可以物理和电气耦合到母板1002，或者集成于其中。会理解，母板1002例如可以是任何印刷电路板，不论是主板还是安装在主板上的子板或者设备1000的唯一的板等。根据其应用，计算设备1000可以包括一个或多个其他部件，其可以也可以不物理和电气耦合到母板1002。这些其他部件可以包括，但不限于，易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、和大容量存储设备(例如硬盘驱动器、压缩盘(CD)、数字多功能盘(DVD)等等)。包括在计算设备1000中的任何部件都可以包括本文所述的一个或多个晶体管结构。在一些实施例中，多个功能可以集成到一个或多个芯片中(例如，注意通信芯片1006可以是处理器1004的一部分，或者集成到处理器1004中)。
通信芯片1006实现了无线通信，用于往来于计算设备1000传递数据。术语“无线”及其衍生词可以用于描述电路、设备、系统、方法、技术、通信信道等，其可以借助使用通过非固态介质的调制的电磁波辐射来传送数据。该术语并非暗示相关设备不包含任何线路，尽管在一些实施例中可以没有线路。通信芯片1006可以执行许多无线标准或协议中的任意无线标准或协议，包括但不限于Wi-Fi(IEEE802.11族)、WiMAX(IEEE802.16族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物，以及指定作为3G、4G、5G及更高代的任何其他无线协议。计算设备1000可以包括多个通信芯片1006。例如，第一通信芯片1006可以专用于较短距离无线通信，诸如Wi-Fi和蓝牙，第二通信芯片1006可以专用于较长距离无线通信，诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
计算设备1000的处理器1004包括封装在处理器1004内的集成电路管芯。在本发明的一些实施例中，处理器的集成电路管芯包括板载非易失性存储器或高速缓存、和/或可通信地耦合到片外存储器，它是以本文所述的一个或多个晶体管结构实现的。术语“处理器”可以指代任何设备或设备的部分，所述设备或设备的部分处理例如来自寄存器和/或存储器的电子数据，以将该电子数据转换为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片1006还可以包括封装在通信芯片1006内的集成电路管芯。根据一些这种示例性实施例，通信芯片的集成电路管芯包括以本文所述的一个或多个晶体管结构实现的一个或多个器件。根据本公开内容会理解，注意多标准无线功能可以直接集成在处理器1004中(例如，任何芯片1006的功能都集成到处理器1004中，而不是具有分离的通信芯片)。此外注意，处理器1004可以是具有这种无线功能的芯片组。简而言之，可以使用许多处理器1004和/或通信芯片1006。类似地，任意一个芯片或芯片组都可以具有集成在其中的多个功能。
在多个实施方式中，计算设备1000可以是膝上型电脑、上网本、笔记本电脑、智能电话、平板电脑、个人数字助理(PDA)、超便携移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器、或数字视频录像机。在进一步的实施方式中，设备1000可以是处理数据或使用晶体管的任何其他电子设备。
根据本公开内容许多实施例将是显而易见的，本文所述的特征可以组合到许多结构中。本发明的一个示例性实施例提供了一种晶体管器件。该器件包括具有沟道区的衬底和在沟道区上的栅极电极。在栅极电极与沟道区之间提供了栅极电介质层，在衬底中并与沟道区相邻地提供了源极和漏极区。器件进一步包括在源极和漏极区的至少一部分上的硼掺杂锗层。这个硼掺杂锗层包括超过90原子％的锗浓度和超过1E20cm-3的硼浓度。器件进一步包括在硼掺杂锗层上的金属-锗化物源极和漏极接触部。在一个这种实例中，器件是平面或FinFET晶体管中的一个。在另一个示例性情况下，器件包括PMOS晶体管。在另一个示例性情况下，器件进一步包括层间电介质。在另一个示例性情况下，器件进一步包括在衬底与源极和漏极区之间的分级的缓冲部，和/或在源极和漏极区与硼掺杂锗层之间的分级的缓冲部。在一个这种情况下，在源极和漏极区与硼掺杂锗层之间的分级的缓冲部具有从与源极和漏极区相容的基准级别浓度到超过95原子％的高浓度分级的锗浓度。在一个这种特定的示例性情况下，高浓度反映纯锗。在另一个示例性情况下，在源极和漏极区与硼掺杂锗层之间的分级的缓冲部具有从与源极和漏极区相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在另一个示例性情况下，硼掺杂锗层具有锗和硼中至少一个的分级的浓度。在另一个示例性情况下，源极和漏极区包括硅锗，其具有从与衬底相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，硼掺杂锗层具有超过95原子％的锗浓度。在另一个示例性情况下，源极和漏极区包括硼掺杂硅锗，其具有从与衬底相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在另一个示例性情况下，源极和漏极区包括硅或硅锗，器件进一步包括在源极和漏极区与硼掺杂锗层之间的缓冲部，缓冲部具有从与源极和漏极区相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，和从与源极和漏极区相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在另一个示例性情况下，硼掺杂锗层包括超过98原子％的锗浓度，和超过2E20cm-3的硼浓度。另一个实施例提供了一种电子设备，其包括具有一个或多个集成电路的印刷电路板，其中，所述一个或多个集成电路中的至少一个包括如在该段落中不同定义的一个或多个晶体管器件。在一个这种情况下，所述一个或多个集成电路包括至少一个通信芯片和/或处理器，至少一个通信芯片和/或处理器包括所述一个或多个晶体管器件。在另一个这种情况下，设备是计算设备(例如，移动电话或智能电话、膝上型电脑、平板电脑等)。
本发明的另一个实施例提供了一种晶体管器件。在这个示例性情况下，该器件包括具有沟道区的衬底和在沟道区上方的栅极电极，其中，在栅极电极与沟道区之间提供了栅极电介质层，在栅极电极的侧面上提供了间隔体。器件进一步包括在衬底中并与沟道区相邻的源极和漏极区，源极与漏极区中的每一个都包括尖端区，其在栅极电介质层和/或对应的一个间隔体下方延伸。器件进一步包括在源极和漏极区的至少一部分上的硼掺杂锗层，并包括超过95原子％的锗浓度和超过2E20cm-3的硼浓度。器件进一步包括在硼掺杂锗层上的金属-锗化物源极和漏极接触部。器件是平面或FinFET晶体管之一。在一个这种示例性情况下，器件进一步包括在源极和漏极区与硼掺杂锗层之间的缓冲部，其中，缓冲部具有从与源极和漏极区相容的基准级别浓度到超过95原子％的高浓度分级的锗浓度，和从与源极和漏极区相容的基准级别浓度到超过2E20cm-3的高浓度分级的硼浓度。在另一个示例性情况下，硼掺杂锗层具有锗和硼至少其中之一的分级的浓度。在另一个示例性情况下，源极和漏极区包括硅锗，其具有从与衬底相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，硼掺杂锗层具有超过98原子％的锗浓度。在另一个示例性情况下，源极和漏极区具有从与衬底相容的基准级别浓度到超过2E20cm-3的高浓度分级的硼浓度。在另一个示例性情况下，源极和漏极区包括硅锗，其具有固定的锗浓度，器件进一步包括在源极和漏极区与硼掺杂锗层之间的缓冲部，其中，缓冲部具有从与源极和漏极区相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，和从与源极和漏极区相容的基准级别浓度到超过2E20cm-3的高浓度分级的硼浓度，缓冲部具有小于100埃的厚度。另一个实施例提供了一种计算设备(例如，台式计算机或便携式计算机等)，其包括具有通信芯片和/或处理器的印刷电路板，其中，至少一个通信芯片和/或处理器包括如在该段落中不同定义的一个或多个晶体管器件。
本发明的另一个实施例提供了一种用于形成晶体管器件的方法。该方法包括提供具有沟道区的衬底，及在沟道区上提供栅极电极，其中，在栅极电极与沟道区之间提供了栅极电介质层。该方法继续，在衬底中并与沟道区相邻地提供源极和漏极区，在源极与漏极区的至少一部分上提供硼掺杂锗层。硼掺杂锗层包括超过90原子％的锗浓度和超过1E20cm-3的硼浓度。该方法继续，在硼掺杂锗层上提供金属-锗化物源极和漏极接触部。在一些示例性的这种情况下，该方法进一步包括在衬底与源极和漏极区之间提供分级的缓冲部，和/或在源极和漏极区与硼掺杂锗层之间提供分级的缓冲部，在另一个示例性情况下，硼掺杂锗层具有锗和硼的至少其中之一的分级的浓度(其可以与或不与分级的缓冲部一起使用)。例如，这个方法可以用于诸如计算设备的任何电子设备的制造中。
出于图示和说明的目的提供了对本发明的示例性实施例的前述说明。其并非旨在是穷举性的或将本发明限制于所公开的准确形式。根据本公开内容，许多修改和变化是可能的。其意图是本发明的范围不局限于该具体实施方式部分，而是由所附的权利要求限定。

Claims (20)

1.一种晶体管器件，包括：
具有沟道区的衬底；
与所述沟道区相邻的源极区和漏极区；以及
在所述源极区和所述漏极区的至少一部分上的硼掺杂锗层，所述硼掺杂锗层具有超过90原子％的锗浓度和超过1E20cm-3的硼浓度。
2.根据权利要求1所述的器件，其中，所述器件是平面晶体管或FinFET晶体管中的一种。
3.根据权利要求1所述的器件，其中，所述器件包括PMOS晶体管。
4.根据权利要求1所述的器件，进一步包括以下的至少一个：
位于所述沟道区上方的栅极电极，其中，在所述栅极电极与所述沟道区之间提供了栅极电介质层；
在所述硼掺杂锗层上的第一金属-锗化物接触部和第二金属-锗化物接触部，所述第一金属-锗化物接触部和所述第二金属-锗化物接触部分别位于所述源极区和所述漏极区中的对应的一个之上；以及
层间电介质。
5.根据权利要求1所述的器件，进一步包括以下的至少一个：
在所述衬底与所述源极区和所述漏极区之间的分级的缓冲部；以及
在所述源极区和所述漏极区中的至少一个与所述硼掺杂锗层之间的分级的缓冲部。
6.根据权利要求5所述的器件，其中，在所述源极区和所述漏极区中的至少一个与所述硼掺杂锗层之间的分级的缓冲部的锗浓度被分级为从与所述源极区和所述漏极区相容的基准级别浓度到超过95原子％的高浓度。
7.根据权利要求6所述的器件，其中所述高浓度反映纯锗。
8.根据权利要求5所述的器件，其中，在所述源极区和所述漏极区中的至少一个与所述硼掺杂锗层之间的分级的缓冲部的硼浓度被分级为从与所述源极区和所述漏极区相容的基准级别浓度到超过1E20cm-3的高浓度。
9.根据权利要求1所述的器件，其中，所述硼掺杂锗层具有锗和硼中的至少一个的分级的浓度。
10.根据权利要求9所述的器件，其中，所述硼掺杂锗层的锗浓度被分级为从与所述衬底相容的基准级别浓度到超过90原子％的高浓度。
11.根据权利要求9所述的器件，其中，所述硼掺杂锗层的硼浓度被分级为从与所述衬底相容的基准级别浓度到超过1E20cm-3的高浓度。
12.根据权利要求1所述的器件，其中，所述源极区和所述漏极区包括硅或硅锗，并且所述器件进一步包括在所述源极区和所述漏极区与所述硼掺杂锗层之间的缓冲部，所述缓冲部的锗浓度被分级为从与所述源极区和所述漏极区相容的基准级别浓度到超过50原子％的高浓度，所述缓冲部的硼浓度被分级为从与所述源极区和所述漏极区相容的基准级别浓度到超过1E20cm-3的高浓度。
13.根据权利要求1所述的器件，其中，所述硼掺杂锗层具有超过98原子％的锗浓度和超过2E20cm-3的硼浓度。
14.一种电子设备，包括：
印刷电路板，其具有一个或多个集成电路，其中，所述一个或多个集成电路中的至少一个集成电路包括一个或多个根据权利要求1所述的晶体管器件。
15.一种晶体管器件，包括：
具有沟道区的衬底；
在所述沟道区上方的栅极电极，其中，在所述栅极电极与所述沟道区之间提供了栅极电介质层，在所述栅极电极的侧面上提供了间隔体；
与所述沟道区相邻的源极区和漏极区，所述源极区和所述漏极区中的每一个都包括尖端区，所述尖端区在所述栅极电介质层和/或对应的一个所述间隔体下方延伸；
在所述源极区和所述漏极区的至少一部分上的硼掺杂锗层，所述硼掺杂锗层具有超过95原子％的锗浓度和超过2E20cm-3的硼浓度；以及
在所述硼掺杂锗层上的第一金属-锗化物接触部和第二金属-锗化物接触部，所述第一金属-锗化物接触部和所述第二金属-锗化物接触部分别位于所述源极区和所述漏极区中的对应的一个之上；
其中，所述器件是平面晶体管或FinFET晶体管中的一种。
16.根据权利要求15所述的器件，其中，所述硼掺杂锗层具有锗和硼中的至少一个的分级的浓度。
17.根据权利要求16所述的器件，其中，所述硼掺杂锗层的锗浓度被分级为从与所述衬底相容的基准级别浓度到超过90原子％的高浓度。
18.根据权利要求16所述的器件，其中，所述硼掺杂锗层的硼浓度被分级为从与所述衬底相容的基准级别浓度到超过1E20cm-3的高浓度。
19.一种用于形成晶体管器件的方法，包括：
提供具有沟道区的衬底；
在所述沟道区上方提供栅极电极，其中，在所述栅极电极与所述沟道区之间提供了栅极电介质层；
与所述沟道区相邻地提供源极区和漏极区；
在所述源极区和所述漏极区中的至少一部分上提供硼掺杂锗层，所述硼掺杂锗层具有超过90原子％的锗浓度和超过1E20cm-3的硼浓度；
在所述硼掺杂锗层上且在所述源极区之上提供第一金属-锗化物接触部；以及
在所述硼掺杂锗层上且在所述漏极区之上提供第二金属-锗化物接触部。
20.根据权利要求19所述的方法，其中，所述硼掺杂锗层具有锗和硼中的至少一个的分级的浓度。
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