CN105932063B - 用于pmos集成的iv族晶体管 - Google Patents

用于pmos集成的iv族晶体管 Download PDF

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CN105932063B
CN105932063B CN201610340122.4A CN201610340122A CN105932063B CN 105932063 B CN105932063 B CN 105932063B CN 201610340122 A CN201610340122 A CN 201610340122A CN 105932063 B CN105932063 B CN 105932063B
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germanium
silicon
source
atomic
drain
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CN105932063A (zh
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G·A·格拉斯
A·S·默西
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Intel Corp
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Intel Corp
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

公开了用于形成IV族晶体管器件的技术，其具有含高浓度锗的源极/漏极区，且相对于常规器件展示了减小的寄生电阻。在一些示例性实施例中，源极/漏极区每一个都包括薄p型硅或锗或SiGe沉积，剩余源极/漏极材料沉积是p型锗或锗合金(例如锗:锡或其他适合的应变诱导物，具有至少80原子％的锗含量，和20原子％或更少的其他成分)。在一些情况下，可以在这个富锗帽层中观察到应变弛豫的证据，包括错配位错和/或穿透位错和/和双晶。可以使用多种晶体管结构，包括平面和非平面晶体管结构(例如，FinFET和纳米线晶体管)，以及应变的和未应变的沟道结构。

Description

用于PMOS集成的IV族晶体管
本申请为分案申请，其原申请是于2013年6月21日(国际申请日为 2011年12月20日)向中国专利局提交的专利申请，申请号为 201180062107.3，发明名称为“用于PMOS集成的IV族晶体管”。
相关申请
本申请是2010年12月21日提交的美国申请No.12/975278的部分继续 申请，并要求其优先权。
背景技术
包括形成于半导体衬底上的晶体管、二极管、电阻器、电容器及其他 无源和有源电子器件的电路器件的提高的性能，通常是在这些器件的设计、 制造和操作过程中考虑的主要因素。例如，在金属氧化物半导体(MOS) 晶体管半导体器件(例如在互补金属氧化物半导体(CMOS)中所使用的那 些)的设计和制造或形成的过程中，常常希望使得与接触部相关的寄生电 阻(或者称为外电阻Rext)最小化。减小的Rext能够由相等的晶体管设计 实现较高的电流。
附图说明
图1示意性地示出了包括源极和漏极尖端区的典型MOS晶体管的电阻 的成分(component)。
图2是根据本发明实施例的形成IV族晶体管的方法。
图3A到3F示出了根据本发明多个实施例的在实施图2的方法时形成 的结构。
图4A到4G均示出了根据本发明一个实施例形成的FinFET晶体管结 构的透视图。
图5A与5B均示出了根据本发明实施例形成的纳米线晶体管结构的透 视图。
图6示出了以根据本发明示例性实施例的一个或多个晶体管结构实现 的计算系统。
会理解，附图不一定是按照比例绘制的，或者旨在将所要求保护的发 明局限于所示出的特定结构。例如，尽管一些图形总体上表示直线、直角 和平滑表面，但考虑到所用的处理设备和技术的现实世界的限制，晶体管 结构的实际实施方式可以具有不太完美的直线、直角，一些特征可以具有 表面拓扑，或者是非平滑的。总之，提供附图仅用于示出示例性结构。
具体实施方式
公开了用于形成IV族晶体管器件的技术，所述IV族晶体管器件具有 含高浓度锗的源极和漏极区，相对于常规器件展示了减小的寄生电阻。在 一些示例性实施例中，得到的晶体管结构的源极/漏极区均包括薄p型硅或 锗或硅锗(SiGe)衬里层，剩余源极/漏极材料是p型锗或例如包括锗和锡 的锗合金，并具有至少80原子％的锗含量(20原子％或更少的其他成分， 例如锡和/或其他适合的应变诱导物)。在一些示例性情况下，可以在这个富锗层中观察到应变弛豫的证据，包括错配位错和/或穿透位错。根据本公开 内容多个晶体管结构和适合的制造工艺会是显而易见的，包括平面和非平 面晶体管结构(例如，FinFET和纳米线晶体管)，以及应变的和未应变的沟 道结构。这些技术尤其适合于实现p型MOS(PMOS)器件，但也有益于 其他晶体管结构。
概述
如前解释的，通常可以通过减小器件的外电阻Rext来实现晶体管中增 大的驱动电流。但如参考图1所见的，PMOS晶体管性能是器件内的多个 成分电阻的函数。可以通过载流子迁移率来调节沟道电阻R1，其是沟道内 压缩应变的函数。器件的外电阻Rext包括尖端电阻R2(尖端区也称为源极 /漏极延伸部)、源极/漏极电阻R3和接触电阻R4(金属与半导体)。所有这 些部分电阻都具有材料成分(例如，横跨分界面的能量势垒，载流子浓度 和迁移率)、几何形状成分(例如，长度、宽度等)、和动态电负荷成分(电 流拥塞)。
因此，根据本发明的一些实施例，以p型薄衬里和高含量锗(具有极 高的p型掺杂浓度)替换源极/漏极区中通常的硅或SiGe合金材料使得外电 阻成分(R2、R3和R4)最小化。另外，通过引入高压缩应变的材料，使 得沟道空穴迁移率最大化，或者被增大了，从而减小了沟道电阻(R1)。减 小的沟道、尖端、源极/漏极和接触电阻的净影响是对于给定电压(相对于 阈值电压Vt，即V-Vt)的改进的晶体管电流。
在一些示例性情况下，薄衬里是p型掺杂的硅或锗或SiGe合金，通常 小于总源极/漏极沉积层的厚度的50％。剩余源极/漏极沉积层的厚度通常大 于总源极/漏极沉积层的厚度的50％，并且例如可以是p型掺杂的锗或锗合 金，诸如锗:锡或锗:锡:x(其中，x例如是硅或其他少量成分或基于工艺-扩 散的人工制品)，其具有至少80原子％的锗和20原子％或更少的其他成分 (例如，锡和/或任何其他适合的应变诱导物和/或其他少量无意的成分)。 在一些特定的这种示例性实施例中，源极/漏极衬里与高浓度锗帽层的厚度 比约为1:5或更小(其中，衬里构成约20％或更少的总源极/漏极沉积层厚 度)。在一些这种示例性情况下，衬里的厚度是一到几个单层。
这些技术可以用于形成许多设备和系统中的晶体管器件。在一些实施 例中，诸如具有n型MOS(NMOS)和PMOS晶体管的CMOS器件，可以 以多种方式实现选择性。在一个实施例中，例如可以通过在PMOS沉积过 程中将NMOS区掩蔽掉来避免在NMOS源极/漏极位置上的沉积。在其他 实施例中，选择性可以包括自然选择性。例如，在硼掺杂锗在p型SiGe(或 硅)源极/漏极区上生长时，它不在诸如氧化硅(SiO2)或氮化硅(SiN)的 绝缘体表面上生长；它也不在例如n型区中露出的重磷掺杂硅上生长。
本文提供的技术可以用于改进许多晶体管结构和配置中的器件电阻， 包括平面、平齐或隆起的源极/漏极，非平面(例如，纳米线晶体管和鳍型 晶体管，诸如双栅极和三栅极晶体管结构)，以及应变的和未应变的沟道结 构。源极/漏极区可以凹陷(例如，使用蚀刻工艺)或不凹陷(例如，在衬 底的顶面上形成)。另外，晶体管器件可任选地包括源极和漏极尖端区，例 如将其设计为减小晶体管的总电阻，同时改进短沟道效应(SCE)，但这种 极端区不是必需的。晶体管器件可以进一步包括许多栅极结构，诸如多晶 栅极、高-k电介质金属栅极、置换金属栅极(RMG)工艺栅极，或任何其 他栅极结构。许多结构特征可以结合本文所述的低电阻晶体管技术来使用。
根据一些实施例，垂直于栅极线的透射电子显微镜法(TEM)横截面 或次级离子质谱法(SIMS)分布图(profile)可以用于显示结构中的锗浓 度，因为可以易于区分硅和SiGe的外延合金的分布图与高锗浓度分布图。 在一些这种包含硅的衬底的情况下，不考虑保留应变的(无位错的)源极/ 漏极区的通常要求，在源极/漏极填充材料与硅沟道之间的晶格尺寸不匹配 对于纯锗而言会增大至少两倍，而对于锗-锡合金而言会更大。尽管在位错 存在于富锗帽层中的情况下不是100％的应变都能够传递到沟道，但沉积后 热处理可以用于提供明确的晶体管性能(在给定V-Vt的电流)改进，即使 对于相对于应变的SiGe控制的(如本文所述的)弛豫膜而言也是如此。会 理解，弛豫通常意味着膜可以有错配位错存在，但也可以指代塑性弛豫机 制，其涉及位错形成和传播。弹性弛豫的工艺在诸如FinFET(例如，三栅 极)和纳米线结构的非平面结构中变得可能，其中，应变的材料没有完全 由衬底约束。这样，面内晶格常数独立于衬底扩展或缩小的灵活性更大， 这个工艺无需错配位错的形成和传播。从此开始，词语弛豫是塑性弛豫的 意思，而不是弹性弛豫的意思。本文所述的用以使高浓度锗帽层成为合金 的锡或其他适合的应变诱导物的使用可任选地用于增大沟道区中的应变， 从而借助减小图1中的电阻R1进一步减小总器件电阻。会进一步理解，尽 管期望有无缺陷的纯锗，但通常对于例如在硅衬底或者即使是具有比方说 50原子％锗的SiGe衬底上的沉积而言难以无缺陷地生长。但令人惊讶地， 如果典型的充分应变的Sie层与具有某些缺陷(例如，有错配位错和/或穿 透位错)的这种富锗层的性能相比，那么有缺陷的富锗层的性能会更好。 会理解，这个结果总体上并非直观的，因为它与传统的对于薄膜的理解相 背。无论如何，本发明的一些实施例可以包括缺少诸如错配位错、穿透位 错和双晶(twin)(由横跨双晶面的晶格取向中的变化引起的缺陷)之类的 晶体特征的富锗帽层，而其他实施例可以包括具有一个或多个此类特征的 富锗帽层。
架构和方法
图2是根据本发明实施例的形成IV族晶体管的方法。图3A到3F示出 了根据多个实施例的在实施图2的方法时形成的示例性结构。在制造例如 处理器或通信芯片或存储器芯片时可以形成一个或多个这种晶体管。这种 集成电路于是可以用于多种电子设备和系统。
示例性方法包括在其上可以形成MOS器件的半导体衬底上形成202一 个或多个栅极堆叠体。MOS器件例如可以包括PMOS晶体管或NMOS和 PMOS晶体管两者(例如，用于CMOS器件)。图3A示出了示例性的得到 的结构，在此情况下其包括形成于衬底300上的PMOS晶体管。如所见到 的，在沟道区上形成了栅极堆叠体，该栅极堆叠体包括栅极电介质层302、 栅极电极304和可任选的硬掩模306。相邻于栅极堆叠体形成间隔体310。
栅极电介质302例如可以是任何适合的氧化物，诸如氧化硅(SiO2)或 高-k栅极电介质材料。高-k栅极电介质材料的实例例如包括二氧化铪、铪 硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、氧化钛、 钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化 物、和铌锌酸铅。在一些实施例中，在使用高-k材料时，可以在栅极电介 质层302上实施退火工艺，以改进其质量。在一些特定的示例性实施例中， 高-k栅极电介质层302可以具有到约厚(例如，)范围中 的厚度。在其他实施例中，栅极电介质层302可以具有一个单层氧化物材 料的厚度。通常，栅极电介质层302的厚度应足以使得栅极电极304与源 极和漏极接触部电隔离。在一些实施例中，可以在高-k栅极电介质层302 上执行额外的处理，诸如退火工艺，以改进高-k材料的质量。
栅极电极304的材料例如可以是多晶硅、氮化硅、碳化硅或金属层(例 如，钨、氮化钛、钽、氮化钽)，尽管也可以使用其他适合的栅极电极材料。 在一些示例性实施例中，栅极电极304的材料可以是稍后为了置换金属栅 极(RMG)工艺而去除掉的牺牲材料，其具有约到(例如， )范围中的厚度。
可任选的栅极硬掩模层306可以用于在处理过程中提供某些益处或用 途，诸如保护栅极电极304使其免于随后的蚀刻和/或离子注入工艺。可以 使用诸如氧化硅、氮化硅、和/或其他常规绝缘体材料等典型的硬掩模材料 来形成硬掩模层306。
可以按照传统所进行的那样或者使用任何适合的定制技术(例如，传 统的构图工艺，以蚀刻掉部分栅极电极和栅极电介质层，从而形成栅极堆 叠体，如图2A所示)来形成栅极堆叠体。例如可以使用诸如化学气相沉积 (CVD)、原子层沉积(ALD)、旋涂沉积(SOD)、或物理气相沉积(PVD) 的传统沉积工艺来形成栅极电介质302和栅极电极304材料中的每一个。 也可以使用替换的沉积技术，例如可以热生长栅极电介质层302和栅极电 极304材料。根据本公开内容会理解，许多其他适合的材料、几何形状和 形成工艺都可以用于实现本发明的实施例，以便提供本文所述的低电阻晶 体管器件或结构。
例如可以使用诸如氧化硅、氮化硅或其他适合的间隔体材料的常规材 料来形成间隔体310。通常可以基于对所形成晶体管的设计要求来选择间隔 体310的宽度。然而根据一些实施例，间隔体310的宽度不受形成源极和 漏极尖端区所施加的设计约束的支配，只要在源极/漏极尖端区中有足够高 的p-掺杂锗含量(例如硼掺杂锗)或Sie合金衬里。
许多适合的衬底都可以用于实现衬底300，包括块体衬底、绝缘体上半 导体衬底(XOI，其中，X是诸如硅、锗或富锗的硅之类的半导体材料)、 多层结构，包括在随后的栅极构图工艺前可以在其上形成鳍或纳米线的那 些衬底。在一些特定示例性情况下，衬底300是锗或硅或SiGe块体衬底、 或者在氧化物衬底上的锗或硅或SiGe。尽管在此说明了可以形成衬底300 的材料的几个实例，但可以充当在其上可以构造低电阻晶体管器件的基础 的其他适合的材料也在所要求保护的本发明的精神和范围内。
进一步参考图3A，在形成一个或多个栅极堆叠体后，该方法继续进行 一些可任选的处理，在这个示例性实施例中所述处理包括蚀刻204晶体管 结构的源极/漏极区，并掩蔽206结构的任何NMOS源极/漏极区(如果存 在的话)。会理解，源极/漏极区不必是凹陷的或者被蚀刻。在这种情况下， 可以在不蚀刻的情况下在衬底300上形成源极/漏极材料。尽管这种非凹陷 的源极/漏极区不会影响沟道电阻，但根据一些实施例，仍可以实现具有薄 衬里和高锗含量帽层的双层源极/漏极结构，以提供低接触电阻。会进一步 理解，并非全部实施例都将包括n型区。在一些示例性情况下，例如制造 的电路可以仅包括PMOS器件。在这种示例性情况下，就没有要掩蔽的n 型源极/漏极区。当存在n型区时，任何适合的掩蔽技术都可以用于在p型 处理过程中保护n型区。
在蚀刻源极/漏极区的示例性实施例中，得到了源极/漏极空腔312/314， 如图3A中最佳示出的。空腔实际上定义了源极/漏极区的位置。如可以进 一步看出的，蚀刻衬底300不仅用以提供源极/漏极空腔312/314，还提供了 其相应的尖端区域312A/314A，它们底切栅极电介质302。可以使用许多适 合的工艺按照传统上所进行的那样来形成空腔312/314及其相应的尖端区 域312A/314A。在一些示例性情况下，这包括向与栅极堆叠体相邻的衬底 300的高掺杂部分的离子注入，随后是退火以驱使掺杂剂进一步进入到衬底 300中，以改进预期源极/漏极区域的蚀刻速率。干法蚀刻工艺随后可以用 于蚀刻衬底300的掺杂区，以形成空腔312/314及其相应的尖端区域 312A/314A。在完成干法蚀刻工艺后，例如可以使用湿法蚀刻来清洗并进一 步蚀刻空腔312/314及其相应的尖端区域312A/314A。可以使用传统或定制 的湿法蚀刻化学反应执行的这种湿法蚀刻可以用于去除诸如碳、氟、含氯氟烃及氧化物(诸如氧化硅)之类的污染物，以提供清洁的表面，在其上 可以实施随后的工艺。另外，假定是单晶硅衬底，湿法蚀刻还可以用于沿 <111>和<001>晶面去除衬底300的薄部分，以提供光滑表面，在其上可以 进行高质量的外延沉积。在一些示例性情况下，蚀刻掉的衬底300的薄部 分例如可以高达5nm厚，还可以去除残留的污染物。湿法蚀刻通常导致空腔312/314及其相应的尖端区域312A/314A的边缘遵循<111>和<001>晶面。
进一步参考图2，该方法继续进行在p型源极/漏极区中沉积208p型硅 或锗或Sie衬里313/315，随后在衬里313/315上的p型源极/漏极区中沉积 210p型锗或锗合金。每一个这些沉积例如都可以使用选择性外延沉积来实 施，尽管可以使用任何适合的沉积工艺。参考图3B可以看出，p型硅或锗 或SiGe衬里313/315沉积在空腔312/314及其相应的尖端区域312A/314A 中。另外，如图3C中最佳示出的，已经进一步填充了空腔312/314和尖端 区域312A/314A以在p型衬里313/315上提供p型锗或锗合金的厚帽层 318/320。会理解，示例性的p型掺杂剂例如包括硼、镓或任何其他适合的 p型掺杂剂，所要求保护的本发明并非旨在局限于任何特定的一种。
根据一些特定的示例性实施例，在衬底300是硅或SiGe块体衬底或绝 缘体上半导体衬底(XOI，其中，X是硅或SiGe)的情况下，以原位硼掺 杂硅或SiGe填充源极和漏极空腔312/314连同其相应的尖端区域 312A/314A，从而形成对应的衬里313/315，随后进一步以原位硼掺杂锗或 富锗合金填充，以提供帽层318/320。在其他示例性实施例中，在衬底300是锗块体衬底或绝缘体上锗衬底的情况下，可以以原位硼掺杂锗填充源极 和漏极空腔312/314连同其相应的尖端区域312A/314A，从而形成对应的衬 里313/315，随后进一步以原位硼掺杂富锗合金(诸如锗:锡)填充，以提供 帽层318/320。根据本公开内容会理解，取决于诸如衬底300的成分、对晶 格匹配/相容性的分级的使用、和总源极/漏极沉积的总预期厚度之类的因 素，衬里313/315和帽层318/320的相应的锗和p型掺杂剂浓度可以改变。根据本公开内容会理解，可以实现许多材料系统和p型掺杂配置。
例如，在具有硅或锗或SiGe衬底的一些示例性实施例中，衬里313/315 的锗浓度可以在20原子％到100原子％的范围中，硼浓度在1E20cm-3到 2E21cm-3的范围中。为了避免与下层含硅衬底的晶格失配，根据一些实施 例，可以将衬里313/315的锗浓度分级。例如，在一个这种实施例中，衬里 313/315可以是分级的硼掺杂SiGe层，具有从与从与下层硅或SiGe衬底300 相容的基准级别浓度到高达100原子％(或接近100原子％，诸如超过90 原子％或95原子％或98原子％)分级的锗成分。在一个特定的这种实施例 中，锗浓度可以在从40原子％或更小到超过98原子％的范围中。衬里 313/315内的硼浓度可以固定在例如高级别，或者可替换地可以是分级的。 例如，衬里313/315内的硼浓度可以从处于下层衬底300的或者与之相容的 基准浓度到预期的高浓度(例如，超过1E20cm-3，超过2E20cm-3，或超过 5E20cm-3)分级。在一些这种实施例中，硼掺杂锗帽层318/320具有超过 1E20cm-3的硼浓度，例如超过2E20cm-3，或超过2E21cm-3或者更高。可以 以参照衬里313/315所述的类似的方式来分级帽层318/320中的该硼浓度。 根据本公开内容会理解，在更普遍的意义上，必要时可以调整硼浓度，以 提供预期程度的导电性。帽层318/320的锗浓度例如可以固定在100原子％。 根据本公开内容会理解，可替换地，帽层318/320的锗浓度可以从低到高浓 度分级(例如，从20原子％到100原子％)，以负责应对在衬里313/315与 帽层318/320的预期峰值锗浓度之间的晶格失配。在其他的实施例中，以锗 合金来实现帽层318/320，其中，混合物例如可以是高达80原子％的锗和高 达20原子％的合金材料，在一些实施例中所述合金材料是锡。注意，会理 解，锡浓度(或其他合金材料)也可以是分级的。在一个这种情况下，以 帽层318/320中3到8原子％范围中的锡浓度增大了沟道应变(帽层318/320 的平衡原子百分比基本上是锗和任何梯度材料)。尽管存在弛豫，但晶格常 数仍相对较大，并能够在相邻沟道上施加相当大的应变。其他适合的锡浓 度会是显而易见的，其他适合的应变诱导物也是如此。
注意，借助纯锗衬底，可以以锗来实现衬里313/315，而无需分级。在 一些这种情况下，衬里313/315的锗浓度可以是固定的(例如，100原子％)， 可以以锗合金(例如，锗:锡，如前所述的或者其他适合的锗合金)来实现 帽层318/320。如前解释的，可以对帽层318/320中的锗浓度(或锡或其他 合金材料浓度)进行分级以实现预期的沟道应变。在一些这种情况下，进 一步注意，锗衬里313/315可以有效地与锗合金帽层318/320集成在一起，或者是源极/漏极区沉积的无法觉察的成分。
对于分级，注意，本文所用的相容性并非必须要求浓度级别重叠(例 如，下层衬底300的锗浓度可以是0到20原子％，衬里313/315的初始锗 浓度可以是30到40原子％)。另外，本文所用的相对于浓度级别的词语“固 定”旨在表示相对恒定的浓度级别(例如，层中最低浓度级别在该层内最 高浓度级别的10％以内)。在更普遍的意义上，固定的浓度级别旨在表示缺 少有意分级的浓度级别。
衬里313/315和帽层318/320的厚度也可以根据诸如衬底300的成分、 对晶格匹配/相容性的分级的使用、和总源极/漏极沉积的总预期厚度之类的 因素而改变。通常，在以分级的锗含量配置衬里313/315以提供与衬底300 的相容性的情况下(其中衬底300不具有或者具有低锗含量)，衬里313/315 可以较厚。在衬底300是锗衬底或包含相对高的锗浓度的其他情况下，衬 里313/315不必被分级，因此可以相对较薄(例如，1到几个单层)。在衬底不具有或具有低锗含量的其他情况下，可以以相对薄的硅层或低锗含量 材料来实现衬里313/315，帽层318/320的锗含量可以按相容性所需来进行 分级。在任何这种情况下，衬里313/315通常组成小于50％的总源极/漏极 沉积层厚度，剩余的源极/漏极沉积层厚度通常大于50％的总源极/漏极沉积 层厚度。根据衬里313/315不分级的一些这种示例性实施例，衬里313/315 与帽层318/320的厚度比约为2:5或更小(即，衬里组成约40％或更小的总源极/漏极沉积层厚度)。在一些特定的这种实施例中，衬里313/315与帽层 318/320的厚度比约为1:5或更小(即，其中衬里组成约20％或更小的总源 极/漏极沉积层厚度)。在一个这种特定的示例性情况下，衬里313/315的厚 度在1到几个单层到约10nm范围中，总源极/漏极沉积层厚度在50到500nm 范围中。根据本公开内容，多种源极/漏极衬里和帽层几何形状和材料配置 会是显而易见的。
根据本公开内容会理解，可以以本发明的实施例实现许多其他晶体管 特征。例如，沟道可以是应变或未应变的，源极/漏极区可以包括或不包括 尖端区，其形成于对应的源极/漏极区与沟道区之间的区域中。在此意义上， 无论晶体管结构具有应变的或者未应变的沟道，或者源极/漏极尖端区，或 者没有源极/漏极尖端区都并非特别相关于本发明的多个实施例，所要求保 护的本发明并非旨在局限于任何特定的这种结构特征。相反，许多晶体管 结构和类型，尤其是具有p型或者同时具有n型和p型源极/漏极晶体管区 的那些结构，都可以得益于使用本文所述的具有衬里和高锗浓度帽层的双 层源极/漏极结构。
CVD工艺或其他适合的沉积技术可以用于沉积208和210。例如，可 以在CVD反应器、LPCVD反应器或超高真空CVD(UHVCVD)中实施沉 积208和210。在一些示例性情况下，反应器温度例如可以在600℃到800℃ 之间，反应器压力例如可以在1到760Torr之间。载运气体例如可以包括 在诸如10到50SLM之间的适当流速的氢或氦。在一些特定实施例中，可 以使用诸如GeH4的锗源前驱气体来实施沉积，其在H2中被稀释(例如， 可以将GeH4稀释为1-20％)。例如，可以以1％的浓度和50到300SCCM 范围的流速来使用稀释的GeH4。对于硼的原位掺杂，可以使用稀释的B2H6 (例如，可以在H2中将B2H6稀释为1-20％)。例如，可以以3％的浓度和 10到100SCCM范围的流速来使用稀释的B2H6。在一些示例性情况下，可 以增加蚀刻剂，以增大沉积的选择性。例如，可以以50到300SCCM范围 的流速添加HCl或Cl2。
根据本公开内容，源极/漏极双层结构的许多变化将是显而易见的。例 如，在一些实施例中，以外延沉积的硼掺杂SiGe来实现衬里313/315，其 可以在一层或多层中，具有30到70原子％范围中或更高的锗浓度。如前解 释的，SiGe衬里的这个锗浓度可以是固定的，或者分级的，以便从基准级 别(接近衬底300的)增大到高级别(例如，超过50原子％，接近帽层318/320 的锗浓度的基准浓度，其以锗梯度继续增大到100原子％)。在一些这种实 施例中的硼浓度可以超过1E20cm-3，诸如高于5E20cm-3或者2E21cm-3，也 可以是分级的，以便从接近衬底300的基准级别增大到高级别(例如，超 过1E20cm-3或2E20cm-3或3E20cm-3等，接近帽层318/320)。在硼掺杂SiGe 衬里313/315的锗浓度固定的实施例中，分级的薄缓冲区可以用于更好地连 接衬里313/315与硼掺杂帽层318/320。注意，这个缓冲区可以是中间层， 或者集成到帽层318/320的成分中。就本公开内容而言，可以将这个缓冲区 视为帽层318/320的部分。根据一些特定实施例，硼掺杂SiGe沉积层(或 者层的集合)313/315的厚度例如可以在单层到50nm范围中，层(或层的 集合)318/320可以具有例如51到500nm范围中的厚度，尽管根据本公开 内容显然地，可替换的实施例可以具有其他衬里或帽层厚度。在一些实施 例中，注意，可以在循环沉积-蚀刻处理过程中，在间隔体下方产生空腔 312/314，这些空腔312/314也可以由外延帽层回填(例如其可以具有与硼 掺杂锗帽层318/320相同的成分)。
根据本公开内容会进一步理解，本文论述的高锗浓度(例如超过50原 子％直至纯锗)与高硼浓度(例如超过1E20cm-3)的组合可以用于实现PMOS 晶体管器件中源极与漏极区(图1中的R3)以及其相应的尖端区(图1中 的R2)中明显高得多的电导。此外，如前解释的，由于硼扩散在高锗成分 层中相对于在较低锗成分层中受到充分抑制，所以尽管沉积的压力膜 (stressor film)中的掺杂程度较高，在与具有相等的p型掺杂剂种类和掺 杂级别的较低锗成分层相比时，随后的热退火实现了较小的不利SCE降级。 由在接触面的较高锗浓度也实现了势垒高度降低，导致了图1中较低的接 触电阻R4。在一些示例性实施例中，超过80原子％直至纯锗(100原子％) 的锗浓度可以用于获得这种益处。但注意纯锗不是必需的。例如，一些实 施例可以具有超过90或95原子％的锗浓度，而非纯锗。
如进一步参考图3C所见的，相对地接近沟道区形成源极/漏极尖端 318A/320A还给沟道施加了较大的流体静应力。该应力增大了沟道内的应 变，从而增大了沟道中的迁移率并增大了驱动电流。在含硅衬底的情况下 通过增大源极/漏极尖端318A/320A的锗浓度，并且在锗衬底的情况下通过 增大锡浓度可以进一步放大该应力。这是对尖端区通常不在沟道区上引起 应变的基于扩散的工艺的改进。
一旦根据本发明的实施例填充了源极和漏极区，就可以实施多种传统 MOS处理，以完成MOS晶体管的制造，例如置换栅极氧化物的工艺、置 换金属栅极的工艺、退火和自对准多晶硅化(salicidation)工艺，它们可以 进一步修改晶体管316和/或提供必要的电连接。例如，在源极/漏极区连同 其相应的尖端的外延沉积后，进一步参考图2，方法可以继续进行从n型区 去除212任何掩模，并按要求处理这些区(如果适用的话，诸如在CMOS 工艺中)，并在晶体管上沉积214绝缘体，随后按照通常所做的那样对该绝 缘层进行平坦化。可以使用已知的适用于集成电路结构的绝缘层中的材料 来形成绝缘层，例如低-k电介质(绝缘)材料。这种绝缘材料例如包括诸 如氧化硅(SiO2)和碳掺杂氧化物(CDO)之类的氧化物、氮化硅、诸如 八氟环丁烷或聚四氟乙烯之类的有机聚合物、氟硅酸盐玻璃(FSG)、和诸 如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃之类的有机硅酸盐。在一些示例 性结构中，绝缘层可以包括小孔或其他孔隙，以进一步减小其介电常数。 图3D示出了示例性绝缘层322，已经对其进行了沉积，并随后向下平坦化 到硬掩模306。
如进一步参考图3D’所见的，本发明的一些实施例使用了置换金属栅极 工艺，该方法可以包括使用如传统所做的蚀刻工艺来去除栅极堆叠体(包 括高-k栅极电介质层302、牺牲栅极电极304和硬掩膜层306)。在替换的 实施方式中，仅去除牺牲栅极304。如果去除栅极电介质302，该方法就可 以包括在沟槽开口中沉积新的栅极电介质层。在此可以使用如前所述的任 何适合的高-k电介质材料，例如二氧化铪。也可以使用相同的沉积工艺。 栅极电介质层302的置换例如可以用于应对在干法和湿法蚀刻工艺实施过 程中会对原始栅极电介质层造成的任何损害，和/或以高-k或预期的栅极电 介质材料来代替低-k或牺牲电介质材料。该方法随后可以继续进行将金属 栅极电极层沉积到沟槽中和栅极电介质层上。传统金属沉积工艺可以用于 形成金属栅极电极层，例如CVD、ALD、PVD、无电镀覆或电镀。金属栅 极电极层例如可以包括P型功函数金属，例如钌、钯、铂、钴、镍，和导 电金属氧化物，例如氧化钌。在一些示例性结构中，可以沉积两个或多个 金属栅极电极层。例如，可以沉积功函数金属，之后是诸如铝的适合的金 属栅极电极填料金属。图3D’示出了根据一个实施例的，已经沉积到沟槽开 口中的示例性高-k电介质层324和金属栅极电极326。注意，如有需要，可 以在工艺锗的不同时间实施这种RMG工艺。
进一步参考图2，在提供了绝缘层322(及任何预期的接触部形成前 RMG工艺)后，该方法继续进行蚀刻216以形成源极/漏极接触沟槽。可以 使用任何适合的干法和/湿法蚀刻工艺。图3E示出了根据一个示例性实施例 的在完成蚀刻后的源极/漏极接触沟槽。
该方法继续进行沉积218接触电阻减小金属和退火，随后沉积220源 极/漏极接触插塞。图3F示出了接触电阻减小金属325，在一些实施例中， 其包括银、镍、铝、钛、金、金-锗、镍-铂、或镍-铝，和/或其他这种电阻 减小金属或合金。图3F进一步示出了接触插塞金属329，在一些实施例中， 其包括铝或钨，尽管使用常规沉积工艺也可以使用任何适合的导电接触部 金属或合金，诸如银、镍-铂或镍-铝或镍与铝的其他合金、或钛。例如使用 锗化工艺(通常是接触部金属的沉积及随后的退火)来实施源极/漏极接触 部的金属化。例如利用镍、铝、镍-铂或镍-铝或镍和铝的其他合金、或者进 行了或没有进行锗的预先非晶化注入的钛进行的锗化可以用于形成低电阻 锗化物。硼掺杂锗帽层318/320允许金属-锗化物形成(例如镍锗)。锗化物 允许比传统金属-硅化物系统低得多的肖特基势垒高度及改善的接触电阻。 例如，传统晶体管通常使用源极/漏极SiGe外延工艺，锗浓度在30-40原子 ％范围中。受到外延/硅化物分界面电阻的限制，这种传统系统呈现了约140 Ohm-um的Rext值，所述外延/硅化物分界面电阻较高并且将来会阻碍栅极 间距缩放调整。本发明的一些实施例允许PMOS器件中Rext相当大的改善 (例如，约2倍或更佳的改善，例如约70Ohm-um的Rext，或者更小)， 这可以更好地支持PMOS器件缩放调整。因此，具有以本文所述的双层源极/漏极结构配置的源极/漏极的晶体管与传统晶体管相比可以呈现出相对 较低的Rext值。
非平面结构
例如可以使用FinFET或纳米线结构来实现非平面架构。FinFET是围 绕半导体材料的薄带(通称为鳍)构造的晶体管。晶体管包括标准场效应 晶体管(FET)节点，包括栅极、栅极电介质、源极区和漏极区。器件的导 电沟道位于栅极电介质下方鳍的外侧上/内。具体地，电流沿鳍的两个侧壁 (垂直于衬底表面的侧面)以及鳍的顶部(平行于衬底表面的侧面)流动。 因为这种结构的导电沟道的位置基本上沿着鳍的三个不同的外部平面区， 这种FinFET设计有时称为三栅极FinFET。其他类型的FinFET结构也是可 用的，诸如所谓的双栅极FinFET，在其中导电沟道的位置主要仅沿着鳍的 两个侧壁(而不沿鳍的顶部)。
图4A到4G均示出了根据本发明的一个实施例形成的FinFET晶体管 结构的透视图。会理解，前面针对图2到3F的论述在此也同等适用。如图 所示，图4A中所示的示例性非平面结构实施有鳍结构，所述鳍结构包括具 有半导体主体或鳍410的衬底400，半导体主体或鳍410从衬底400延伸通 过浅槽绝缘(STI)层420。衬底例如可以是硅、锗或SiGe。
图4B示出了的栅极电极440，其形成在鳍410的3个表面上以形成3 个栅极(因此为三栅极器件)。在鳍410与栅极电极440之间提供栅极电介 质材料430，在栅极电极440的顶部上形成硬掩膜450。图4C示出了在沉 积绝缘材料，及随后的蚀刻后得到的结构，所述蚀刻在所有垂直表面上留 下了绝缘体材料的覆盖层，以便提供间隔体460。
图4D示出了在额外的蚀刻处理后得到的结构，所述额外的蚀刻处理用 以从鳍410的侧壁消除过多的绝缘/间隔体材料，从而仅在栅极电极440的 相反侧壁上留下间隔体460。图4E示出了在凹槽蚀刻后得到的结构，所述 凹槽蚀刻用以去除衬底400的源极/漏极区中的鳍410，从而形成凹槽470。 注意，其他实施例可以不形成凹槽(例如，源极/漏极区与STI层420平齐)。
图4F示出了在外延衬里480生长后得到的结构，该外延衬里480可以 是薄p型的且包含很大部分的硅(例如，硅或具有70原子％硅的SiGe)， 或者是纯锗(例如，单独一层锗，或者结合或包括在帽层318/320的成分中 的无法察觉的层)。图4G示出了在外延源极/漏极帽层490生长后得到的结 构，该帽层490可以是p型的，主要包括锗，但也可以包含少于20原子％ 的锡或其他适合的合金材料，如前解释的。根据本公开内容会理解，传统 的工艺和形成技术可以用于制造具有本文所述的双层源极/漏极结构的 FinFET晶体管结构。
会进一步理解，注意到所示的三栅极结构的可替换方式是双栅极架构， 其包括在鳍410顶部上的电介质层/隔离层。进一步注意到，构成图4G所 示的源极/漏极区的衬里480和帽层490的示例性形状并非旨在将所要求保 护的本发明局限于任何特定源极/漏极类型或形成工艺，根据本公开内容， 其他源极/漏极形状也将是显而易见的(例如，可以实现圆形、方形或矩形 源极/漏极区)。
图5A示出了根据本发明一个实施例形成的纳米线晶体管结构的透视 图。纳米线晶体管(有时称为全环栅FET)被配置成类似于基于鳍的晶体 管，但使用纳米线来代替鳍，栅极材料通常在各侧面围绕沟道区。取决于 具体设计，一些纳米线晶体管例如具有四个有效栅极。图5A示出了具有两 个纳米线510的纳米线沟道架构，尽管其他实施例可以具有任意数量的纳 米线。例如可以用p型硅或锗或SiGe纳米线来实现纳米线510。如图所示， 一个纳米线510形成于或提供在衬底400的凹槽中，另一个纳米线510实 际上浮在包括衬里580和帽层590的源极/漏极材料双层结构中。正如鳍结 构一样，注意到在源极/漏极区中可以用本文所述的源极/漏极材料的双层结 构来代替纳米线510(例如，相对薄的硅或锗或SiGe衬里和相对厚的高浓 度锗帽层)。可替换地，可以如图所示的那样在初始形成的纳米线510周围 提供双层结构(在此，围绕纳米线510提供衬里580，随后围绕衬里580提 供帽层590)。图5B也示出了具有多个纳米线510的纳米线结构，但在这 个示例性情况下，在纳米线形成过程期间，不从各个纳米线之间去除非活 性材料511，根据本公开内容会理解，这可以使用多种传统技术来实施。这 样，在衬底400的凹槽中提供一个纳米线510，另一个纳米线510实际上位 于材料511的顶部上。注意，纳米线510在整个沟道上是活性的，但材料 511不是。如图所示，围绕纳米线510的全部其他露出的表面提供衬里580 和帽层590的双层源极/漏极结构。
示例性系统
图6示出了实现有根据本发明的示例性实施例配置的一个或多个晶体 管结构的计算系统1000。如图所示，计算系统1000容纳母板1002。母板 1002可以包括多个组件，包括但不限于处理器1004和至少一个通信芯片 1006，其每一个都可以物理和电气耦合到母板1002，或者集成于其中。会 理解，母板1002例如可以是任何印刷电路板，不论是主板还是安装在主板 上的子板或者系统1000的唯一的板等。根据其应用，计算系统1000可以 包括一个或多个其他部件，其可以也可以不物理和电气耦合到母板1002。 这些其他部件可以包括，但不限于，易失性存储器(例如，DRAM)、非易 失性存储器(例如，ROM)、图形处理器、数字信号处理器、加密处理器、 芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码 解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、罗盘、 加速度计、陀螺仪、扬声器、照相机、和大容量存储设备(例如硬盘驱动 器、压缩盘(CD)、数字多功能盘(DVD)等等)。包括在计算系统1000 中的任何部件都可以包括本文所述的一个或多个晶体管结构(例如，具有 包括相对薄的p型硅或锗或SiGe衬里和相对厚的p型高锗含量帽层的双层 源极/漏极结构)。这些晶体管例如可以用于实现板载处理器高速缓存或存储 器阵列。在一些实施例中，多个功能可以集成到一个或多个芯片中(例如， 注意通信芯片1006可以是处理器1004的一部分，或者集成到处理器1004 中)。
通信芯片1006实现了无线通信，用于往来于计算系统1000传递数据。 术语“无线”及其衍生词可以用于描述电路、设备、系统、方法、技术、 通信信道等，其可以借助使用通过非固态介质的调制的电磁波辐射来传送 数据。该术语并非暗示相关设备不包含任何线路，尽管在一些实施例中可 以没有线路。通信芯片1006可以执行许多无线标准或协议中的任意无线标 准或协议，包括但不限于Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16 族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、 EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物，以及指 定作为3G、4G、5G及更高代的任何其他无线协议。计算系统1000可以包括 多个通信芯片1006。例如，第一通信芯片1006可以专用于较短距离无线通信， 诸如Wi-Fi和蓝牙，第二通信芯片1006可以专用于较长距离无线通信，诸如 GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
计算系统1000的处理器1004包括封装在处理器1004内的集成电路管 芯。在本发明的一些实施例中，处理器的集成电路管芯包括板载存储器电 路，它是以本文所述的一个或多个晶体管结构(例如，PMOS或CMOS) 实现的。术语“处理器”可以指代任何设备或设备的部分，所述设备或设 备的部分处理例如来自寄存器和/或存储器的电子数据，以将该电子数据转 换为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片1006还可以包括封装在通信芯片1006内的集成电路管芯。 根据一些这种示例性实施例，通信芯片的集成电路管芯包括以本文所述的 一个或多个晶体管结构实现的一个或多个电路(例如片上处理器或存储 器)。根据本公开内容会理解，注意多标准无线功能可以直接集成在处理器 1004中(例如，任何芯片1006的功能都集成到处理器1004中，而不是具 有分离的通信芯片)。此外注意，处理器1004可以是具有这种无线功能的 芯片组。简而言之，可以使用许多处理器1004和/或通信芯片1006。类似 地，任意一个芯片或芯片组都可以具有集成在其中的多个功能。
在多个实施方式中，计算系统1000可以是膝上型电脑、上网本、笔记 本电脑、智能电话、平板电脑、个人数字助理(PDA)、超便携移动PC、 移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱 乐控制单元、数字照相机、便携式音乐播放器、或数字视频录像机。在进 一步的实施方式中，系统1000可以是如本文所述的处理数据或使用低电阻晶体管器件的任何其他电子设备(例如，PMOS和CMOS电路)。
许多实施例将是显而易见的，本文所述的特征可以组合到许多结构中。 本发明的一个示例性实施例提供了一种晶体管器件。该器件包括具有沟道 区的衬底，在沟道区上方的栅极电极，和形成于衬底上或中并与沟道区相 邻的源极和漏极区。源极和漏极区中的每一个都具有总厚度，包括硅或锗 或硅锗的p型衬里和具有超过80原子％的锗浓度的p型帽层，其中，衬里 小于总厚度的50％。在一些情况下，所述器件是平面、FinFET或纳米线 PMOS晶体管之一。在一些情况下，所述器件进一步包括金属-锗化物源极 和漏极接触部。在一些情况下，衬里厚度与帽层厚度的厚度比是2:5，或者 更小(衬里是总厚度的40％或更小)。在一些情况下，衬里厚度与帽层厚度 的厚度比是1:5，或者更小(衬里是总厚度的20％或更小)。在一些情况下， 每一个衬里都具有约一个单层到10nm范围中的厚度，每一个帽层都具有 约50nm到500nm范围中的厚度。在一些情况下，至少一个衬里和/或帽层 具有浓度被分级的锗和/或p型掺杂剂中的至少一个。例如，在一些情况下， 至少一个衬里具有从与衬底相容的基准级别浓度到超过50原子％的高浓度 分级的锗浓度。在一个这种情况下，高浓度超过90原子％。在一些情况下， 至少一个衬里具有从与衬底相容的基准级别浓度到超过1E20cm-3的高浓度 分级的p型掺杂剂浓度。在一个这种情况下，一个或多个衬里的p掺杂剂是硼。在一些情况下，至少一个帽层具有超过95原子％的锗浓度。在一些 情况下，至少一个帽层具有从与对应的衬里相容的基准级别浓度到超过80 原子％的高浓度分级的锗浓度。在一些情况下，至少一个帽层具有从与对应 的衬里相容的基准级别浓度到超过1E20cm-3的高浓度分级的p型掺杂剂浓 度。在一个这种情况下，一个或多个帽层的p-掺杂剂是硼。在一些情况下， 至少一个帽层进一步包括锡。多种变化是显而易见的。例如，在一些示例 性情况下，衬底是含硅衬底。在一些这种情况下，p型衬里包括硅或硅锗。 在其他示例性情况下，衬底是锗衬底。在一些这种情况下，p型衬里是p型 锗。在一些示例性的这种情况下，每一个衬里都包括在对应的帽层的成分 中(以至于不能从清晰且单独的帽层辨别出清晰且单独的衬里层)。在一些 情况下，至少一个帽层进一步包括错配位错和/或穿透位错和/或双晶，而在 其他情况下，帽层没有错配位错和/或穿透位错和/或双晶。本发明的另一个 实施例包括一种电子设备，其包括印刷电路板，所述印刷电路板具有集成 电路，所述集成电路包括如在该段落中不同定义的一个或多个晶体管器件。 在一个这种情况下，所述集成电路包括至少一个通信芯片和/或处理器。在 一些情况下，电子设备是计算设备。
本发明的另一个实施例提供了一种集成电路。电路包括具有沟道区的 衬底(例如，硅、SiGe、或锗)，在沟道区上方的栅极电极，形成于衬底上 或中并与沟道区相邻的源极和漏极区，和金属－锗化物源极和漏极接触部。 每一个源极和漏极区都具有总厚度，包括硅或锗或硅锗的p型衬里和具有 超过80原子％的锗浓度的p型帽层，其中，衬里是总厚度的40％或更小。 在一些情况下，衬里厚度与帽层厚度的厚度比是1:5或更小。在一些情况下，至少一个帽层进一步包括锡。
本发明的另一个实施例提供了一种用于形成晶体管器件的方法。所述 方法包括提供具有沟道区的衬底，在沟道区上方提供栅极电极，和提供形 成于衬底上或中并与沟道区相邻的源极和漏极区。每一个源极和漏极区都 具有总厚度，包括硅或锗或硅锗的p型衬里和具有超过80原子％的锗浓度 的p型帽层，其中，衬里小于总厚度的50％。在一些情况下，该方法包括 提供金属-锗化物源极和漏极接触部。在一些情况下，衬里厚度与帽层厚度的厚度比是2:5，或者更小。在一些情况下，至少一个衬里和/或帽层具有浓 度被分级的锗和/或p型掺杂剂中的至少一个。在一些情况下，至少一个帽 层进一步包括锡(或其它适合的应变诱导物)。
出于图示和说明的目的提供的本发明的示例性实施例的前述说明。其 并非旨在是穷举性的或将本发明限制于公开的准确形式。根据本公开内容， 许多修改和变化是可能的。例如，本发明的一些实施例利用锗的原位硼掺 杂，而其他实施例可以使用本征锗，它在沉积以后，随后对其进行p型掺 杂剂注入和退火工艺，以提供预期的p型掺杂浓度。此外，一些实施例可 以包括如本文所述那样制造的源极和漏极区，但仍使用传统处理(例如， 注入和退火)来形成源极和漏极区的尖端。在这种实施例中，尖端可以具 有低于主源极/漏极区的锗和/或p型掺杂剂浓度，这在一些应用中是可接受 的。在其他的实施例中，仅以高锗和p型掺杂剂浓度配置源极与漏极区的 尖端，源极和漏极区的主要部分可以具有常规的，或者较低的锗/掺杂剂浓 度。其意图是本发明的范围不局限于该具体实施方式部分，而是由所附的 权利要求限定。

Claims (25)

1.一种集成电路装置，包括：
半导体主体，其包括硅和锗中的至少一种；
至少在所述半导体主体之上的栅极结构，所述栅极结构包括栅电极和在所述半导体主体和所述栅电极之间的栅极电介质；
与所述半导体主体相邻的源极结构或漏极结构，所述源极结构或漏极结构包括第一部分和第二部分，所述第一部分包括硅和锗中的至少一种，并且所述第二部分包括p型掺杂剂、锗和锡，所述第二部分具有至少80原子％的锗浓度，并具有20原子％或少于20原子％的锡浓度，其中所述第一部分比所述第二部分薄；以及
所述源极结构或漏极结构的第二部分上的接触结构。
2.根据权利要求1所述的装置，其中所述p型掺杂剂是镓。
3.根据权利要求1所述的装置，其中所述锡浓度在3原子％至8原子％的范围内。
4.根据权利要求1所述的装置，其中除了所述p型掺杂剂之外，所述第二部分由锗和锡组成。
5.根据权利要求4所述的装置，其中所述锡浓度在3原子％至8原子％的范围内。
6.根据权利要求1所述的装置，其中所述第二部分还包括硅。
7.根据权利要求6所述的装置，其中除了所述p型掺杂剂之外，所述第二部分由锗、硅和锡组成。
8.根据权利要求7所述的装置，其中所述锡浓度在3原子％至8原子％的范围内。
9.根据权利要求1所述的装置，其中所述半导体主体由锗或硅和锗组成，并且所述源极结构或漏极结构的第一部分由硅或硅和锗组成。
10.根据权利要求9所述的装置，还包括锗衬底，其中所述半导体主体是所述衬底的一部分。
11.根据权利要求1-10中任一项所述的装置，其中所述半导体主体包括鳍状物或纳米线。
12.一种集成电路装置，包括：
半导体主体，包括硅和锗中的至少一种；
在所述半导体主体的多个侧面上的栅极结构，所述栅极结构包括栅电极和在所述半导体主体和所述栅电极之间的栅极电介质；
与所述半导体主体相邻的源极结构或漏极结构，所述源极结构或漏极结构包括第一部分和第二部分，所述第一部分包括硅和锗中的至少一种，并且所述第二部分包括p型掺杂剂和锗，所述第二部分具有超过80原子％的锗浓度，其中所述第一部分比所述第二部分薄，并且其中所述第一部分在所述第二部分和所述半导体主体之间，并且其中所述第二部分包括一个或多个位错，所述一个或多个位错包括错配位错、穿透位错或由横跨双晶面的晶格取向中的变化引起的缺陷中的至少一种；以及
在所述源极结构或漏极结构的第二部分上的接触结构。
13.根据权利要求12所述的装置，其中所述第二部分还包括锡，所述锡浓度在3原子％至8原子％的范围内。
14.根据权利要求12所述的装置，其中除了所述p型掺杂剂之外，所述第二部分由锗组成。
15.根据权利要求12所述的装置，其中除了所述p型掺杂剂之外，所述第二部分由锗和硅组成。
16.根据权利要求12所述的装置，其中所述半导体主体由硅组成，并且所述源极结构或漏极结构的第一部分由硅或硅和锗组成。
17.根据权利要求12所述的装置，其中所述半导体主体由锗组成，并且所述源极结构或漏极结构的第一部分由硅或硅和锗组成。
18.根据权利要求12-17中任一项所述的装置，其中所述半导体主体包括鳍状物，并且所述栅极结构位于所述鳍状物的三个侧面上。
19.根据权利要求12-17中任一项所述的装置，其中所述一个或多个位错包括至少一个错配位错。
20.根据权利要求12-17中任一项所述的装置，其中所述一个或多个位错包括至少一个穿透位错。
21.根据权利要求12-17中任一项所述的装置，其中所述一个或多个位错包括由横跨双晶面的晶格取向中的变化引起的至少一个缺陷。
22.一种集成电路装置，包括：
半导体纳米线，其包括硅和锗中的至少一种；
在所述半导体纳米线周围的栅极结构，所述栅极结构包括栅电极和在所述半导体纳米线与所述栅电极之间的栅极电介质；
与所述半导体纳米线相邻的源极结构或漏极结构，所述源极结构或漏极结构包括第一部分和第二部分，所述第一部分包括硅和锗中的至少一种，并且所述第二部分包括p型掺杂剂和锗，所述第二部分具有超过80原子％的锗浓度，其中所述第一部分比所述第二部分薄，并且其中所述第一部分位于所述第二部分和所述半导体纳米线之间，并且其中所述第二部分包括一个或多个位错，所述一个或多个位错包括错配位错、穿透位错或由横跨双晶面的晶格取向中的变化引起的缺陷中的至少一种；以及
在所述源极结构或漏极结构的第二部分上的接触结构。
23.根据权利要求22所述的装置，其中所述半导体纳米线由硅组成，并且所述源极结构或漏极结构的第一部分由硅或硅和锗组成。
24.根据权利要求22所述的装置，其中所述半导体纳米线由锗组成，并且所述源极结构或漏极结构的第一部分由硅或硅和锗组成。
25.根据权利要求22所述的装置，其中所述半导体纳米线由硅和锗组成，并且所述源极结构或漏极结构的第一部分由硅或硅和锗组成。
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