TWI544630B - 具有高濃度的硼摻雜鍺之電晶體 - Google Patents

具有高濃度的硼摻雜鍺之電晶體 Download PDF

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Publication number
TWI544630B
TWI544630B TW100145538A TW100145538A TWI544630B TW I544630 B TWI544630 B TW I544630B TW 100145538 A TW100145538 A TW 100145538A TW 100145538 A TW100145538 A TW 100145538A TW I544630 B TWI544630 B TW I544630B
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concentration
boron
substrate
source
germanium
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TW100145538A
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TW201242022A (en
Inventor
安拿 莫希
葛蘭 葛雷斯
塔何 甘尼
拉維 皮拉瑞斯提
尼洛依 穆可吉
傑克 卡瓦萊羅斯
羅沙 寇利爾
威利 瑞奇曼第
馬克 劉
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英特爾股份有限公司
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Description

具有高濃度的硼摻雜鍺之電晶體
本發明係關於具有高濃度的硼摻雜鍺之電晶體
包含形成於半導體基底上的電晶體、二極體、電阻器、電容器、及其它被動和主動電子裝置之電路裝置的增加之性能是這些裝置在設計、製造、及操作期間典型上主要考慮的因素。舉例而言，在例如互補式金屬氧化物半導體(CMOS)中所用的金屬氧化物半導體(MOS)電晶體等半導體裝置的設計和製造或形成期間，通常希望增加N型MOS裝置(NMOS)通道區中的電子移動以及增加P型MOS裝置(PMOS)通道區中正電荷電洞的移動。藉由降低裝置電阻，能夠取得電晶體中此增加的驅動電流。
降低MOS裝置的整體電阻之一方法是摻雜MOS裝置的稱為尖端區之源極/汲極區與通道區之間的區域(或者有時稱為源極/汲極延伸)。舉例而言，摻雜劑可以佈植入源極/汲極區中以及執行後續的退火以使摻雜劑朝向通道區擴散。由於使用佈植及擴散方法，所以，控制摻雜劑及位置的能力是受限的。此外，例如MOS裝置的偏移間隔器的厚度等MOS裝置的其它部份之大小也對尖端區的位置具有強烈影響。所有這些接著影響尖端區的使摻雜劑濃度最大化及接近通道區的極近處之能力。因此，需要進步的方法或結構以克服習知的尖端區之限制。
【發明內容及實施方式】
揭示用於形成具有高濃度的硼摻雜鍺之源極和汲極區的電晶體裝置之技術。舉例而言，可以使用所述技術以延伸自行對準磊晶尖端(SET)電晶體以達成非常接近單軸應變的理論極限。在某些實施例中，藉由在源極和汲極區與它們的對應尖端區中使用選擇性的磊晶沈積所提供之原地硼摻雜鍺以達成此點。在其它實施例中，使用選擇性磊晶沈積，以在源極/汲極和各別的尖端區中形成由重度硼摻雜的鍺層覆蓋之硼摻雜矽鍺的雙層結構。在此情形中，舉例而言，鍺濃度在20原子%至100原子%的範圍中，以及，舉例而言，硼濃度在1E20cm-3至2E21cm-3的範圍中(例如，鍺濃度超過50原子%及硼濃度超過2E20cm-3)。具有階化的鍺及/或硼濃度的選加薄緩衝物作為下層基底材料或是具有硼摻雜鍺的層之材料的界面層。同樣地，在雙層配置中，具有階化的鍺及/或硼濃度的薄緩衝物作為具有硼摻雜鍺蓋的矽鍺層之界面層。在其它實施例中，仍以類似於選加緩衝物的方式，硼摻雜鍺或矽鍺層本身具有階化的鍺及/或硼濃度。在任何此情形中，由於在鍺中抑制硼擴散(濃度愈高，抑制愈大)，所以，高濃度的硼摻雜於鍺中，接著造成更低的寄生電阻且不會使尖端陡峭劣化。此外，從肖特基能障高度的下降，接觸電阻降低。舉例而言，所述技術可以具體實施於平面的或非平面的FinFET電晶體裝置中。
概述
如同已知，金屬氧化物半導體(MOS)電晶體可以包含設計成降低電晶體的整體電阻的源極和汲極尖端區並進步短通道效應(SCE)。習知上，這些尖端區是使用佈植及擴散技術佈植例如硼或碳等摻雜劑的基底之部份。在源極區與通道區之間的區域中形成源極尖端區。類似地，在汲極區與通道區之間的區域中形成汲極尖端區。導因於此習知的處理之尖端區最小地下擴散電晶體的閘極介電層。
更詳細而言，圖1A顯示形成於基底102上的習知MOS電晶體100A。藉由佈植例如硼等摻雜劑至基底中或是藉由蝕刻基底並接著磊晶地沈積矽或矽鍺材料(具有10至40原子%範圍的鍺濃度)，而典型地形成源極區110和汲極區112。在電晶體100A的通道區120上形成閘極堆疊122。進一步可見，閘極堆疊122包含閘極介電層106和閘極電極104，間隔器108形成為相鄰於閘極堆疊122。在某些舉例說明的情形中，且視技術節點而定，間隔器108在閘極介電層106的邊緣與源極和汲極區110/112中每一區的邊緣之間產生約10至20奈米(nm)的距離。在此空間中，形成源極尖端區110A與汲極尖端區112A。如同所見，佈植-擴散為基礎的尖端區110A/112A與間隔器108重疊，且以小於10nm的距離與閘極介電層106重疊或下擴散。在形成佈植-擴散為基礎的尖端區110A/112A時，例如硼或碳等摻雜劑佈植於源極 區110和汲極區112中。電晶體100A接著被退火而促使摻雜劑朝向通道區120擴散。也可以使用有角度的離子佈植技術以將摻雜劑進一步植入於閘極介電層106與源極/汲極區110/112之間的那些區域中。不幸地，例如尖端區110A/112A的形狀、摻雜劑穿透至間隔器108之下的距離、及尖端區110A/112A的濃度梯度等因素視基底材料中的摻雜劑的擴散特性而定。舉例而言，尖端區的濃度將高至接近源極/汲極區110/112及低至接近通道區120。雖然高度地希望，但是，不將摻雜劑驅動至通道區120中，幾乎不可能使摻雜劑濃度很高地接近通道區120。此外，由於摻雜劑可能再度被驅動至通道區120中，所以，源極和汲極區110/112無法移動至較接近通道區120。這限制了源極和汲極區110/112形成為多接近通道區120，因而限制閘極長度比例。
圖1B顯示根據本發明的實施例配置之包含源極和汲極磊晶尖端(於下通稱為磊晶尖端)之舉例說明的MOS裝置100B。詳而言之，MOS電晶體100B使用下切割蝕刻以允許源極區110和汲極區112延伸至間隔器108之下，在某些情形中，延伸至閘極介電層106之下。延伸至間隔器108(可能是閘極介電層106)之下的源極/汲極區110/112的部份於此分別稱為源極磊晶尖端110B和汲極磊晶尖端112B。源極和汲極磊晶尖端110B/112B取代參考圖1A所述的佈植/擴散為基礎的尖端區110A/112A。
根據本發明的實施例，舉例而言，如圖1B中所示， 藉由蝕刻基底102(包含下切割間隔器108(可能是閘極介電層106))，以形成源極/汲極區110/112和源極/汲極磊晶尖端110B/112B，然後使用選擇性磊晶沈積以提供原地硼摻雜鍺、或是由重度硼摻雜的硼摻雜鍺所覆蓋的硼摻雜矽鍺(SiGe)，以填充源極/汲極區110/112和源極/汲極磊晶尖端110B/112B。注意，又如圖1B中所示般，可以相對於基底102的表面，升高磊晶填充。
根據本發明的某些實施例，取決於例如基底成分及裝置結構的不同層之間要禁止的誤置缺陷之程度等因素，在結構的更多位置中使用階化的緩衝物。舉例而言，基底102可為矽基底、或是絕緣體(SOI)基底上的矽的矽膜、或是包含矽、矽鍺、鍺、及/或III-V化合物半導體之多層基底。因此，舉例而言，在使用具有矽或矽鍺基底102及原地硼摻雜鍺以填充源極/汲極區110/112及源極/汲極磊晶尖端110B/112B的實施例中，緩衝物設於下方基底102與上方硼摻雜鍺之間。在此實施例中，緩衝物是階化的硼摻雜(或本質的)矽鍺層，具有從與下方矽基底或矽鍺基底並容的基層濃度至高達100原子%(或接近100原子%，例如超過90原子%或95原子%或98原子%)的階化鍺成份。在一特定的此實施例中，鍺濃度範圍從40原子%或更少至超過98原子%。在此緩衝物內的硼濃度可以是固定的，例如高位準，或是階化的，例如處於或與下方基底並容的基層濃度至所需的高濃度(例如，超過1E20cm-3、或是5E20cm-3)。注意，此處所使用的並容 性並非一定是濃度位準上重疊(舉例而言，下方基底的鍺濃度為0至20原子%，以及緩衝物的鍺濃度為30至40原子%)。此外，如同此處所使用般，與濃度位準有關的「固定」一詞係要標示相對固定的濃度位準(例如，在層中的最低濃度位準是在該內的最高濃度位準的10%之內)。更廣義而言，固定濃度位準是要表示缺乏刻意階化的濃度位準。緩衝物的厚度視例如被緩衝的濃度範圍等因素而變，但是，在某些實施例中是在30至120埃(Å)的範圍中，例如50至100埃(Å)(例如，60至65埃(Å))。如同考慮本揭示時將瞭解般，此階化緩衝物有利地降低肖特基能障高度。
或者，除了在下方基底102與上方硼摻雜鍺之間設置薄緩衝物之外，硼摻雜鍺層本身可以以類似方式階化。舉例而言，根據一舉例說明的實施例，硼摻雜鍺層配置有從與下方基底(例如30原子%至70原子%)並容的基層濃度至高達100原子%的階化鍺濃度。在某些此類實施例中，舉例而言，在此硼摻雜鍺層內的硼濃度範圍從處於或與下方基底並容的基層濃度至所需的高濃度(例如，超過1E20cm-3)。
在具有矽或矽鍺基底102以及填充源極/汲極區110/112及源極/汲極磊晶尖端110B/112B的硼摻雜鍺蓋及原地硼摻雜SiGe的雙層結構之其它實施例中，緩衝物設於硼摻雜SiGe層與上方硼摻雜鍺蓋之間。在一此實施例中，硼摻雜SiGe層具有固定濃度的鍺(例如，在30至 70原子%的範圍內)，緩衝物可為薄的SiGe層(例如30至120Å，例如50至100Å)，具有從與下方硼摻雜SiGe層並容的基層濃度至高達100原子%(或接近100原子%，例如超過90原子%或95原子%或98原子%)的階化鍺濃度。在某些此情形中，在此緩衝物之內的硼濃度是固定的，舉例而言，處於高位準，或是從處於或與下方硼摻雜SiGe層並容的基層濃度至所需的高濃度(舉例而言，超過1E20cm-3、2E20cm-3、3E20cm-3、4E20cm-3、或5E20cm-3)之範圍中。
或者，除了在雙層結構的二層之間使用薄緩衝物之外，硼摻雜SiGe層本身可以以類似方式階化。舉例而言，根據一舉例說明的實施例，硼摻雜SiGe層配置有從與下方基底(例如在30原子%至70原子%的範圍中)並容的基層濃度至高達100原子%(如同先前舉例說明般，或接近100原子%)的階化鍺濃度。舉例而言，在此硼摻雜SiGe層內的硼濃度是固定的，例如處於高位準，或者是從處於或與下方基底並容的基層濃度至所需的高濃度(例如，超過1E20cm-3)之範圍內。
如此，提供用於平面及非平面的FinFET電晶體裝置的SET架構。所述裝置由例如仿閘極氧化物、薄間隔器、及各向等性下切割蝕刻(或是氨蝕刻以在單晶基底中形成有刻面的鰭凹部、或是其它適當的蝕刻以形成鰭凹部)等習知的處理部份地形成。根據某些實施例，接著使用選擇性磊晶沈積以提供原地硼摻雜鍺、或是由重度硼摻雜純鍺 覆蓋的完全應變的硼摻雜矽鍺層，以形成尖端及源極/汲極區。可以如同先前所述般使用選加的緩衝物。根據這些實施例，由於硼於沈積時是完全活性的，所以，不要求P型源極和汲極(PSD)佈植或是高溫擴散為基礎的退火。也可使用任何適當的高k更換金屬閘(RMG)處理流程，其中，高k介電質替換仿閘極氧化物。使用或不使用鍺預非晶化之例如鎳、鎳-鉑、或鈦等矽金屬化可以用以形成低電阻鍺化物。如同先前所述般，這些實施例擴充SET電晶體裝置架構以達成(接近)單軸應變的理論極限。此處所提供的技術能應用至例如利於任何技術節點(例如，90nm、65nm、45nm、32nm、22nm、14nm、及10nm電晶體、及更低的電晶體)，且所主張之發明並非要侷限於任何特定的這些節點或是裝置幾何的範圍。參閱本揭示，將清楚其它優點。
舉例而言，值得注意的是，根據本發明的實施例配置之源極和汲極磊晶尖端110B/112B能夠在與源極和汲極區110/112相同的製程中形成，這降低製程時間。此外，不同於習知的佈植/擴散為基礎的尖端區，根據本發明的實施例配置之源極/汲極磊晶尖端110B/112B的晶格參數在通道區120中包含增加電洞遷移率的應變參數，並因而降低通道中的電阻。根據本發明的某些實施例配置之SET架構的另一優點是形成通道區120之源極/汲極磊晶尖端110B和112B與基底102材料之間的界面是陡峭的。舉例而言，在界面的一側是磊晶沈積的硼摻雜鍺(B：Ge)材料 (例如，B濃度超過2E20cm-3或5E20cm-3)，且界面的另一側是構成通道區120的基底材料(例如，矽鍺，或是其它適合的基底材料)。此結構使得磊晶源極/汲極磊晶尖端110B/112B能夠將重度硼摻雜的高濃度鍺材料帶至很緊密地近接通道區120。磊晶的源極/汲極磊晶尖端110B/112B中的硼維持實質上或完全地在磊晶尖端之內且不傾向於擴散至通道區120中。
能用於形成源極/汲極磊晶尖端110B/112B的習知方法具有應被考慮的議題。特別地，參考圖1B和1C，習知的下切割蝕刻技術導致對下切割區形成子彈輪廓。在此情形中，在閘極介電層106下方些微距離處被蝕刻的基底材料比與閘極介電層106直接相鄰的被蝕刻的基底材料還多。如此，源極磊晶尖端110B/和汲極磊晶尖端112B均符合該子彈輪廓，在通道區120中產生小於最佳應變之應變。此外，習知的下切割蝕刻技術中的變異轉移成形成的源極和汲極磊晶尖端110B/112B中的變異。如圖1B和1C中所示般，與形成源極和汲極磊晶尖端110B/112B的習知方法有關的另一議題是關於間隔器厚度對下切割蝕刻的效果。參考圖1B，MOS電晶體100B顯示為具有第一厚度x1的偏移間隔器108。執行基底蝕刻，將間隔器108及部份閘極介電層106下切割以致能夠形成源極/汲極磊晶尖端110B/112B。下切割至下切割(UC至UC)距離114將源極磊晶尖端110B與汲極磊晶尖端112B分開。參考圖1C，顯示MOS電晶體100C具有厚度x2的偏移間隔器 108。此處，厚度x2遠大於圖1B中的間隔器108的厚度x1。結果，當執行基底蝕刻時，愈厚的間隔器108排除愈多的下切割蝕刻並使得源極/汲極磊晶尖端110B/112B形成為更遠離電晶體100C的通道區120。基底蝕刻因而下切割較少的MOS電晶體100C下方的表面區域。因此，對於MOS電晶體100C的UC至UC距離116遠大於對於MOS電晶體100B的UC至UC距離114。以此方式改變UC至UC距離對MOS電晶體造成大驅動電流變化。圖1D是圖形，顯示使用習知的方法所形成的裝置中間隔器厚度如何影響UC至UC距離。圖形提供線118所表示的資料，顯示隨著間隔器厚度增加，UC至UC的距離也增加，導致大驅動電流變化。典型地，對於每增加一奈米的間隔器厚度，UC至UC的距離增加約2nm。依此方式，至少在某些情形中使用習知的方法形成源極/汲極磊晶尖端會使得偏移間隔器的厚度對MOS裝置的性能有顯著的影響。如同考量本揭示後將瞭解般，對於這些議題，本發明的某些實施例提供形成自行對準及磊晶沈積的源極和汲極尖端之方法。
架構及方法論
圖2是根據本發明的實施例之具有自行對準的源極和汲極磊晶尖端之MOS電晶體的製造方法200。圖3A至3J顯示根據某些實施例執行方法200而形成之舉例說明的結構。
如同所見般，方法200始於設置半導體基底之步驟202，在半導體基底上可以形成例如PMOS電晶體等MOS裝置。舉例而言，半導體基底可以由矽塊或絕緣體上的矽之配置實施。在其它實施中，可以使用與矽或不與矽結合之替代材料以形成半導體基底，舉例而言，鍺、矽鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、或銻化鎵。更廣義而言，根據本發明的實施例，可以使用任何可以作為半導體裝置建立於其上的基部材料。
方法200繼續進行至步驟204，在半導體基底上形成閘極堆疊。如同習知方式般或是使用任何適當的客製技術，形成閘極堆疊。在本發明的某些實施例中，藉由沈積及接著圖型化閘極介電層和閘極電極層，形成閘極堆疊。舉例而言，在一舉例說明的情形中，使用例如化學汽相沈積(CVD)、原子層沈積(ALD)、旋轉沈積(SOD)、或物理汽相沈積(PVD)等習知的沈積製程，將閘極介電層地毯式地沈積至半導體基底上。也可以使用其它的沈積技術，舉例而言，以熱方式，生長閘極介電層。舉例而言，閘極介電材料可以由例如二氧化矽或高k介電材料等材料形成。舉例而言，高k閘極介電材料包含氧化鉿、鉿矽氧化物、氧化鑭、鑭鋁氧化物、氧化鋯、鋯矽氧化物、氧化鉭、氧化鈦、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、氧化釔、氧化鋁、鉛鈧鉭氧化物、及鈮酸鉛鋅。在某些特定的實施例中，高k閘極介電層的厚度在約5Å至約200Å(例如，20Å至50Å)之間。一般而言，閘極介電層 的厚度應足以將閘極電極與鄰近的源極和汲極接點隔離。在其它實施例中，對高k閘極介電層執行例如退火處理等額外的處理，以進步高k材料的品質。接著，使用例如ALD、CVD、或PVD等類似的沈積技術，將閘極電極材料沈積至閘極介電層上。在某些此類特定實施例中，閘極電極材料是多晶矽或金屬層，但是，也可以使用其它適當的閘極電極材料。在某些舉例說明的實施例中，典型上是稍後為了更換金屬閘極(RMG)製程而被移除的犧牲材料之閘極電極材料具有50Å至500Å(例如100Å)範圍內的厚度。接著執行習知的圖型化製程，以將部份閘極電極層及閘極介電層蝕刻移除，以形成如圖3A所示的閘極堆疊。
圖3A顯示基底300，閘極堆疊形成於其上。如同根據本舉例說明的實施例所見般，閘極堆疊包含閘極介電層302(其可為高k閘極介電材料)及犠牲閘極電極304。在一特定之舉例說明的情形中，閘極堆疊包含二氧化矽閘極介電層302及多晶矽閘極電極304。閘極堆疊也包含閘極硬掩罩層306，在處理期間提供例如保護閘極電極304不受後續的的離子佈植製程損傷等優點或用途。可以使用典型的硬掩罩材料以形成硬掩罩層306，例如二氧化矽、氮化矽、及/或其它習知的介電材料。
又參考圖2，在形成閘極堆疊之後，方法200繼續離子佈植製程，藉由將摻雜劑佈植至基底中之步驟206，以高度地摻雜相鄰於閘極堆疊的部份基底。舉例而言，離子佈植製程中使用的摻雜劑係根據增加所佈植之基底材料的 蝕刻率之能力來選取，選取之用於離子佈植製程的特定摻雜劑視後續蝕刻製程中使用基底材料及蝕刻劑而變。被選取以增加基底的蝕刻率之特定摻雜劑包含例如碳、磷、及砷。舉例而言，以落在5與15仟電子伏特(keV)之間的佈植能量，以1x1014至1x1016原子/cm3範圍內的劑量，使用碳。以落在1與5仟電子伏特(keV)之間的佈植能量，以1x1014至5x1015原子/cm3範圍內的劑量，使用磷。以落在2與5仟電子伏特(keV)之間的佈植能量，以1x1014至5x1015原子/cm3範圍內的劑量，使用砷。考量本揭示，將清楚其它適當的摻雜劑及劑量設計。在某些實施例中，離子佈植實質上發生於垂直方向(亦即，垂直於基底的方向)；但是，在其它實施例中，至少部份離子佈植製程以有角度的方向發生以將離子佈植至閘極堆疊之下。注意，硬掩罩可以用以防止閘極電極304材料的摻雜。
接著，方法200繼續進行至將基底退火的步驟207，以將摻雜劑進一步驅入基底及降低離子佈植製程期間基底遭受之任何傷害。在某些實施例中，佈植步驟206及後續的退火步驟207可以將離子驅動至落在例如2nm與20nm之間的基底深度。以落在例如700℃與1100℃之間的溫度，執行退火207高達60秒或更低的(例如5秒)持續時間。如同將瞭解般，退火溫度及持續時間視例如擴散速率、基底材料、所使用的摻雜劑、及所需的終端摻雜劑濃度等因素，而隨著實施例不同而變。
圖3B顯示離子佈植及擴散製程之後的基底300。如同本舉例說明的實施例中所示般，對於要形成的MOS電晶體，離子佈植製程產生相鄰於閘極介電層302之二個摻雜區308。當曝露於適當的蝕刻劑時，摻雜區308將具有高於週遭的基底材料之蝕刻率。摻雜區308中之一將作為部份源極區，包含其自行對準的磊晶尖端。其它摻雜區308將作為部份汲極區，包含其自行對準的磊晶尖端。在所示之舉例說明的實施例中，部份摻雜區308位於閘極介電層302之下。注意，摻雜區308包含其深度之尺寸會視形成的MOS電晶體的要求而變。
接著，方法200繼續進行在閘極堆疊的任一側上形成間隔器之步驟208。舉例而言，使用例如氧化矽、氮化矽、或其它適合的間隔器材料等習知材料，形成間隔器。根據形成的MOS電晶體之設計需求，大致地選取間隔器的寬度。但是，根據某些實施例，間隔器的寬度未遭受源極和汲極磊晶尖端的形成所造成的設計限制。圖3C顯示根據舉例說明的實施例之具有形成於閘極電極層304及閘極介電層302的任一側上的間隔器310之基底300。
又參考圖2，方法200繼續進行乾蝕刻基底摻雜區之步驟210，以形成穴，包含自己各別的磊晶尖端之源極/汲極區形成於所述穴中。如同圖3D最佳顯示般，被蝕刻的穴大致上相鄰於閘極堆疊，且磊晶尖端區是源極/汲極穴區的有效延伸。在某些舉例說明的實施例中，被蝕刻的穴形成至深度落在50nm與1500nm之間，比摻雜區還 深。更廣義而言，根據所需的MOS裝置性能，蝕刻深度可以依需求而設定。在某些實施例中，乾蝕刻製程可使用一蝕刻劑配方，其在離子注入的過程中補充摻雜，以增加摻雜區的蝕刻率，從而使蝕刻過程中，以更快的速度移除在摻雜區的基底材料其超過基底300的其餘部分。在某些實施例中，這包含下切割間隔器310和閘極介電層302之部份摻雜區，藉以界定電晶體的自行對準尖端架構。進步摻雜區的蝕刻率使得被蝕刻的源極和汲極尖端穴能夠下切割間隔器310和閘極介電層302，而UC至UC距離實質上不受例如間隔器厚度、乾蝕刻製程變異、及其它製程變異等因素衝擊。
根據某些實施例，乾蝕刻製程可以使用發生於電漿反應器中的氯化化學物。在某些特定的這些實施例中，蝕刻劑配方包含NF3和Cl2與作為緩衝或載送氣體之氬或氦的組合。根據某些此類實施例，活性蝕刻物的流速可以在例如每分鐘50與200標準立方公分(SCCM)之間變化，而載送氣體的流速可以在例如每分鐘150與400標準立方公分之間變化。根據某些此類實施例，可以採用功率在例如700W至1100W之間且具有小於100W的低RF偏移之高能電漿。根據某些此類實施例，反應器壓力可以在約1帕斯卡(Pa)至約2Pa。在其它特定舉例說明的實施例中，蝕刻劑化學物可以包含HBr及Cl2的組合。在某些此類實施例中，蝕刻物的流速可以在例如40SCCM至100SCCM之間變化。根據某些此類實施例，可以採用功率在例如約 600W至1000W之間且具有小於100W的低RF偏移之高能電漿，以及，反應器壓力可以在約0.3Pa至約0.8Pa之範圍中。在又另一舉例說明的實施例中，蝕刻劑化學物可以包含Ar及Cl2的組合。在某些此類實施例中，蝕刻物的流速可以在例如40SCCM至80SCCM之間變化。根據某些此類實施例，可以採用功率在例如約400W至800W之間且具有約100W至200W之間的高RF偏移之中能電漿，以及，反應器壓力可以在約1Pa至約2Pa之範圍中。每一這些舉例說明的實施例中之乾蝕刻製程時間可以高達例如每一基底60秒，但是，可以視例如所需的蝕刻深度及蝕刻劑等因素而變。如同將瞭解般，這些蝕刻製程參數可以變化。
圖3D顯示根據本發明的某些實施例之執行乾蝕刻製程之後的基底300。如同所示，形成源極區穴312和汲極區穴314。此外，如同先前所述般，藉由摻雜區的蝕刻步驟210，形成源極尖端穴312A和汲極尖端穴314A分別作為穴312和314的延伸。注意，由於蝕刻步驟210期間使用增加摻雜區的蝕刻率之摻雜劑和蝕刻物，所以，摻雜區間隔器310的厚度對源極尖端穴312A和汲極尖端穴314A的蝕刻具有最小的衝擊。
在完成乾蝕刻製程之後，又參考圖2，本舉例說明的實施例之方法繼續進行濕蝕刻步驟212，以清潔及進一步蝕刻源極區穴312和其源極磊晶尖端穴312A、以及汲極區穴314和其汲極磊晶尖端穴314A。使用習知的或客製 的濕蝕刻化學物之濕蝕刻步驟212可以用以移除例如碳、氟、氟氯碳化物、及等例氧化矽等氧化物，以提供乾淨的表面，以在其上執行後續的處理。此外，假定是單晶矽基底，濕蝕刻步驟212也可以用以移除延著<111>及<001>結晶面之基底的薄部份，以提供平滑表面，以在其上產生高品質的磊晶沈積。在某些舉例說明的情形中，被蝕刻移除的基底的薄的部份可達到例如5nm厚且也可以移除餘留的污染物。如同圖3E中最佳顯示般，濕蝕刻步驟212造成源極區穴312及其磊晶尖端區312A的邊緣、以及汲極區穴314及其磊晶尖端區314A的邊緣依循<111>和<001>結晶面。又注意，源極和汲極磊晶尖端區312A和314A未具有習知處理中發生的子彈輪廓。
在完成濕蝕刻製程之後，又參考圖2，方法200繼續進行磊晶沈積步驟214，在源極/汲極和各別的尖端穴中，磊晶沈積原地硼摻雜鍺(在某些情形中，具有插入的薄緩衝物)、或是由重度硼摻雜鍺層覆蓋的硼摻雜矽鍺。根據某些實施例，此磊晶沈積在同一製程中填充包含各自的磊晶尖端區之源極和汲極穴。CVD製程或其它適當的沈積技術可以用於沈積步驟214。舉例而言，沈積步驟214可以在CVD反應器、LPCVD反應器、或是超高真空CVD(UHVCVD)中執行。在某些舉例說明的情形中，反應器溫度可以落在例如600℃與800℃之間，以及，反應器壓力可以落在1與760托(Torr)之間。舉例而言，載送氣體可以包含例如10與50 SLM之間的適當流速之氫或氦。 在某些特定實施例中，使用例如於H2中稀釋的GeH4(例如，GeH4以1-5%稀釋)等鍺源先驅物，以執行沈積。舉例而言，使用1%濃度及流速在50與300SCCM之間的範圍之稀釋的GeH4。對於硼的原地摻雜，使用稀釋的B2H6(例如，B2H6可於H2中以1-5%稀釋)。例如，使用3%濃度及流速在10與100SCCM之間的範圍的稀釋的B2H6。在某些舉例說明的情形中，可以添加蝕刻劑以增加沈積的選擇性。舉例而言，以範圍在例如50與300SCCM之流速，添加HCl或Cl2。
根據本發明的某些舉例說明的實施例，以及，如圖3F中最佳顯示般，源極和汲極穴312/314與它們各別的尖端區312A/314A由原地硼摻雜鍺填充，藉以在基底300中形成MOS電晶體316的源極區318(以及磊晶尖端318A)以及汲極區320(以及磊晶尖端320A)。在某些此類實施例中，硼摻雜鍺具有超過5E20cm-3的硼濃度，例如2E21cm-3或更高。根據某些特定實施例，硼摻雜鍺沈積層的厚度範圍在例如50至500nm(例如120nm)內，但是，參考本揭示，將清楚知道其它的層厚度。如同先前所述般，某些此類實施例包含以薄緩衝物介於純鍺層與基底之間。舉例而言，從圖3F中所示的舉例說明的實施例中進一步可見，在沈積原地硼摻雜鍺之前，沈積源極緩衝物313及汲極緩衝物315。在某些此類實施例中，緩衝物313和315是階化的硼摻雜矽鍺層，具有從與下層基底300材料並容的基層濃度至100原子%(或如先前所述般接近100原子%)階化的 鍺成份。緩衝物313和315的厚度將視例如緩衝物變化的濃度範圍及下方基底300的構成等因素而變。在具有矽鍺基底的一舉例說明的實施例中，緩衝物厚度範圍從2nm至10nm，但是，也可以使用其它適當的厚度。在一特定的此類實施例中，舉例而言，在緩衝物313及315之內的硼濃度範圍從與下方矽鍺基底並容的基層濃度至所需的濃度(例如，超過1E20cm-3及高達2E21cm-3)，二個特定實施例是超過2E20cm-3或超過5E20cm-3。如同慮及本揭示時將瞭解般，更廣義而言，於需要時可調整硼濃度以提供所需程度的導電率。
根據本發明的其它舉例說明的實施例，及如圖3G中最佳顯示般，源極和汲極區穴312/314與它們各別的尖端區312A/314A由原地硼摻雜矽鍺填充，以在基底300中形成MOS電晶體316的源極區318(及磊晶尖端318A)以及汲極區320(及磊晶尖端320A)。硼摻雜矽鍺填充物接著由重度硼摻雜鍺層遮蓋，以提供源極蓋317及汲極蓋319。在某些此類雙層結構實施例中，以一或更多層磊晶地沈積的硼摻雜矽鍺填充物具有範圍在30至70原子%的濃度或更高的鍺濃度。如同先前所述般，SiGe填充物的鍺濃度可以是固定的或階化的，以從基層(接近基底300)至高位準(例如超過50原子%，接近純鍺蓋317/319)。在某些此類實施例中，硼濃度超過1E20cm-3，例如高於5E20cm-3或2E21cm-3，也可以階化成從接近基底300的基層濃度增加至高位準(例如超過1E20cm-3或2E20cm-3 或3E20cm-3等等，接近鍺蓋317/319)。在硼摻雜SiGe層的鍺濃度固定的情形中，如同先前所述般，使用薄的階化緩衝物以使硼摻雜SiGe層與硼摻雜Ge蓋更佳地交界。根據某些特定實施例，硼摻雜SiGe沈積層318/320(或者多個層的總體)的厚度之範圍從50至250nm(例如，60nm)以及，純鍺蓋317/319的厚度可以具有例如50至250nm(例如，50nm)範圍內的厚度，但是，如同從本揭示中可瞭解般，替代實施例可以具有其它層及蓋厚度。在某些實施例中，注意，在循環沈積蝕刻處理期間，在間隔器下方產生穴，這些穴也由磊晶蓋層回填(舉例而言，具有與硼摻雜鍺蓋317/319相同的成份)。
如同考慮本揭示將瞭解般，例如圖3F及3G中所示的實施例有關之說明所述般，高鍺濃度(例如，超過50原子%及高達純鍺)與高硼濃度(例如，超過1E20cm-3)的結合用以在PMOS SET電晶體裝置中的源極和汲極區以及它們各別的尖端區中實現顯著地更高的導電性。此外，如同先前所述般，由於硼擴散由純鍺充份地抑制，所以，僅管在沈積的壓力膜中有高濃度硼，但是，後續的熱退火仍能實現非不利的SCE劣化。因接觸表面之較高的鍺濃度，能障高度也能夠降低。在某些舉例說明的實施例中，超過95原子%及高達純鍺(100原子%)的鍺濃度也可以用以達到這些優點。
又如同圖3F及3G中所示般，與經由佈植及擴散技術所形成且因而在尖端區與通道區之間未具有清楚的邊界之 習知的源極和汲極尖端區不同，MOS電晶體316的自行對準源極和汲極磊晶尖端具有陡峭的邊界。換言之，在源極/汲極磊晶尖端與通道區之間的界面清楚且良好地界定。在界面的一側上是重度硼摻雜鍺層(圖3F的層318/320或圖3G的蓋317/319)，在界面的另一側上是構成通道區的基底300的材料。源極/汲極磊晶尖端318A/320A中的硼維持實質上或完全在磊晶尖端之內且不傾向擴散至通道區中，因而相對於習知技術，能使重度硼摻雜鍺材料非常緊密地近接通道區。舉例而言，在某些特定實施例中，源極/汲極磊晶尖端318A/320A可以將閘極介電層302下切割10nm以上。這接著使得閘極長度能夠比例下降，而不必縮短通道區。
將源極和汲極磊晶尖端形成為相當緊密近接通道區也對通道施加更大的流體靜應力。此應力增加通道內的應變，藉以增加通道中的遷移率及增加驅動電流。藉由增加源極和汲極磊晶尖端的鍺濃度，進一步放大此應力。這是擴散為基礎的製程之進步，其中，該尖端區大致上未對通道區造成應變。
一旦根據本發明的實施例以填充源極和汲極區時，執行各種習知的MOS處理以完成MOS電晶體316的製造，各種習知的MOS處理為例如進一步修改電晶體316及/或提供所需的電互連之更換閘極氧化物製程、更換金屬閘極製程、退火、及矽金屬化製程。舉例而言，在磊晶沈積源極/汲極區與它們各別的尖端之後，又參考圖2，方法 200可以繼續進行沈積步驟216，以在電晶體316上沈積層間介電質(ILD)，然後如同通常所作般，將ILD層平坦化。使用例如低k介電材料等己知可應用於積體電路結構的介電層之材料，以形成ILD層。舉例而言，此介電材料包含例如二氧化矽(SiO2)及碳摻雜氧化物(CDO)等氧化物、氮化矽、例如全氟基環丁烷或聚四氟乙烯等有機聚合物、氟矽酸鹽玻璃(FSG)、及例如倍半矽氧烷、矽氧烷等有機矽酸鹽、或有機矽酸鹽玻璃。在某些舉例說明的配置中，ILD層包含孔或其它空穴，以進一步降低其介電常數。圖3H顯示已沈積且接著被向下平坦化至硬掩罩306之舉例說明的ILD層322。
接著，在使用更換金屬閘極製程之本發明的某些實施例中，方法200繼續進行移除步驟218，如同習知上執行般，使用蝕刻製程以移除閘極堆疊(包含高k閘極介電層302、犠牲閘極電極304、及硬掩罩層306)。在替代實施中，僅有犠牲閘極304被移除。圖3I顯示根據一此實施例之當閘極堆疊被蝕刻移除時形成的溝槽開口。假使閘極介電層被移除時，方法繼續進行沈積步驟220，將新的閘極介電層沈積至溝槽開口中。此處，可以使用例如先前所述之任何適當的高k介電材料，例如氧化鉿。也可以使用相同的沈積製程。可以使用閘極介電層的更換，以克服施加乾及濕蝕刻製程期間發生於原始閘極介電層之任何損傷，以及/或以高k或其它所需的閘極介電材料更換低k或犠牲介電材料。
方法200接著繼續進行沈積步驟222，以將金屬閘極電極層沈積至溝槽中及閘極介電層上。可以使用例如CVD、ALD、PVD、無電電鍍、或電鍍等習知的金屬沈積製程，以形成金屬閘極電極層。舉例而言，金屬閘極電極層可以包含例如釕、鈀、鉑、鈷、鎳等P型功函數金屬、以及例如氧化釕等導體金屬氧化物。在某些舉例說明的情形中，可以沈積二或更多金屬閘極電極層。舉例而言，沈積功函數金屬，接著是例如鋁等適當的金屬閘極電極填充金屬。圖3J顯示根據一實施例之沈積於溝槽開口中之舉例說明的高k閘極介電層324和金屬閘極電極326。
使用金屬矽化製程(一般而言，接觸金屬的沈積及後續的退火)，以執行源極和汲極接點的金屬化。舉例而言，使用或不使用鍺預非晶化之例如鎳、鋁、鎳-鉑、或鎳-鋁或是鎳及鋁的其它合金、或鈦等矽金屬化可以用以形成低電阻鍺化物。硼摻雜鍺磊晶層允許金屬鍺化物形成(例如，鎳-鍺)。相較於習知的金屬矽化物系統，鍺化物允許顯著地降低肖特基能障高度以及進步的接點電阻(包含電阻Rext)。舉例而言，習知的電晶體典型上使用源極/汲極SiGe磊晶製程，具有在30至40原子%的鍺濃度。此習知的系統呈現約140歐姆*μm的電阻Rext的電阻值，由磊晶/矽化物界面電阻限制，此值是高的且阻礙未來的閘極間距比例化。本發明的某些實施例允許PMOS裝置中的電阻Rext的電阻值顯著進步(例如，約2x進步，或是，約70歐姆*μm的電阻Rext的電阻值)，更 佳地支援PMOS裝置比例化。因此，根據本發明的實施例，具有配置有重度硼摻雜鍺的源極/汲極的電晶體，在源極/汲極磊晶尖端與通道區之間的界面具有超過1E20cm-3的硼濃度及超過50原子%及高達或者接近純鍺(100原子%)之鍺濃度，所述電晶體呈現小於100歐姆*μm的電阻Rext的電阻值，在某些情形中，小於90歐姆*μm，在某些情形中，小於80歐姆*μm，在某些情形中，小於75歐姆*μm或更低。
據此，已揭示自行對準的源極和汲極磊晶尖端，因增加的硼摻雜鍺量(例如，硼摻雜鍺或具有鍺蓋之硼摻雜矽鍺體)，而降低MOS電晶體的整體電阻及進步通道應變。在某些此類實施例中，源極和汲極磊晶尖端未具有子彈輪廓、在通道區與源極和汲極區之間形成陡峭的邊界、及/或具有更容易受控制的摻雜濃度，造成更最佳化的源極-汲極輪廓。此外，根據某些實施例藉由選取摻雜劑與蝕刻劑配方的適當組合，蝕刻源極和汲極磊晶尖端，而實質上不受間隔器厚度影響。此自行對齊準製程因而能如同所需地用以增加性能並使製程變異最小化。
FinFTE配置
如同所知，FinFET是圍繞薄長條的半導體材料(一般稱為鰭部)建立的電晶體。電晶體包含標準的場效電晶體(FET)節點，場效電晶體(FET)節點包括閘極、閘極介電質、源極區、和汲極區。裝置的導電通道設於閘極 介電質下方的鰭部之外側上。具體而言，電流延著鰭部的二側壁(垂直於基底表面的側)以及鰭部的頂部(與基底表面平行的側)流動。由於這些配置的導電通道基本上延著鰭部的三個不同的外部、平坦區設置，所以，此FinFET設計有時稱為三閘極FinFET。其它型式的FinFET配置也可取得，例如所謂的雙閘極FinFET，其中，導電通道主要僅延著鰭部的二側壁設置(且未延著鰭部的頂部設置)。
圖4顯示根據本發明的一實施例配置之舉例說明的三閘極架構的透視圖。如同所示，三閘極裝置包含基底400，基底400具有從基底400延伸經過隔離區710、720之半導體本體或是鰭部260(以虛線表示)。閘極電極340形成於鰭部260的3表面上以形成3閘極。硬掩罩410形成於閘極電極340的頂部上。閘極間隔器460、470形成於閘極電極340的對立側壁上。源極區包括形成於凹部源極界面266上及一鰭部260側壁上的磊晶區531，以及，汲極區包括形成於凹部源極界面266上及對立的鰭部260側壁上的磊晶區531(未顯示)。蓋層541沈積於磊晶區531上。在一實施例中，隔離區710、720是由一般技術形成之淺溝槽隔離(STI)區，舉例而言，藉由蝕刻基底200以形成溝槽，然後將氧化物材料沈積至溝槽以形成STI區。隔離區710、720由例如SiO2等任何已知的絕緣材料製成。此處，可等效地應用有關於基底102的先前說明(例如，基底400可以是矽基底、或是SOI基底、或 是多層基底)。
如同慮及本揭示將瞭解般，習知的製程及形成技術可以用以製造三閘極電晶體結構。但是，根據本發明的一舉例說明的實施例，使用由重度硼摻雜鍺覆蓋的原地硼摻雜矽鍺，實施磊晶區531及蓋層541的雙層結構，而以選加的鍺及/或硼階化緩衝物介於二層之間。如同先前所述般，此緩衝物可以用以從與在凹部源極界面266中對磊晶區531沈積之硼摻雜SiGe並容的基層鍺/硼濃度變化至重度硼摻雜鍺蓋541。或者，在磊晶區531中直接地實施鍺及/或硼濃度階化，而不是在插入的階化緩衝配置中實施鍺及/或硼濃度階化。如同將進一步瞭解般，注意，三閘極配置的替代是雙閘極架構，其包含鰭部260的頂部上的介電質/隔離層。
圖5是圖形，顯示使用根據本發明的實施例配置之自行對準源極和汲極磊晶尖端而取得的進步。線500代表對使用此處提供的技術所建立的MOS裝置收集的資料。如同所示，相較於使用先前製程形成的裝置，UC至UC距離更佳不受間隔器厚度影響，先前製程形成的裝置的資料再度以線118表示。圖6A及6B又顯示藉由使用根據本發明的一舉例說明的實施例配置之自行對準的源極和汲極磊晶尖端而產生之進步。具體而言，圖6A顯示肖特基能障NiGe二極體測量(漏電流相對於電壓)，確認鎳-鍺功函數是很p型的(在Ge共價帶上方約85mV)。圖6B繪出模擬資料，其顯示相較於習知的SiGe源極/汲極PMOS 裝置，根據本發明的某些舉例說明的實施例，此鍺化物材料及肖特基能障高度進步能夠造成多於2x電阻Rext的電阻值的進步。如同所知，肖特基能障高度是跨越半導體金屬接面之導電的整流能障。肖特基能障高度的量值反映跨越半導體金屬界面之金屬費米能階與半導體的主要載子能帶邊緣之能量位置的不匹配。對於p型半導體金屬界面，肖特基能障高度是金屬費米能階與半導體的共價帶最大值之間的差。
因此，如同考慮本揭示時將瞭解般，此處所提供之本發明的各式各樣的實施例可以用以克服多個電晶體比例議題，例如以間距及電源(Vcc)比例化提供更高的通道遷移率、提供降低的源極/汲極和接觸電阻、提供進步的通道陡峭度、在金屬矽化物與源極/汲極之間提供降低的能障高度以使整體寄生電阻降低，特別是在平面及非平面架構中。慮及本揭示，將清楚眾多實施例。
本發明的一舉例說明的實施例提供電晶體裝置。裝置包含具有通道區的基底。裝置又包含在通道區上方的閘極電極，其中，閘極介電層設於閘極電極與通道區之間，以及，間隔器設於閘極電極的側邊上。裝置又包含形成於基底中的源極和汲極區以及相鄰於通道區，源極和汲極區均包含尖端區，延伸至閘極介電層及/或對應的間隔器之下，其中，源極和汲極區包括具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度之硼摻雜鍺層。在一此情形中，裝置是平面的或FinFET PMOS電晶體中之一。在另 一此情形中，裝置包含金屬鍺化物源極和汲極接點。在另一此情形中，裝置在源極和汲極區上包含層間介電質。在另一此情形中，裝置在基底與硼摻雜鍺層之間包含緩衝物。在一此特定情形中，緩衝物具有從與基底並容的基層濃度至超過95原子%的高濃度之階化鍺濃度。在另一此特定情形中，緩衝物具有從與基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。在另一特定實施例中，硼摻雜鍺層具有包括硼摻雜矽鍺部份及位於其上的硼摻雜鍺蓋的雙層構造。在一此特定情形中，硼摻雜矽鍺部份具有從與基底並容的基層濃度至超過50原子%的高濃度之階化鍺濃度，以及，硼摻雜鍺蓋具有超過95原子%的鍺濃度。在另一此特定情形中，硼摻雜矽鍺部份具有從與基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。在另一此特定情形中，硼摻雜矽鍺部份具有固定的鍺濃度，以及，裝置又在硼摻雜矽鍺部份與硼摻雜鍺蓋之間包括緩衝物，緩衝物具有從與硼摻雜矽鍺部份並容的基層濃度至超過50原子%的高濃度之階化鍺濃度、以及從與硼摻雜矽鍺部份並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。在另一特定情形中，電晶體具有小於100歐姆*μm的電阻Rext的電阻值(例如，電阻Rext的電阻值=70歐姆*μm，+/-10%)。如同將瞭解般，根據例如所需的導電率等因素而將硼濃度設定得更高，以及，在某些舉例說明的此情形中是超過2E20cm-3或3E20cm-3或4E20cm-3或5E20cm-3或2E21cm-3。
本發明的另一實施例提供電晶體裝置。在此舉例說明的情形中，裝置包含具有通道區以及在通道區上方的閘極電極，其中，閘極介電層設於閘極電極與通道區之間，且間隔器設於閘極電極的側上。裝置又包含形成於基底中的源極和汲極區以及相鄰於通道區，源極和汲極區中的每一區包含延伸在閘極介電層以及/或對應的間隔器之下的尖端區，其中，源極和汲極區包含具有超過50原子%的鍺濃度及超過2E20cm-3的硼濃度之硼摻雜鍺層。裝置又包含金屬鍺化物源極和汲極接點。在某些此情形中，裝置又在基底與硼摻雜鍺層之間包含緩衝物，其中，緩衝物具有從與基底並容的基層濃度至超過95原子%的高濃度之階化鍺濃度、以及與基底並容的基層濃度至超過2E20cm-3的高濃度之階化硼濃度。在另一特定實施例中，硼摻雜鍺層具有包括硼摻雜矽鍺部份及位於其上的硼摻雜鍺蓋的雙層構造。在某些此特定情形中，硼摻雜矽鍺部份具有從與基底並容的基層濃度至超過50原子%的高濃度之階化鍺濃度，以及，硼摻雜鍺蓋具有超過95原子%的鍺濃度。在某些此特定實施例中，硼摻雜矽鍺部份具有從與基底並容的基層濃度至超過2E20cm-3的高濃度之階化硼濃度。在其它特定情形中，硼摻雜矽鍺部份具有固定的鍺濃度，以及，裝置又在硼摻雜矽鍺部份與硼摻雜鍺蓋之間包括薄緩衝物，緩衝物具有從與硼摻雜矽鍺部份並容的基層濃度至超過50原子%的高濃度之階化鍺濃度、以及從與硼摻雜矽鍺部份並容的基層濃度至超過2E20cm-3的高濃度之階化硼濃 度，緩衝物具有小於100埃的厚度。
本發明的另一實施例提供電晶體裝置形成方法。方法包含設置具有通道區的基底、以及在通道區上方設置閘極電極，其中，閘極介電層設在閘極電極與通道區之間以及間隔器設在閘極電極的側上。方法繼續在基底中形成與通道區相鄰的源極和汲極區，源極和汲極區中的每一區包含延伸在閘極介電層以及/或對應的間隔器之下的尖端區，其中，源極和汲極區包含具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度之硼摻雜鍺層。在某些此實施例中，裝置又在基底與硼摻雜鍺層之間設置緩衝物，其中，緩衝物具有從與基底並容的基層濃度至超過95原子%的高濃度之階化鍺濃度、以及從與基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。在其它實施例中，硼摻雜鍺層具有包括硼摻雜矽鍺部份及位於其上的硼摻雜鍺蓋的雙層構造。在一此情形中，硼摻雜矽鍺部份具有從與基底並容的基層濃度至超過50原子%的高濃度之階化鍺濃度，以及，硼摻雜鍺蓋具有超過95原子%的鍺濃度。在另一此情形中，硼摻雜矽鍺部份具有固定的鍺濃度，以及，方法又包含在硼摻雜矽鍺部份與硼摻雜鍺蓋之間設置緩衝物，緩衝物具有從與硼摻雜矽鍺部份並容的基層濃度至超過50原子%的高濃度之階化鍺濃度、以及從與硼摻雜矽鍺部份並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。在某些此情形中，硼摻雜矽鍺部份具有從與基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
為了顯示及說明，呈現上述本發明的舉例說明之實施例的說明。並非是耗竭性的或是侷限本發明於所揭示的精準形式。慮及本揭示，很多修改及變化是可能的。舉例而言，雖然本發明的某些實施例利用原地硼摻雜鍺，但是，其它實施例可以使用本質鍺，本質鍺在其沈積之後接著接受硼佈植以及退火製程，而提供所需的硼摻雜濃度。此外，某些實施例包含如同此處所述般製造的源極和汲極區(例如，具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度)，但是，仍可使用習知的處理(例如，佈植及退火)以形成源極和汲極區的尖端。在這些實施例中，尖端可以比主源極/汲極區具有更低的鍺及/或硼濃度，在某些應用中，這是可以接受的。在又其它實施例中，僅有源極和汲極區的尖端可以配置有高鍺及硼濃度，且源極和汲極區的主部份可以具有習知的或其它的更低鍺/硼濃度。本發明的範圍不受此詳細說明限定，而是由後附的申請專利範圍界定。
100A‧‧‧電晶體
100B‧‧‧電晶體
100C‧‧‧電晶體
102‧‧‧基底
104‧‧‧閘極電極
106‧‧‧閘極介電層
108‧‧‧間隔器
110‧‧‧源極區
110A‧‧‧尖端區
110B‧‧‧磊晶尖端
112‧‧‧汲極區
112A‧‧‧汲極尖端區
112B‧‧‧磊晶尖端
114‧‧‧下切割至下切割距離
116‧‧‧下切割至下切割距離
120‧‧‧通道區
122‧‧‧閘極堆疊
260‧‧‧鰭部
266‧‧‧凹部源極界面
300‧‧‧基底
302‧‧‧閘極介電層
304‧‧‧閘極電極
306‧‧‧硬掩罩層
308‧‧‧摻雜區
310‧‧‧間隔器
312‧‧‧源極區穴
312A‧‧‧尖端穴
313‧‧‧源極緩衝物
314‧‧‧汲極尖端穴
314A‧‧‧尖端穴
315‧‧‧汲極緩衝物
316‧‧‧電晶體
317‧‧‧蓋
318‧‧‧源極區
318A‧‧‧磊晶尖端
319‧‧‧蓋
320‧‧‧汲極區
320A‧‧‧磊晶尖端
322‧‧‧層間介電層
324‧‧‧高k閘極介電層
326‧‧‧金屬閘極電極
340‧‧‧閘極電極
400‧‧‧基底
410‧‧‧硬掩罩
460‧‧‧閘極間隔器
470‧‧‧閘極間隔器
531‧‧‧磊晶區
541‧‧‧蓋層
710‧‧‧隔離區
720‧‧‧隔離區
圖1A顯示使用佈植及擴散形成的包含源極和汲極尖端區之習知的MOS裝置。
圖1B顯示根據本發明的實施例配置之包含源極和汲極磊晶尖端之MOS裝置。
圖1C顯示間隔器厚度如何影響MOS裝置的磊晶尖端的蝕刻。
圖1D是圖形，顯示UC至UC距離與間隔器厚度的相依性。
圖2是根據本發明的實施例之形成源極和汲極磊晶尖端的方法。
圖3A至3J顯示根據本發明的多個實施例之當執行圖2的方法時形成的結構。
圖4顯示根據本發明的一實施例配置之FinFET電晶體架構的透視圖。
圖5是圖形，顯示根據本發明的實施例形成之MOS裝置的UC至UC距離如何較不視間隔器厚度而定。
圖6A顯示根據本發明的某些實施例之肖特基能障鍺化鎳(NiGe)二極體測量，確認NiGe功函數約為共價帶邊緣的85mV。
圖6B係模擬資料繪圖，顯示根據本發明的某些實施例之此鍺化物材料比習知的矽鍺源極/汲極PMOS裝置提供更顯著的電阻Rext進步。
100B‧‧‧電晶體
102‧‧‧基底
104‧‧‧閘極電極
106‧‧‧閘極介電層
108‧‧‧間隔器
110‧‧‧源極區
110B‧‧‧磊晶尖端
112‧‧‧汲極區
112B‧‧‧磊晶尖端
114‧‧‧下切割至下切割距離
120‧‧‧通道區

Claims (18)

  1. 一種電晶體裝置，包括：基底，具有通道區；閘極電極，在該通道區上方，其中，閘極介電層設在該閘極電極與該通道區之間，以及，間隔器設於該閘極電極側上；源極和汲極區，形成於該基底中且相鄰於該通道區，該源極和汲極區中的每一區包含延伸在該閘極介電層及/或該間隔器中之對應的一間隔器之下的尖端區，其中，該源極和汲極區包括具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度之硼摻雜鍺層；以及在該基底與該硼摻雜鍺層之間的緩衝物，其中，該緩衝物具有從與該基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
  2. 如申請專利範圍第1項之裝置，其中，該裝置是平面電晶體或FinFET PMOS電晶體之一。
  3. 如申請專利範圍第1項之裝置，更包括金屬鍺化物源極和汲極接點。
  4. 如申請專利範圍第1項之裝置，更包括在該源極和汲極區上的層間介電質。
  5. 如申請專利範圍第1項之裝置，其中，該緩衝物具有從與該基底並容的基層濃度至超過95原子%的高濃度之階化鍺濃度。
  6. 如申請專利範圍第5項之裝置，其中，該高濃度反 映純鍺。
  7. 一種電晶體裝置，包括：基底，具有通道區；閘極電極，在該通道區上方，其中，閘極介電層設在該閘極電極與該通道區之間，以及，間隔器設於該閘極電極側上；以及源極和汲極區，形成於該基底中且相鄰於該通道區，該源極和汲極區中的每一區包含延伸在該閘極介電層及/或該間隔器中之對應的一間隔器之下的尖端區，其中，該源極和汲極區包括具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度之硼摻雜鍺層，其中，該硼摻雜鍺層具有包括硼摻雜矽鍺部份及硼摻雜鍺蓋之雙層結構，該硼摻雜鍺蓋設於該硼摻雜矽鍺部份之上，並且其中，該硼摻雜矽鍺部份具有從與該基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
  8. 如申請專利範圍第7項之裝置，其中，該硼摻雜矽鍺部份具有從與該基底並容的基層濃度至超過50原子%的高濃度之階化鍺濃度，以及，該硼摻雜鍺蓋具有超過95原子%的鍺濃度。
  9. 如申請專利範圍第7項之裝置，其中，該硼摻雜矽鍺部份具有固定的鍺濃度，以及，該裝置更包含在該硼摻雜矽鍺部份與該硼摻雜鍺蓋之間的緩衝物，該緩衝物具有從與該硼摻雜矽鍺部份並容的基層濃度至超過50原子%的 高濃度之階化鍺濃度、以及從與該硼摻雜矽鍺部份並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
  10. 如申請專利範圍第7項之裝置，其中，該電晶體具有小於100歐姆*μm的電阻Rext的電阻值。
  11. 一種電晶體裝置，包括：基底，具有通道區；閘極電極，在該通道區上方，其中，閘極介電層設在該閘極電極與該通道區之間，以及，間隔器設於該閘極電極側上；源極和汲極區，形成於該基底中且相鄰於該通道區，該源極和汲極區中的每一區包含延伸在該閘極介電層及/或該間隔器中之對應的一間隔器之下的尖端區，其中，該源極和汲極區包括具有超過50原子%的鍺濃度及超過2E20cm-3的硼濃度之硼摻雜鍺層；金屬鍺化物源極和汲極接點；以及在該基底與該硼摻雜鍺層之間的緩衝物，其中，該緩衝物具有從與該基底並容的基層濃度至超過95原子%的高濃度之階化鍺濃度、以及從與該基底並容的基層濃度至超過2E20cm-3的高濃度之階化硼濃度。
  12. 一種電晶體裝置，包括：基底，具有通道區；閘極電極，在該通道區上方，其中，閘極介電層設在該閘極電極與該通道區之間，以及，間隔器設於該閘極電極側上； 源極和汲極區，形成於該基底中且相鄰於該通道區，該源極和汲極區中的每一區包含延伸在該閘極介電層及/或該間隔器中之對應的一間隔器之下的尖端區，其中，該源極和汲極區包括具有超過50原子%的鍺濃度及超過2E20cm-3的硼濃度之硼摻雜鍺層；金屬鍺化物源極和汲極接點，其中，該硼摻雜鍺層具有包括硼摻雜矽鍺部份及硼摻雜鍺蓋之雙層結構，該硼摻雜鍺蓋設於該硼摻雜矽鍺部份之上，並且其中，該硼摻雜矽鍺部份具有從與該基底並容的基層濃度至超過2E20cm-3的高濃度之階化硼濃度。
  13. 如申請專利範圍第12項之裝置，其中，該硼摻雜矽鍺部份具有從與該基底並容的基層濃度至超過50原子%的高濃度之階化鍺濃度，以及，該硼摻雜鍺蓋具有超過95原子%的鍺濃度。
  14. 如申請專利範圍第12項之裝置，其中，該硼摻雜矽鍺部份具有固定的鍺濃度，以及，該裝置又包含在該硼摻雜矽鍺部份與該硼摻雜鍺蓋之間的薄的緩衝物，該緩衝物具有從與該硼摻雜矽鍺部份並容的基層濃度至超過50原子%的高濃度之階化鍺濃度、以及從與該硼摻雜矽鍺部份並容的基層濃度至超過2E20cm-3的高濃度之階化硼濃度，該緩衝物具有小於100埃的厚度。
  15. 一種電晶體裝置形成方法，包括：設置具有通道區的基底； 在通道區上方設置閘極電極，其中，閘極介電層設在該閘極電極與該通道區之間，以及，複數間隔器設在閘極電極的側上；在該基底中形成與該通道區相鄰的源極和汲極區，該源極和汲極區中的每一區包含延伸在該閘極介電層以及/或該複數間隔器中之對應的一間隔器之下的尖端區，其中，該源極和汲極區包含具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度之硼摻雜鍺層；以及在該基底與該硼摻雜鍺層之間設置緩衝物，其中，該緩衝物具有從與基底並容的基層濃度至超過95原子%的高濃度之階化鍺濃度、以及從與基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
  16. 一種電晶體裝置形成方法，包括：設置具有通道區的基底；在通道區上方設置閘極電極，其中，閘極介電層設在該閘極電極與該通道區之間，以及，複數間隔器設在閘極電極的側上；在該基底中形成與該通道區相鄰的源極和汲極區，該源極和汲極區中的每一區包含延伸在該閘極介電層以及/或該複數間隔器中之對應的一間隔器之下的尖端區，其中，該源極和汲極區包含具有超過50原子%的鍺濃度及超過1E20cm-3的硼濃度之硼摻雜鍺層，其中，該硼摻雜鍺層具有包括硼摻雜矽鍺部份及硼摻雜鍺蓋之雙層結構，該硼摻雜鍺蓋設於該硼摻雜矽鍺部份 之上，並且其中，該硼摻雜矽鍺部份具有從與該基底並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
  17. 如申請專利範圍第16項之方法，其中，該硼摻雜矽鍺部份具有從與該基底並容的基層濃度至超過50原子%的高濃度之階化鍺濃度，以及，該硼摻雜鍺蓋具有超過95原子%的鍺濃度。
  18. 如申請專利範圍第16項之方法，其中，該硼摻雜矽鍺部份具有固定的鍺濃度，以及，該方法又包括在該硼摻雜矽鍺部份與該硼摻雜鍺蓋之間設置緩衝物，該緩衝物具有從與該硼摻雜矽鍺部份並容的基層濃度至超過50原子%的高濃度之階化鍺濃度、以及從與該硼摻雜矽鍺部份並容的基層濃度至超過1E20cm-3的高濃度之階化硼濃度。
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