JP7282485B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP7282485B2 JP7282485B2 JP2018093120A JP2018093120A JP7282485B2 JP 7282485 B2 JP7282485 B2 JP 7282485B2 JP 2018093120 A JP2018093120 A JP 2018093120A JP 2018093120 A JP2018093120 A JP 2018093120A JP 7282485 B2 JP7282485 B2 JP 7282485B2
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910052796 boron Inorganic materials 0.000 claims description 60
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 59
- 229910052799 carbon Inorganic materials 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 41
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 284
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 24
- 239000010703 silicon Substances 0.000 description 24
- 230000004048 modification Effects 0.000 description 22
- 238000012986 modification Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000003860 storage Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- -1 carbon ions Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
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Description
図1は、第1実施形態に係る半導体装置におけるメモリセルアレイの構成の一例を示す図である。なお、図1においては、図を見易くするために、メモリホール113内に形成された絶縁膜以外の絶縁部分については図示を省略している。また、以下の実施形態では半導体としてシリコンを例示するが、シリコン以外の半導体を用いてもよい。
図13は、第2エピタキシャル層60のボロン濃度とコンタクト抵抗との関係を示すグラフである。横軸はボロン濃度を示し、縦軸はコンタクト抵抗を示す。ただし、コンタクト抵抗は、任意単位で示されている。このグラフによれば、ボロン濃度は、1×1021cm-3以上であることが好ましいことが分かる。ボロン濃度が1×1021cm-3未満であると、メモリセルアレイMCAの形成時における熱負荷により、ボロン濃度がさらに低下するので、第2エピタキシャル層60とコンタクトプラグ70との間のショットキー障壁が十分に下がらず、コンタクト抵抗が高くなってしまう。
図16は、第2実施形態による半導体装置のコンタクト構造の一例を示す断面図である。第2エピタキシャル層60は、第1エピタキシャル層50上にシリコンをエピタキシャル成長させることによって形成される。このとき、第2エピタキシャル層60の上面は、半導体基板10の表面を(001)面としたときに、(001)面および(11n)面の両方を含む。即ち、図16に示すように、第2エピタキシャル層60の上面は、半導体基板10の表面に略平行な面と、半導体基板10の表面に対して傾斜するファセット面とを有する。(11n)面は、(001)面の周囲に設けられており、(001)面と第2エピタキシャル層60の側面との間に設けられている。(11n)面は、第1実施形態で説明した傾斜角を有すればよい。第2実施形態のその他の構成は第1実施形態の対応する構成と同様でよい。また、エピタキシャル層50、60の不純物濃度は、それぞれ第1実施形態におけるそれらの不純物濃度と同じでよい。
図17は、第2実施形態の変形例1による半導体装置のコンタクト構造の一例を示す断面図である。変形例1では、第1エピタキシャル層50は、ドレイン層20またはソース層21上にシリコンをエピタキシャル成長させることによって形成される。このとき、第1エピタキシャル層50の上面は、半導体基板10の表面を(001)面としたときに、(001)面に対して傾斜面を含む。傾斜面は例えば(113)面である。即ち、図17に示すように、第1エピタキシャル層50の上面は、半導体基板10の表面に対して傾斜するファセット面とを有する。変形例1の他の構成は、第2実施形態の構成と同様でよい。このような変形例1であっても、第2実施形態と同様の効果を得ることができる。尚、変形例1は、第1実施形態と組み合わせてもよい。
図18は、第2実施形態の変形例2による半導体装置のコンタクト構造の一例を示す断面図である。変形例2では、ドレイン層20またはソース層21の上部が窪んでおり、第1エピタキシャル層50が、ドレイン層20またはソース層21の窪みからエピタキシャル成長によって形成されている。変形例2の他の構成は、第2実施形態の構成と同様でよい。このような変形例2であっても、第2実施形態と同様の効果を得ることができる。尚、変形例2は、第1実施形態と組み合わせてもよい。
図19は、第2実施形態の変形例3による半導体装置のコンタクト構造の一例を示す断面図である。変形例3では、ドレイン層20またはソース層21の上部が窪んでおり、第1エピタキシャル層50が、ドレイン層20またはソース層21の窪みからエピタキシャル成長によって形成されている。しかし、第1エピタキシャル層50は、ドレイン層20またはソース層21の他の上面よりも低い位置までしか設けられておらず、窪み内に形成されている。変形例3の他の構成は、第2実施形態の構成と同様でよい。このような変形例3であっても、第2実施形態と同様の効果を得ることができる。尚、変形例3は、第1実施形態と組み合わせてもよい。
Claims (9)
- 基板、
前記基板の表面領域に設けられ不純物を含むソース層およびドレイン層と、前記ソース層と前記ドレイン層との間の前記基板上に設けられたゲート絶縁膜と、前記ゲート絶縁膜上に設けられたゲート電極と、濃度1×1021cm-3以上の不純物を均一に含み、かつ、濃度1×1020cm-3以上5×1020cm-3以下のカーボンを含む膜厚10nm以上150nm未満の第2エピタキシャル層と、前記第2エピタキシャル層上に接触するコンタクトプラグとを備えたトランジスタ、および、
前記トランジスタの上方に設けられたメモリセルアレイ、を備えた半導体装置。 - 前記トランジスタは、P型MOSFET(Metal Oxide Semiconductor Field Effect Transistor)であり、
前記不純物は、ボロンである、請求項1に記載の半導体装置。 - 前記ソース層または前記ドレイン層上に設けられた第1エピタキシャル層をさらに含み、
前記第1エピタキシャル層は、前記第2エピタキシャル層よりも不純物濃度が低いアンドープトエピタキシャル層である、請求項1または請求項2に記載の半導体装置。 - 前記コンタクトプラグに接触する前記第2エピタキシャル層の上面は、前記基板の表面を(001)面としたときに、(11n)面(nは正整数)となっている、請求項1から請求項3のいずれか一項に記載の半導体装置。
- 前記トランジスタは、前記メモリセルアレイを制御する制御回路の一部である、請求項1に記載の半導体装置。
- 前記第2エピタキシャル層と前記コンタクトプラグとの間に設けられ、Ti、Si、B、Cを含むシリサイド層をさらに備えた請求項1に記載の半導体装置。
- 前記第1エピタキシャル層は、前記基板の表面よりも低い位置から設けられている、請求項3に記載の半導体装置。
- 基板上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記基板の表面領域に不純物を導入してソース層およびドレイン層を形成し、
前記ソース層または前記ドレイン層上に前記基板の表面よりも高い位置まで半導体結晶をエピタキシャル成長させて第1エピタキシャル層を形成し、
前記第1エピタキシャル層上に半導体結晶をエピタキシャル成長させて、前記不純物およびカーボンの両方を同時にドープしながらSiを成膜し、濃度1×1021cm-3以上の不純物を均一に含み、かつ、濃度1×1020cm-3以上5×1020cm-3以下のカーボンを含む膜厚10nm以上150nm未満の第2エピタキシャル層を、形成し、
前記第2エピタキシャル層上に接触するコンタクトプラグを形成し、
前記ゲート電極の上方にメモリセルアレイを形成することを具備した半導体装置の製造方法。 - 前記第2エピタキシャル層は、前記不純物およびカーボンの両方をドープしながら半導体結晶をエピタキシャル成長させることによって形成される、請求項8に記載の半導体装置の製造方法。
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