CN106684148B - 具有高浓度硼掺杂锗的晶体管 - Google Patents

具有高浓度硼掺杂锗的晶体管 Download PDF

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CN106684148B
CN106684148B CN201610552470.8A CN201610552470A CN106684148B CN 106684148 B CN106684148 B CN 106684148B CN 201610552470 A CN201610552470 A CN 201610552470A CN 106684148 B CN106684148 B CN 106684148B
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germanium
concentration
source
boron
drain region
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CN106684148A (zh
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A·S·默西
G·A·格拉斯
T·加尼
R·皮拉里塞泰
N·慕克吉
J·T·卡瓦列罗斯
R·科特利尔
W·拉赫马迪
M·Y·刘
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Intel Corp
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

公开了用于形成具有高浓度硼掺杂锗的源极和漏极区的晶体管器件的技术。在一些实施例中，在源极和漏极区及其对应的尖端区中使用选择性外延沉积提供原位硼掺杂锗，或者可替换地，覆盖有重硼掺杂锗层的硼掺杂硅锗。在一些此类情况下，锗浓度例如可以超过50原子％，并高达100原子％，硼浓度例如可以超过1E20cm‑3。提供分级的锗和/或硼浓度的缓冲部可以用于更好地连接不同的层。在不使尖端陡度降级的情况下，在外延‑金属分界面的掺杂在锗中的硼的浓度有效地降低了寄生电阻。这些技术例如可以体现在平面或非平面晶体管器件中。

Description

具有高浓度硼掺杂锗的晶体管
本申请为分案申请，其原申请是2013年6月21日进入中国国家阶段、国际申请日为2011年12月7日的国际专利申请PCT/US2011/063813，该原申请的中国国家申请号是201180062124.7，发明名称为“具有高浓度硼掺杂锗的晶体管”。
背景技术
包括形成于半导体衬底上的晶体管、二极管、电阻器、电容器及其他无源和有源电子器件的电路器件的提高的性能，通常是在这些器件的设计、制造和操作过程中考虑的主要因素。例如，在金属氧化物半导体(MOS)晶体管半导体器件(例如在互补金属氧化物半导体(CMOS)中所使用的那些)的设计和制造或形成的过程中，常常希望增大N型MOS器件(NMOS)沟道区中电子的移动，并增大P型MOS器件(PMOS)沟道区中带正电荷空穴的移动。通过减小器件电阻可以在晶体管中实现这种增大的驱动电流。
减小MOS器件的整体电阻的一种方法是对源极/漏极区与沟道区之间的区域进行掺杂，该区域称为MOS器件的尖端区(tip region)(或者有时称为源极/漏极延伸部)。例如，可以在源极/漏极区中注入掺杂剂，并可以实施随后的退火，以向沟道区扩散掺杂剂。因为使用了注入和扩散方法，所有限制了控制掺杂剂浓度和位置的能力。此外，诸如其偏移间隔体的厚度等的MOS器件的其他部分的尺寸也可能对尖端区的位置有很大影响。所有这些又影响尖端区使掺杂剂浓度最大化并接近沟道区的能力。相应的，需要改进的方法或结构来克服传统尖端区的局限。
附图说明
图1A示出了传统的MOS器件，其包括使用注入和扩散形成的源极和漏极尖端区。
图1B示出了根据本发明实施例配置的MOS器件，其包括源极和漏极外延尖端。
图1C示出了间隔体厚度可以如何影响MOS器件的外延尖端的蚀刻。
图1D是示出UC到UC距离与间隔体厚度的相关性的曲线图。
图2是根据本发明实施例的形成源极和漏极外延尖端的方法。
图3A到3J示出了根据本发明多个实施例的在执行图2的方法时形成的结构。
图4示出了根据本发明一个实施例配置的FinFET晶体管架构的透视图。
图5是示出根据本发明实施例形成的MOS器件的UC到UC距离如何与间隔体厚度不太相关的曲线图。
图6A示出了根据本发明一些实施例的肖特基势垒锗化镍(nickel germanide)(NiGe)二极管的测量值，证实了NiGe功函数的价带边缘约为85mV。
图6B描绘了根据本发明一些实施例的仿真数据，其显示了这种锗化物材料提供了对传统硅锗源极/漏极PMOS器件的相当大的Rext改善。
具体实施方式
公开了用于形成具有高浓度硼掺杂锗的源极和漏极区的晶体管器件的技术。例如，可以使用这些技术来延伸自对准外延尖端(SET)晶体管，以达到极为接近单轴向应变的理论极限。在一些实施例中，这通过使用原位硼掺杂锗来实现，所述原位硼掺杂锗是由在源极和漏极区以及其对应的尖端区中的选择性外延沉积来提供的。在其他实施例中，选择性外延沉积用于形成在源极/漏极及相应的尖端区中覆盖有重硼掺杂锗层的硼掺杂硅锗的双层结构。在这种情况下，锗浓度例如可以在20原子％到100原子％范围内，硼浓度例如可以在1E20cm-3到2E21cm-3范围内(例如，锗浓度超过50原子％，硼浓度超过2E20cm-3)。可任选的具有分级的(graded)锗和/或硼浓度的薄缓冲部可以用作与具有硼掺杂锗层的一种或多种下层衬底材料的分界面层。类似地，在双层结构中，具有分级的锗和/或硼浓度的薄缓冲部可以用作与具有硼掺杂锗帽层的硅锗层的分界面层，在其他的实施例中，硼掺杂锗或硅锗层自身可以以类似于可任选的缓冲部的方式具有分级的锗和/或硼浓度。在任何此类情况下，由于在锗中抑制了硼扩散(浓度越高，抑制越大)，可以在锗中掺杂高浓度的硼，这又导致较低的寄生电阻，且不会使尖端的陡度降级。另外，由于肖特基势垒高度的降低，减小了接触电阻。这些技术例如可以体现在平面或非平面FinFET晶体管器件中。
概述
众所周知，金属氧化物半导体(MOS)晶体管可以包括源极与漏极尖端区，将它们设计为降低晶体管的整体电阻，同时改善短沟道效应(SCE)。传统上，这些尖端区是衬底的使用注入和扩散技术注入了诸如硼或碳的掺杂剂的部分。在源极区与沟道区之间的区域中形成源极尖端区。类似地，在漏极区与沟道区之间的区域中形成漏极尖端区。通过这种传统处理得到的尖端区最低限度地下扩散(underdiffuse)晶体管的栅极电介质层。
更具体地，图1A示出了形成于衬底102上的传统MOS晶体管100A。通常通过将诸如硼的掺杂剂注入衬底中，或者通过蚀刻衬底，随后外延沉积硅或硅锗材料(具有10到40原子％范围中的锗浓度)，来形成源极区110和漏极区112。在晶体管100A的沟道区120上形成栅极堆叠体122。可以进一步看出，栅极堆叠体122包括栅极电介质层106和栅极电极104，相邻于栅极堆叠体122形成间隔体108。在一些实例情况下，并且取决于技术节点，间隔体108在栅极电介质层106的边缘与每一个源极区和漏极区110/112的边缘之间产生约10到20纳米(nm)的距离。在这个间隔内形成源极尖端区110A和漏极尖端区112A。如图所示，基于注入-扩散的尖端区110A/112A与间隔体108重叠，并还可以以小于10nm的距离与栅极电介质层106重叠或对其进行下扩散。在形成基于注入-扩散的尖端区110A/112A的过程中，将诸如硼或碳的掺杂剂注入源极区110和漏极区112中。随后对晶体管100A进行退火，以使得掺杂剂向沟道区120扩散。成角度的离子注入技术也可以用于将掺杂剂进一步注入在栅极电介质层106与源极/漏极区110/112之间的那些区域中。不幸的是，诸如尖端区110A/112A的形状、掺杂剂在间隔体108下渗透的距离、和尖端区110A/112A的浓度梯度之类的因素取决于掺杂剂在衬底材料中的扩散特性。例如，尖端区的浓度在源极/漏极区110/112附近将较高，而在沟道区120附近将较低。尽管是非常希望的，但几乎不可能在不驱使掺杂剂进入沟道区120的情况下，使得掺杂剂浓度在沟道区120附近极高。而且，不能移动源极和漏极区110/112使其更接近沟道区120，因为会同样驱使掺杂剂进入沟道区120中。这限制了可以将源极和漏极区110/112形成得有多接近沟道区120，从而约束了栅极长度缩放。
图1B示出了示例性MOS器件100B，其包括根据本发明实施例配置的源极和漏极外延尖端(本文中通常称为外延尖端(epi-tip))。更具体地，MOS晶体管100B使用底切蚀刻，以允许源极区110和漏极区112在间隔体108下方延伸，在一些情况下，是在栅极电介质层106下方延伸。本文中将在间隔体108(有可能在栅极电介质层106)下方延伸的源极/漏极区110/112的部分分别称为源极外延尖端110B和漏极外延尖端112B。源极和漏极外延尖端110B/112B代替针对图1A所述的基于注入/扩散的尖端区110A/112A。
根据本发明的实施例，如图1B所示，例如可以通过：蚀刻衬底102，其包括底切间隔体108(有可能是栅极电介质层106)；随后使用选择性外延沉积来提供原位硼掺杂锗，或者覆盖有重硼掺杂锗的硼掺杂硅锗(SiGe)，以填充源极/漏极区110/112和源极/漏极外延尖端110B/112B，来形成源极/漏极区110/112和源极/漏极外延尖端110B/112B。注意，外延填充可以相对于衬底102的表面隆起，如图1B中进一步示出的。
根据本发明的一些实施例，取决于诸如衬底成分和将在器件结构的不同层之间禁止失配位错的程度之类的因素，分级的缓冲部可以用于更多结构或结构的更多位置。例如，衬底102可以是硅衬底，或者绝缘体上硅(SOI)的硅膜衬底，或者多层衬底，其包括硅、硅锗、锗、和/或III-V族化合物半导体。因此，示例性地，在具有硅或硅锗衬底102，且原位硼掺杂锗用于填充源极/漏极区110/112和源极/漏极外延尖端110B/112B的实施例中，可以在下层衬底102与上层硼掺杂锗之间提供缓冲部。在这个实施例中，缓冲部可以是分级的硼掺杂的(或本征的)硅锗层，其具有从与下层硅衬底或硅锗衬底相容的基准级别(base level)浓度到高达100原子％(或接近100原子％，诸如超过90原子％或95原子％或98原子％)分级的锗成分。在一个特定的这种实施例中，锗浓度范围从小于等于40原子％到超过98原子％。这个缓冲部内的硼浓度例如可以固定在高级别或等级，例如从处于下层衬底的或与其相容的基准浓度到预期的高浓度(例如，超过1E20cm-3或5E20cm-3)。注意，本文所用的相容性并非必须要求浓度级别重叠(例如，下层衬底的锗浓度可以是0到20原子％，缓冲部的初始锗浓度可以是30到40原子％)。另外，本文所用的相对于浓度级别的词语“固定”旨在表示相对恒定的浓度级别(例如，层中最低浓度级别在该层内最高浓度级别的10％以内)。在更普遍的意义上，固定的浓度级别旨在表示缺少有意分级的浓度级别。缓冲部的厚度可以根据诸如缓冲的浓度的范围之类的因素而改变，但在一些实施例中，缓冲部的厚度在30到120埃
Figure BDA0001049147150000051
的范围中，诸如50到
Figure BDA0001049147150000052
(例如，
Figure BDA0001049147150000053
或
Figure BDA0001049147150000054
)。根据本公开内容将会意识到，这种分级的缓冲部有益地降低了肖特基势垒高度。
可替换地，不是使用在下层衬底102与上层硼掺杂锗之间的薄缓冲部，可以以类似的方式将硼掺杂锗层自身分级。例如，根据一个示例性实施例，可以以从与下层衬底相容的基准级别浓度(例如，在30到70原子％范围中)到高达100原子％分级的锗浓度来配置硼掺杂锗层。在一些这种实施例中，该硼掺杂锗层内的硼浓度范围例如可以是从处于下层衬底的或与之相容的基准浓度到预期的高浓度(例如，超过1E20cm-3)。
在具有硅或硅锗衬底102，及原位硼掺杂的SiGe与填充源极/漏极区110/112和源极/漏极外延尖端110B/112B的硼掺杂锗帽层的双层结构的其他实施例中，可以在硼掺杂的SiGe层与上层硼掺杂锗帽层之间提供缓冲部。在一个这种实施例中，硼掺杂的SiGe层具有固定的锗浓度(例如，在30到70原子％范围中)，缓冲部可以是薄SiGe层(例如，30到
Figure BDA0001049147150000055
诸如50到
Figure BDA0001049147150000056
)，其具有从与下层硼掺杂的SiGe层相容的基准级别浓度到高达100原子％(或接近100原子％，诸如超过90原子％或95原子％或98原子％)分级的锗浓度。在一些这种情况下，该缓冲部内的硼浓度例如可以固定在高级别，或者范围例如可以是从处于下层SiGe层的或与之相容的基准浓度到预期的高浓度(例如，超过1E20cm-3、2E20cm-3、3E20cm-3、4E20cm-3、或5E20cm-3)。
可替换地，不是使用在双层结构的两层之间的薄缓冲部，可以以类似的方式对硼掺杂的SiGe层自身分级。例如，根据一个示例性实施例，可以以从与下层衬底相容的基准级别浓度(例如，在30到70原子％的范围中)到高达100原子％(或者如前解释的接近100原子％)分级的锗浓度来配置硼掺杂的SiGe层。在该硼掺杂的SiGe层内的硼浓度例如可以固定在高级别或者例如可以在从处于下层衬底的或与之相容的基准浓度到预期的高浓度(例如，超过1E20cm-3)的范围中。
因此，提供了用于平面和非平面FinFET晶体管器件的SET架构。可以部分地使用传统工艺来形成器件，例如通过虚设栅极氧化物、薄间隔体、及各向同性底切蚀刻(或者氨蚀刻，以在单晶衬底中形成有小面的(faceted)鳍凹槽，或者用以形成鳍凹槽的其他适合的蚀刻)来形成器件。根据一些实施例，选择性外延沉积随后可以用于提供原位硼掺杂锗，或者可替换地，覆盖有重硼掺杂的纯锗的充分应变的硼掺杂硅锗层，以形成尖端和源极/漏极区。可以如前所解释地使用可任选的缓冲部。借助这种实施例，无需P型源极和漏极(PSD)注入或基于高温扩散的退火，因为硼在沉积时是完全活性的。也可以使用任何适合的高-k置换金属栅极(RMG)工艺流程，其中高-k电介质代替了虚设栅极氧化物。例如，利用镍、镍-铂、或者进行了或没有进行锗的预先非晶化注入的钛的硅化(silicidation)可以用于形成低电阻锗化物。如前解释的，这种实施例延伸SET晶体管器件架构，以达到(几乎)单轴应变的理论极限。本文提供的技术例如可应用，以有益于任何技术节点(例如，90nm、65nm、45nm、32nm、22nm、14nm和10nm晶体管，及更低的)，所要求保护的本发明并非旨在局限于器件几何尺寸的任何特定的此类节点或范围。根据本公开内容，其他优点会显而易见。
例如，注意到可以以与源极和漏极区110/112相同的工艺来形成根据本发明实施例配置的源极和漏极外延尖端110B/112B，这减小了工艺时间。另外，与传统的基于注入/扩散的尖端区不同，根据本发明实施例配置的源极/漏极外延尖端110B/112B的晶格参数引起了沟道区120中的应变，这增大了空穴迁移率，并因此减小了沟道中的电阻。根据本发明一些实施例配置的SET架构的另一个优点在于在源极/漏极外延尖端110B和112B与形成沟道区120的衬底材料102之间的分界面是突变的(abrupt)。例如，在分界面的一侧上是外延沉积的硼掺杂锗(B:Ge)材料(例如，具有超过2E20cm-3或5E20cm-3的B浓度)，在分界面的另一侧上是衬底材料，其构成沟道区120(例如，硅锗、或其他适合的衬底材料)。这个结构使得外延源极/漏极外延尖端110B/112B能够使重硼掺杂的高浓度锗材料非常接近沟道区120。外延源极/漏极外延尖端110B/112B中的硼在外延尖端内基本上或完全保留，而不趋向于扩散到沟道区120中。
可以用于形成源极和漏极外延尖端110B/112B的传统方法会存在应考虑的问题。具体地，参考图1B和1C，传统底切蚀刻技术可以导致底切区形成子弹形轮廓。在这种情况下，在略低于栅极电介质层106处比直接相邻于栅极电介质层106处蚀刻了更多的衬底材料。这样，源极外延尖端110B和漏极外延尖端112B每一个都与该子弹形轮廓相一致，这会在沟道区120中产生非最佳的应变。而且，传统底切蚀刻技术中的偏差可以转换为形成的所得到的源极和漏极外延尖端110B/112B中的偏差。使用形成源极和漏极外延尖端110B/112B的传统方法的另一个问题涉及间隔体厚度对底切蚀刻的影响，如图1B和1C所示。参考图1B，将MOS晶体管100B示出为具有第一厚度x1的偏移间隔体108。执行了衬底蚀刻，其底切间隔体108和一部分栅极电介质层106，以实现源极和漏极外延尖端110B/112B的形成。底切到底切(UC到UC)距离114将源极外延尖端110B与漏极外延尖端112B分离。参考图1C，将MOS晶体管100C示出为具有厚度x2的偏移间隔体108。在此，厚度x2比图1B的间隔体108的厚度x1大得多。结果，当执行衬底蚀刻时，较厚的间隔体108将底切蚀刻向外推(push out)，并导致源极/漏极外延尖端110B/112B被进一步远离晶体管100C的沟道区120形成。衬底蚀刻因此底切MOS晶体管100C下方较少的表面区。因此，MOS晶体管100C的UC到UC距离116比MOS晶体管100B的UC到UC距离114大得多。以此方式改变UC到UC距离产生MOS晶体管的大驱动电流变化。图1D是示出间隔体厚度如何影响使用已知方法形成的器件中UC到UC距离的曲线图。该曲线图提供了由线118代表的数据，显示了随着间隔体厚度增大，UC到UC距离也增大，从而导致大驱动电流变化。通常，间隔体厚度增大每一纳米，UC到UC距离就增大约2nm。在此意义上，使用传统方法形成源极/漏极外延尖端至少在一些情况下允许偏移间隔体的厚度对MOS器件的性能具有显著影响。如根据本公开内容将会意识到的，本发明的一些实施例提供了形成自对准和外延沉积的源极和漏极尖端的方法，其解决了此类问题。
架构和方法
图2是根据本发明实施例的构造具有自对准源极和漏极外延尖端的MOS晶体管的方法200。图3A到3J示出了根据一些实施例的随着执行方法200而形成的示例性结构。
如图所示，方法200以提供202半导体衬底开始，在该衬底上可以形成诸如PMOS晶体管的MOS器件。例如可以以块硅或绝缘体上硅结构来实现半导体衬底。在其他实现方式中，可以使用可以结合或不结合硅的替换的材料来形成半导体衬底，所述替换的材料诸如锗、硅锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。在更普遍的意义上，根据本发明的实施例，可以使用可以充当在其上可以构造半导体器件的基础的任何材料。
方法200继续，在半导体衬底上形成204栅极堆叠体。可以如传统所实施的那样来形成栅极堆叠体，或者可以使用任何适合的定制技术来形成栅极堆叠体。在本发明的一些实施例中，可以通过沉积，随后对栅极电介质层和栅极电极层进行构图来形成栅极堆叠体。例如，在一个示例性情况下，可以使用传统沉积工艺在半导体衬底上均厚沉积栅极电介质层，所述传统沉积工艺例如化学气相沉积(CVD)、原子层沉积(ALD)、旋涂沉积(SOD)、或物理气相沉积(PVD)。也可以使用替换的沉积技术，例如，可以热生长栅极电介质层。例如，可以由诸如氧化硅或高-k电介质材料的材料形成栅极电介质材料。高-k栅极电介质材料的实例例如包括二氧化铪、铪硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、氧化钛、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铌锌酸铅。在一些特定示例性实施例中，高-k栅极电介质层的厚度可以在约
Figure BDA0001049147150000081
到约
Figure BDA0001049147150000082
之间(例如，
Figure BDA0001049147150000083
到
Figure BDA0001049147150000084
)。通常，栅极电介质层的厚度应足以使得栅极电极与相邻的源极和漏极接触部电隔离。在进一步的实施例中，可以对高-k栅极电介质层执行额外的处理，诸如退火处理，以改进高-k材料的质量。接下来，可以使用诸如ALD、CVD、或PVD的类似的沉积技术在栅极电介质层上沉积栅极电极材料。在一些这种特定实施例中，栅极电极材料是多晶硅或金属层，尽管也可以使用其他适合的栅极电极材料。栅极电极材料通常是牺牲材料，稍后针对置换金属栅极(RMG)工艺将其去除，其在一些实施例中具有
Figure BDA0001049147150000091
到
Figure BDA0001049147150000092
范围中(例如
Figure BDA0001049147150000093
)的厚度。随后可以实施传统的构图工艺，以蚀刻掉栅极电极层和栅极电介质层的部分，从而形成栅极堆叠体，如图3A所示。
图3A示出了衬底300，在其上形成栅极堆叠体。如可以借助这个示例性实施例看出的，栅极堆叠体包括栅极电介质层302(其可以是高-k栅极电介质材料)和牺牲栅极电极304。在一个特定示例性情况下，栅极堆叠体包括氧化硅栅极电介质层302和多晶硅栅极电极304。栅极堆叠体还可以包括栅极硬掩模层306，其在处理过程中提供某些益处或用途，诸如保护栅极电极304使其免于随后的离子注入工艺。可以使用诸如氧化硅、氮化硅、和/或常规电介质材料等典型的硬掩模材料来形成硬掩模层306。
进一步参考图2，在形成栅极堆叠体后，方法200继续进行离子注入工艺，以通过将掺杂剂注入206到衬底中来高度掺杂相邻于栅极堆叠体的衬底部分。例如可以基于掺杂剂增大其所注入的衬底材料的蚀刻速率的能力来选择用于离子注入工艺中的掺杂剂，并且为离子注入工艺所选择的特定掺杂剂可以基于衬底材料和随后蚀刻工艺中所使用的蚀刻剂而改变。可以选择以增大衬底的蚀刻速率的特定掺杂剂例如包括碳、磷和砷。例如，可以以1×1014到1×1016原子/cm3范围的剂量，使用在5到15千电子伏(keV)之间的注入能量来使用碳。可以以1×1014到5×1015原子/cm3范围的剂量，使用在1到5keV之间的注入能量来使用磷。可以以1×1014到5×1015原子/cm3范围的剂量，使用在2到5keV之间的注入能量来使用砷。根据本公开内容，其他适合的掺杂剂和剂量方案会是显而易见的。在一些实施例中，离子注入基本上在垂直方向上进行(即，垂直于衬底的方向)；而在其他实施例中，至少一部分离子注入工艺在成角度的方向上进行，以在栅极堆叠体下注入离子。注意，硬掩模306可以用于防止栅极电极304材料的掺杂。
接下来，方法200继续对衬底进行退火207，以驱使掺杂剂进一步进入衬底中，并减小在离子注入工艺过程中衬底所经受的任何损害。在一些实施例中，注入206和随后的退火207可以驱使离子到达例如2nm到20nm之间的衬底深度。可以例如在60秒或更少的(例如5秒)持续时间中在700℃到1100℃之间的温度下来实施退火207。将会理解的是，退火温度和持续时间在一个实施例与下一个实施例之间可以变化，这取决于诸如扩散速率、衬底材料、所用的掺杂剂及预期的最终掺杂剂浓度之类的因素。
图3B示出了离子注入和扩散工艺后的衬底300。如在这个示例性实施例中所示的，离子注入工艺为形成的MOS晶体管产生了相邻于栅极电介质层302的两个掺杂区308。在暴露于适当的蚀刻剂时，掺杂区308的蚀刻速率会高于周围衬底材料的蚀刻速率。一个掺杂区308会充当源极区的一部分，包括其自对准外延尖端。另一个掺杂区308会充当漏极区的一部分，包括其自对准外延尖端。在所示的示例性实施例中，掺杂区308的部分位于栅极电介质层302以下。注意，包括其深度的掺杂区308的尺寸可以基于对形成的MOS晶体管的要求而改变。
接下来，方法200继续，在栅极堆叠体的任一侧上形成208间隔体。例如可以使用诸如氧化硅、氮化硅或其他适合的间隔体材料等常规材料来形成间隔体。通常可以基于对所形成的MOS晶体管的设计要求来选择间隔体的宽度。然而根据一些实施例，间隔体的宽度不受形成源极和漏极外延尖端所施加的设计约束的支配。图3C示出了根据示例性实施例的衬底300，其具有形成于栅极电极层304和栅极电介质层302的任一侧上的间隔体310。
进一步参考图2，方法200继续，干法蚀刻210衬底的掺杂区，以形成空腔，在其中可以形成包括其相应的外延尖端的源极/漏极区。参考图3D可以最好地了解到，蚀刻的空腔通常相邻于栅极堆叠体，外延尖端区实际上是源极/漏极空腔区的延伸。在一些示例性实施例中，可以将蚀刻的空腔形成为深度在50nm到1500nm之间，其可以比掺杂区更深。在更普遍的意义上，可以基于预期的MOS器件性能，根据需要设定蚀刻深度。在一些实施例中，干法蚀刻工艺可以使用是用于离子注入工艺中的掺杂剂的补充的蚀刻剂配方，以增大掺杂区的蚀刻速率，从而使得蚀刻工艺能够以快于衬底300的剩余部分的速率从掺杂区去除衬底材料。在一些实施例中，这包括底切间隔体310和栅极电介质层302的掺杂区的部分，由此定义了具体限定了晶体管的自对准尖端架构。增大掺杂区的蚀刻速率实现了在UC到UC距离基本上不受诸如间隔体厚度、干法蚀刻工艺中的偏差及其他工艺偏差等因素影响的情况下，蚀刻的源极和漏极尖端空腔能够底切间隔体310和栅极电介质层302。
根据一些实施例，干法蚀刻工艺可以使用在等离子体反应器中进行的氯化化学反应。在一些特定的这种实施例中，蚀刻剂配方可以包括NF3与Cl2的组合，其中将氩或氦用作缓冲气体或载运气体。根据一些这种实施例，活性蚀刻剂品种的流速例如可以在每分钟50到200标准立方厘米(SCCM)之间变化，而载运气体的流速例如可以在150到400SCCM之间变化。根据一些这种实施例，可以例如以700W到1100W范围的功率，以小于100W的低RF偏置来使用高能等离子体。根据一些这种实施例，反应器压力可以在约1帕斯卡(Pa)到约2Pa的范围。在另一个特定示例性实施例中，蚀刻剂化学试剂可以包括HBr与Cl2的组合。在一些这种实施例中，蚀刻剂品种的流速例如可以在40SCCM到100SCCM之间变化。根据一些这种实施例，可以例如以约600W到约1000W范围的功率，以小于100W的低RF偏置来使用高能等离子体，反应器压力可以在约0.3Pa到约0.8Pa的范围。在另一个示例性实施例中，蚀刻剂化学试剂可以包括Ar与Cl2的组合。在一些这种实施例中，蚀刻剂品种的流速例如可以在40SCCM到80SCCM之间变化。根据一些这种实施例，可以例如以约400W到约800W范围的功率，以在约100W到200W之间的高RF偏置来使用中等能量等离子体，反应器压力可以在约1Pa到约2Pa的范围。对于这些示例性实施例中的每一个，干法蚀刻工艺的时间例如可以高达每衬底60秒，但可以根据诸如预期的蚀刻深度和蚀刻剂等因素变化。如将会理解的那样，这种蚀刻工艺参数可以改变。
图3D示出了根据本发明一些实施例的实施干法蚀刻工艺后的衬底300。如图所示，形成源极区空腔312和漏极区空腔314。另外，通过如前所述的掺杂区的蚀刻210分别作为空腔312和314的延伸形成源极尖端空腔312A和漏极尖端空腔314A。注意，由于在蚀刻210过程中使用增大了掺杂区的蚀刻速率的掺杂剂和蚀刻剂配方，间隔体310的厚度对源极尖端空腔312A和漏极尖端空腔314A的蚀刻具有最低限度的影响。
在完成干法蚀刻工艺后，进一步参考图2，这个示例性实施例的方法继续进行湿法蚀刻212，以清洁并进一步蚀刻源极区空腔312及其源极外延尖端空腔312A，以及漏极区空腔314及其漏极外延尖端空腔314A。可以使用传统或定制的湿法蚀刻化学反应来实施湿法蚀刻212，湿法蚀刻212可以用于去除诸如碳、氟、含氯氟烃及氧化物(诸如氧化硅)之类的污染物，以提供清洁的表面，在其上可以实施随后的工艺。另外，假定是单晶硅衬底，湿法蚀刻212还可以用于沿<111>和<001>晶面去除衬底的薄部分，以提供光滑表面，在其上可以进行高质量的外延沉积。在一些示例性情况下，蚀刻掉的衬底的薄部分例如可以高达5nm厚，还可以去除残留的污染物。如图3E中最佳示出的，湿法蚀刻212导致源极区空腔312及其外延区312A，以及漏极区空腔314及其外延尖端区314A的边缘遵循<111>和<001>晶面。此外注意，源极和漏极外延尖端区312A和314A不具有在传统处理中出现的子弹形轮廓。
在完成湿法蚀刻工艺后，进一步参考图2，方法200继续进行在源极/漏极及相应的尖端空腔中外延沉积214原位硼掺杂锗(在一些情况下具有居间的薄缓冲部)，或者覆盖有重硼掺杂锗层的硼掺杂硅锗。根据一些实施例，在一个工艺中该外延沉积填充包括其相应的外延尖端区的源极和漏极空腔。CVD工艺或其他适合的沉积技术可以用于沉积214。例如，可以在CVD反应器、LPCVD反应器或超高真空CVD(UHVCVD)中实施沉积214。在一些示例性情况下，反应器温度例如可以在600℃到800℃之间，反应器压力例如可以在1到760Torr之间。载运气体例如可以包括在诸如10到50SLM之间的适当流速的氢或氦。在一些特定实施例中，可以使用诸如GeH4的锗源前驱气体来实施沉积，其在H2中被稀释(例如，可以将GeH4稀释为1-5％)。例如，可以以1％的浓度和50到300SCCM范围的流速来使用稀释的GeH4。对于硼的原位掺杂，可以使用稀释的B2H6(例如，可以在H2中将B2H6稀释为1-5％)。例如，可以以3％的浓度和10到100SCCM范围的流速来使用稀释的B2H6。在一些示例性情况下，可以增加蚀刻剂，以增大沉积的选择性。例如，可以以50到300SCCM范围的流速添加HCl或Cl2。
根据本发明的一些示例性实施例，并如图3F最佳示出的，以原位硼掺杂锗填充源极和漏极区空腔312/314连同其相应的尖端区312A/314A，从而在衬底300中形成MOS晶体管316的源极区318(连同外延尖端318A)和漏极区320(连同漏极外延尖端320A)。在一些这种实施例中，硼掺杂锗具有超过5E20cm-3的硼浓度，例如2E21cm-3或者更高。根据一些特定实施例，硼掺杂锗沉积层的厚度例如范围可以在50到500nm之间(例如，120nm)，尽管根据本公开内容，其他层厚度会是显而易见的。如前解释的，一些这种实施例可以包括在纯锗层与衬底之间具有薄缓冲部。例如，可以进一步在图3F所示的示例性实施例中见到，在沉积原位硼掺杂锗之前沉积源极缓冲部313和漏极缓冲部315。在一些这种实施例中，缓冲部313和315可以是分级的硼掺杂硅锗层，其中锗成分从与下层衬底300材料相容的基准级别浓度到高达100原子％(或如前所述的接近100原子％)分级。缓冲部313和315的厚度将根据诸如缓冲部过渡的浓度范围和下层衬底300的组成之类的因素而变化。在具有硅锗衬底的一个示例性实施例中，缓冲部厚度的范围从2nm到10nm，尽管也可以使用其他适合的厚度。在一个特定的这种实施例中，缓冲部313和315内的硼浓度的范围例如从与下层硅锗衬底相容的基准浓度到预期浓度(例如，超过1E20cm-3，一直到2E21cm-3)，两个特定实施例超过2E20cm-3或超过5E20cm-3。在更普遍的意义上，必要时可以调整硼浓度，以提供预期程度的导电性，如根据本公开内容会意识到的。
根据本发明的其他示例性实施例，及在图3G中最佳示出的，以原位硼掺杂硅锗填充源极与漏极区空腔312/314连同其相应的尖端区312A/314A，以在衬底300中形成MOS晶体管316的源极区318(连同外延尖端318A)和漏极区320(连同漏极外延尖端320A)。随后以重硼掺杂锗层覆盖硼掺杂硅锗填料，以提供源极帽层317和漏极帽层319。在一些这种双层结构实施例中，可以外延沉积在一个或多个层中的硼掺杂硅锗填料具有范围在30到70原子％或者更高的锗浓度。如前所解释的，SiGe填料的该锗浓度可以是固定的或者分级的，以便从基准级别(接近衬底300)增大到高级别(例如，超过50原子％，接近纯锗帽层317/319)。在一些这种实施例中，硼浓度可以超过1E20cm-3，诸如高于5E20cm-3或2E21cm-3，并且也可以分级，以便从接近衬底300的基准级别增大到高级别(例如超过1E20cm-3或2E20cm-3或3E20cm-3等，接近帽层317/319。在硼掺杂SiGe层的锗浓度固定的实施例中，薄分级缓冲部可以用于更好地连接硼掺杂SiGe层与硼掺杂Ge帽层，如前所解释的。根据一些特定实施例，硼掺杂SiGe沉积层(或层的集合)的厚度318/320例如可以在50到250nm(例如60nm)范围中，纯锗帽层317/319可以具有例如50到250nm(例如50nm)范围中的厚度，尽管可替换的实施例可以具有其他层和帽层厚度，如根据本公开内容将显而易见的。在一些实施例中，注意可以在循环沉积-蚀刻处理过程中，在间隔体下方产生空腔，这些空腔也可以由外延帽层回填(其例如可以具有与硼掺杂锗帽层317/319相同的成分)。
如根据本公开内容会进一步理解的，诸如针对图3F和3G中所示的实施例论述的高锗浓度(例如，超过50原子％，一直到纯锗)和高硼浓度(例如，超过1E20cm-3)的组合可以用于在PMOS SET晶体管器件的源极和漏极区以及它们相应的尖端区中实现高得多的传导性。此外，如前所解释的，由于硼扩散受到纯锗的充分抑制，所以尽管沉积的压力膜(stressorfilm)中的硼较高，随后的退火也没有获得不利的SCE降级。由在接触面的较高锗浓度也实现了势垒高度的降低。在一些示例性实施例中，超过95原子％到高达纯锗(100原子％)的锗浓度可以用于获得这种益处。
如图3F与3G进一步示出的，与通过注入和扩散技术形成的，并因此在尖端区与沟道区之间不具有清晰的边界的传统源极和漏极尖端区不同，MOS晶体管316的自对准源极和漏极外延尖端具有突变的边界。换句话说，在源极/漏极外延尖端与沟道区之间的分界面清晰且明确。在分界面的一侧上是重硼掺杂锗层(图3F的层318/320，或者图3G的帽层317/319)，在分界面的另一侧上是衬底300材料，其构成沟道区。源极/漏极外延尖端318A/320A中的硼基本上或者完全保留在外延尖端内，而不趋向于扩散到沟道区中，从而使得重硼掺杂锗材料相对于传统技术能够极为接近沟道区。例如，在一些特定实施例中，源极/漏极外延尖端318A/328A可以底切栅极电介质层302超过10nm。这又使得能够在不必须缩短沟道区的情况下缩减栅极长度。
相对接近沟道区形成源极和漏极外延尖端还给沟道施加了较大的流体静应力。该应力增大了沟道内的应变，从而增大了沟道中的迁移率并增大了驱动电流。通过增大源极和漏极外延尖端的锗浓度可以进一步放大该应力。这是对尖端区通常不在沟道区上引起应变的基于扩散的工艺的改进。
一旦根据本发明的实施例填充了源极和漏极区，就可以实施多种传统MOS处理，以完成MOS晶体管316的构造，例如置换栅极氧化物的工艺、置换金属栅极的工艺、退火和自对准多晶硅化(salicidation)工艺，它们可以进一步修改晶体管316和/或提供必要的电连接。例如，在源极/漏极区连同其相应的尖端的外延沉积后，进一步参考图2，方法200可以继续进行在晶体管316上沉积216层间电介质(ILD)，随后按照通常所实施的那样对ILD层进行平坦化。可以使用已知的适用于集成电路结构的电介质层中的材料来形成ILD层，例如低-k电介质材料。这种电介质材料例如包括诸如氧化硅(SiO2)和碳掺杂氧化物(CDO)之类的氧化物、氮化硅、诸如八氟环丁烷或聚四氟乙烯之类的有机聚合物、氟硅酸盐玻璃(FSG)、和诸如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃之类的有机硅酸盐。在一些示例性结构中，ILD层可以包括小孔或其他孔隙，以进一步减小其介电常数。图3H示出了示例性ILD层322，已经对其进行了沉积，并随后向下平坦化到硬掩模306。
接下来，在使用了置换金属栅极工艺的本发明的一些实施例中，方法200继续使用如传统所实施的蚀刻工艺，去除218栅极堆叠体(包括高-k栅极电介质层302、牺牲栅极电极304和硬掩模层306)。在替换的实现方式中，仅去除牺牲栅极304。图3I示出了根据一个这种实施例的在蚀刻掉栅极堆叠体时形成的沟槽开口。如果去除栅极电介质层，该方法就可以继续进行在沟槽开口中沉积220新的栅极电介质层。在此可以使用如前所述的任何适合的高-k电介质材料，例如二氧化铪。也可以使用相同的沉积处理。栅极电介质层的置换例如可以用于应对在干法和湿法蚀刻工艺实施过程中会对原始栅极电介质层造成的任何损害，和/或以高-k或其他预期的栅极电介质材料来代替低-k或牺牲电介质材料。
方法200随后可以继续进行将金属栅极电极层沉积222到沟槽中和栅极电介质层上。传统金属沉积工艺可以用于形成金属栅极电极层，例如CVD、ALD、PVD、无电镀或电镀。金属栅极电极层例如可以包括P型功函数金属，例如钌、钯、铂、钴、镍，和导电金属氧化物，例如氧化钌。在一些示例性结构中，可以沉积两个或更多个金属栅极电极层。例如，可以沉积功函数金属，之后是诸如铝的适合的金属栅极电极填料金属。图3J示出了根据一个实施例的，已经沉积到沟槽开口中的示例性高-k电介质层324和金属栅极电极326。
使用硅化工艺(通常沉积接触部金属并随后进行退火)来实施源极和漏极接触部的金属化。例如，以镍、铝、镍-铂或镍-铝或镍和铝的其他合金、或者进行或没有进行锗的预先非晶化注入的钛进行的硅化可以用于形成低电阻锗化物。硼掺杂锗外延层允许金属-锗化物形成(例如，镍-锗)。锗化物允许比传统金属硅化物系统低得多的肖特基势垒高度及改善的接触电阻(包括Rext)。例如，传统晶体管通常使用源极/漏极SiGe外延工艺，其中锗浓度在30-40原子％范围中。受到外延/硅化物分界面电阻的限制，这种传统系统呈现了约140Ohm*um的Rext值，其较高并且将来会阻碍栅极间距缩放。本发明的一些实施例允许PMOS器件中Rext相当大的改善(例如，约2倍的改善，或者约70Ohm*um的Rext)，这可以更好地支持PMOS器件缩放。因此，具有以根据本发明实施例的重硼掺杂锗配置的源极/漏极的晶体管可以呈现出小于100Ohm*um的Rext值，在一些情况下小于90Ohm*um，在一些情况下小于80Ohm*um，在一些情况下小于75Ohm*um或者更低，其中在源极/漏极外延尖端与沟道区之间的分界面具有超过1E20cm-3的硼浓度、超过50原子％并高达或者接近纯锗(100原子％)的锗浓度。
相应地，公开了自对准源极和漏极外延尖端，其由于增大的硼掺杂锗的量(例如，硼掺杂锗或具有锗帽层的硼掺杂硅锗的量)而减小了MOS晶体管的整体电阻，增大了沟道应变。在一些这种实施例中，源极和漏极外延尖端不具有子弹形轮廓，在沟道区与源极和漏极区之间形成突变的边界，和/或具有更易于控制的掺杂浓度，从而产生了更优化的源-漏剖面。此外，根据一些实施例，通过选择适当的掺杂剂和蚀刻剂配方的组合，可以在基本上不受间隔体厚度影响的情况下蚀刻源极和漏极外延尖端。该自对准工艺因此可以用于在需要时提高性能，同时使得工艺偏差最小化。
FinFET结构
众所周知，FinFET是围绕半导体材料的薄带(通常称为鳍)构造的晶体管。晶体管包括标准场效应晶体管(FET)节点，包括栅极、栅极电介质、源极区和漏极区。器件的导电沟道位于栅极电介质下方鳍的外侧上。具体地，电流沿鳍的两个侧壁(垂直于衬底表面的侧面)以及鳍的顶部(平行于衬底表面的侧面)流动。因为这种结构的导电沟道的位置基本上沿着鳍的三个不同的外部平面区，这种FinFET设计有时称为三栅极FinFET。其他类型的FinFET结构也是可用的，诸如所谓的双栅极FinFET，在其中导电沟道的位置主要仅沿着鳍的两个侧壁(而不沿鳍的顶部)。
图4示出了根据本发明的一个实施例配置的示例性三栅极架构的透视图。如图所示，三栅极器件包括具有半导体主体或鳍260(由虚线表示)的衬底400，半导体主体或鳍260从衬底400通过隔离区710、720延伸。在鳍260的3个表面上形成栅极电极340以形成3个栅极。在栅极电极340的顶部上形成硬掩模410。在栅极电极340的相反侧壁上形成栅极间隔体460、470。源极区包括形成于凹陷的源极分界面266和一个鳍260的侧壁上的外延区531，漏极区包括形成于凹陷的源极分界面266和相反的鳍260的侧壁(未示出)上的外延区531。帽层541沉积在外延区531上。在一个实施例中，隔离区710、720是通过常用技术形成的浅槽隔离(STI)区，诸如蚀刻衬底200以形成沟槽，随后将氧化物材料沉积在沟槽上，以形成STI区。隔离区710、720可以由诸如SiO2的公知的绝缘材料制成。先前针对衬底102的论述在此也是同样适用的(例如，衬底400可以是硅衬底，或SOI衬底，或多层衬底)。
如根据本公开内容会理解的，传统工艺和形成技术可以用于制造三栅极晶体管结构。但根据本发明的一个示例性实施例，可以使用以重硼掺杂锗覆盖的原位硼掺杂硅锗来实现外延区531和帽层541的双层结构，在两个双层之间具有可任选的锗和/或硼的分级的缓冲部。如前解释的，这种缓冲部可以用于从与在凹陷的源极分界面266中为外延区531沉积的硼掺杂SiGe相容的基准级别锗/硼浓度过渡到重硼掺杂的锗帽层541。可替换地，可以直接在外延区531中，而不是在居间的分级缓冲部布置中实现锗和/或硼浓度的分级。如会进一步理解的，注意到三栅极结构的可替换方式是双栅极架构，其包括在鳍260顶部上的电介质/隔离层。
图5是示出通过使用根据本发明的一个示例性实施例配置的自对准源极和漏极外延尖端可获得的改进的曲线图。线500表示为使用本文提供的技术构造的MOS器件收集的数据。如图所示，UC到UC距离受到间隔体厚度的影响比使用传统工艺形成的器件小得多，后者的数据同样由线118表示。图6A和6B进一步展示了通过使用根据本发明的一个示例性实施例配置的自对准源极和漏极外延尖端实现的改进。具体地，图6A示出了肖特基势垒NiGe二极管测量值(泄露相对于电压)，证实了镍锗功函数是极为p型的(大致高于Ge价带85mV)。图6B描绘了根据本发明一些实施例的仿真数据，其显示了这种锗化物材料和肖特基势垒高度的改进相对于传统SiGe源极/漏极PMOS器件实现了2倍的Rext改善。众所周知，肖特基势垒高度是横跨半导体-金属结的电传导的整流势垒。肖特基势垒高度的量值反应了金属的费米能级的势能与横跨半导体-金属分界面的半导体的多数载流子能带边缘的不匹配。对于p型半导体-金属分界面，肖特基势垒高度是金属费米能级与半导体的价带最大值之间的差。
这样，如根据本公开内容会理解的，本文提供的本发明的多个实施例可以用于应对几个晶体管尺寸调节问题，诸如利用间距和电源(Vcc)大小调整提供较高的沟道迁移率，提供减小的源极/漏极和接触电阻，提供改进的沟道突变，提供在自对准多晶硅化物与源极/漏极之间的减小的势垒高度以使得总寄生电阻最小化，尤其是在平面与非平面架构中。根据本公开内容，多个实施例将是显而易见的。
本发明的一个示例性实施例提供了一种晶体管器件。该器件包括具有沟道区的衬底。器件进一步包括在沟道区上的栅极电极，其中，在栅极电极与沟道区之间提供了栅极电介质层，在栅极电极的侧面上提供了间隔体。器件进一步包括形成于衬底中并与沟道区相邻的源极和漏极区，源极与漏极区中的每一个都包括尖端区，其在栅极电介质层和/或对应的一个间隔体下方延伸，其中，源极和漏极区包括硼掺杂锗层，该硼掺杂锗层具有超过50原子％的锗浓度和超过1E20cm-3的硼浓度。在一个此类情况下，器件是平面或FinFET PMOS晶体管中的一个。在另一个此类情况下，器件可以包括金属－锗化物源极和漏极接触部。在另一个此类情况下，器件可以包括在源极和漏极区上的间层电介质。在另一个此类情况下，器件可以包括在衬底与硼掺杂锗层之间的缓冲部。在一个此类特定情况下，缓冲部具有从与衬底相容的基准级别浓度到超过95原子％的高浓度分级的锗浓度。在另一个此类特定情况下，缓冲部具有从与衬底相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在另一个特定实施例中，硼掺杂锗层具有双层结构，包括硼掺杂硅锗部分和在其上的硼掺杂锗帽层。在一个此类特定情况下，硼掺杂硅锗部分具有从与衬底相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，硼掺杂锗帽层具有超过95原子％的锗浓度。在另一个此类特定情况下，硼掺杂硅锗部分具有从与衬底相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在另一个此类特定情况下，硼掺杂硅锗部分具有固定的锗浓度，器件进一步包括在硼掺杂硅锗部分与硼掺杂锗帽层之间的缓冲部，缓冲部具有从与硼掺杂硅锗部分相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，和从与硼掺杂硅锗部分相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在另一个特定情况下，晶体管具有小于100Ohm*um的Rext值(诸如Rext＝70Ohm*um，+/-10％)。如会理解的，可以基于诸如预期电导率之类的因素将硼浓度设定得较高，在一些此类示例性情况下，超过2E20cm-3或3E20cm-3或4E20cm-3或5E20cm-3或2E21cm-3。
本发明的另一个实施例提供了一种晶体管器件，在这个示例性情况下，器件包括具有沟道区的衬底，和在沟道区上的栅极电极，其中在栅极电极与沟道区之间提供了栅极电介质层，在栅极电极的侧面上提供了间隔体。器件进一步包括形成于衬底中并与沟道区相邻的源极和漏极区，源极和漏极区中的每一个都包括尖端区，所述尖端区在栅极电介质层和/或对应的一个间隔体下方延伸，其中，源极和漏极区包括硼掺杂锗层，该硼掺杂锗层具有超过50原子％的锗浓度和超过2E20cm-3的硼浓度。器件进一步包括金属-锗化物源极和漏极接触部。在一些此类情况下，器件可以进一步包括在衬底和硼掺杂锗层之间的缓冲部，其中，缓冲部具有从与衬底相容的基准级别浓度到超过95原子％的高浓度分级的锗浓度，和从与衬底相容的基准级别浓度到超过2E20cm-3的高浓度分级的硼浓度。在其他示例性情况下，硼掺杂锗层具有双层结构，包括硼掺杂硅锗部分和在其上的硼掺杂锗帽层。在某些此类特定情况下，硼掺杂硅锗部分具有从与衬底相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，硼掺杂锗帽层具有超过95原子％的锗浓度。在一些此类特定实施例中，硼掺杂硅锗部分具有从与衬底相容的基准级别浓度到超过2E20cm-3的高浓度分级的硼浓度。在其他特定情况下，硼掺杂硅锗部分具有固定的锗浓度，器件进一步包括在硼掺杂硅锗部分与硼掺杂锗帽层之间的薄缓冲部，缓冲部具有从与硼掺杂硅锗部分相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，和从与硼掺杂硅锗部分相容的基准级别浓度到超过2E20cm-3的高浓度分级的硼浓度，缓冲部具有小于100埃的厚度。
本发明的另一个实施例提供了一种用于形成晶体管器件的方法。该方法包括提供具有沟道区的衬底，及在沟道区上提供栅极电极，其中，在栅极电极与沟道区之间提供栅极电介质层，在栅极电极的侧面上提供间隔体。该方法继续，在衬底中并与沟道区相邻地形成源极和漏极区，源极与漏极区中的每一个都包括尖端区，所述尖端区在栅极电介质层和/或对应的一个间隔体下方延伸，其中，源极和漏极区包括硼掺杂锗层，该硼掺杂锗层具有超过50原子％的锗浓度和超过1E20cm-3的硼浓度。在某些此类实施例中，该方法进一步包括在衬底与硼掺杂锗层之间提供缓冲部，其中，缓冲部具有从与衬底相容的基准级别浓度到超过95原子％的高浓度分级的锗浓度，和从与衬底相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在其他实施例中，硼掺杂锗层具有双层结构，包括硼掺杂硅锗部分和在其上的硼掺杂锗帽层。在一个此类情况下，硼掺杂硅锗部分具有从与衬底相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，硼掺杂锗帽层具有超过95原子％的锗浓度。在另一个此类情况下，硼掺杂硅锗部分具有固定的锗浓度，该方法进一步包括在硼掺杂硅锗部分与硼掺杂锗帽层之间提供缓冲部，缓冲部具有从与硼掺杂硅锗部分相容的基准级别浓度到超过50原子％的高浓度分级的锗浓度，和从与硼掺杂硅锗部分相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。在某些此类情况下，硼掺杂硅锗部分具有从与衬底相容的基准级别浓度到超过1E20cm-3的高浓度分级的硼浓度。
出于图示和说明的目的提供了对本发明的示例性实施例的前述说明。其并非旨在是穷举性的或将本发明限制于所公开的准确形式。根据本公开内容，许多修改和变化是可能的。例如，本发明的一些实施例利用锗的原位硼掺杂，而其他实施例可以使用本征锗，在其沉积之后，随后对其进行硼注入和退火工艺，以提供预期的硼掺杂浓度。此外，一些实施例可以包括如本文所述构造的源极和漏极区(例如，具有超过50原子％的锗浓度和超过1E20cm-3的硼浓度)，但仍使用传统处理(例如，注入和退火)来形成源极和漏极区的尖端。在此类实施例中，尖端可以具有低于主源极/漏极区的锗和/或硼浓度，这在一些应用中是可接受的。在其他的实施例中，可以仅以高锗和硼浓度配置源极与漏极区的尖端，源极和漏极区的主要部分可以具有常规的，或者较低的锗/硼浓度。其意图是本发明的范围不局限于该具体实施方式部分，而是由所附的权利要求限定。

Claims (13)

1.一种集成电路结构，包括：
包括硅的鳍；
在所述鳍上方的栅极电极，所述栅极电极具有第一侧，并且所述栅极电极具有与所述第一侧相对的第二侧；
沿着所述栅极电极的所述第一侧的第一电介质间隔体；
所述鳍中邻近所述栅极电极的所述第一侧的第一源极区或漏极区，所述第一源极区或漏极区的一部分在所述第一电介质间隔体下方，并且所述第一源极区或漏极区包括多个小面和顶表面，其中，所述第一源极区或漏极区包括硅和锗，所述硅和锗具有被分级为浓度超过50％的锗浓度，并且其中，所述第一源极区或漏极区包括超过5E20cm-3的硼浓度；
在所述第一源极区或漏极区的所述顶表面上方的第一层，所述第一层包括硅、锗和钛；
沿着所述栅极电极的所述第二侧的第二电介质间隔体；
所述鳍中邻近所述栅极电极的所述第二侧的第二源极区或漏极区，所述第二源极区或漏极区的一部分在所述第二电介质间隔体下方，并且所述第二源极区或漏极区包括多个小面和顶表面，其中，所述第二源极区或漏极区包括硅和锗，所述硅和锗具有被分级为浓度超过50％的锗浓度，并且其中，所述第二源极区或漏极区包括超过5E20cm-3的硼浓度；以及
在所述第二源极区或漏极区的所述顶表面上方的第二层，所述第二层包括硅、锗和钛。
2.根据权利要求1所述的集成电路结构，其中，所述第一源极区或漏极区包括超过2E21cm-3的硼浓度，并且其中，所述第二源极区或漏极区包括超过2E21cm-3的硼浓度。
3.一种集成电路结构，包括：
包括硅的主体；
在所述主体上方的栅极电极，所述栅极电极具有第一侧，并且所述栅极电极具有与所述第一侧相对的第二侧；
沿着所述栅极电极的所述第一侧的第一电介质间隔体；
所述主体中邻近所述栅极电极的所述第一侧的第一源极区或漏极区，所述第一源极区或漏极区的一部分在所述第一电介质间隔体下方，并且所述第一源极区或漏极区包括多个小面和顶表面，其中，所述第一源极区或漏极区包括硅和锗，所述硅和锗具有被分级为浓度超过50％的锗浓度，并且其中，所述第一源极区或漏极区包括超过5E20cm-3的硼浓度；
在所述第一源极区或漏极区的所述顶表面上方的第一层，所述第一层包括硅、锗和钛；
沿着所述栅极电极的所述第二侧的第二电介质间隔体；
所述主体中邻近所述栅极电极的所述第二侧的第二源极区或漏极区，所述第二源极区或漏极区的一部分在所述第二电介质间隔体下方，并且所述第二源极区或漏极区包括多个小面和顶表面，其中，所述第二源极区或漏极区包括硅和锗，所述硅和锗具有被分级为浓度超过50％的锗浓度，并且其中，所述第二源极区或漏极区包括超过5E20cm-3的硼浓度；以及
在所述第二源极区或漏极区的所述顶表面上方的第二层，所述第二层包括硅、锗和钛。
4.根据权利要求3所述的集成电路结构，其中，所述第一源极区或漏极区包括超过2E21cm-3的硼浓度，并且其中，所述第二源极区或漏极区包括超过2E21cm-3的硼浓度。
5.一种集成电路结构，包括：
包括硅的鳍；
在所述鳍上方的栅极电极，所述栅极电极具有第一侧，并且所述栅极电极具有与所述第一侧相对的第二侧；
沿着所述栅极电极的所述第一侧的第一电介质间隔体；
在所述鳍上方并且邻近所述第一电介质间隔体的第一层，所述第一层包括硅、锗和钛；
所述第一层和所述鳍之间的第一半导体区，所述第一半导体区的一部分在所述第一电介质间隔体下方，并且所述第一半导体区包括多个小面和顶表面，其中，所述第一半导体区的第一区包括硅和锗，所述硅和锗具有被分级为浓度超过50％的锗浓度，并且其中，所述第一半导体区的第二区包括超过5E20cm-3的硼浓度；
沿着所述栅极电极的所述第二侧的第二电介质间隔体；
在所述鳍上方并且邻近所述第二电介质间隔体的第二层，所述第二层包括硅、锗和钛；以及
所述第二层和所述鳍之间的第二半导体区，所述第二半导体区的一部分在所述第二电介质间隔体下方，并且所述第二半导体区包括多个小面和顶表面，其中，所述第二半导体区的第一区包括硅和锗，所述硅和锗具有被分级为浓度超过50％的锗浓度，并且其中，所述第二半导体区的第二区包括超过5E20cm-3的硼浓度。
6.一种集成电路晶体管，包括：
包含沟道区的半导体主体；
在所述沟道区之上并且相邻于所述半导体主体的多个表面的栅极结构，所述栅极结构包含栅极电介质、栅极电极和栅极间隔体，所述栅极电介质位于所述栅极电极与所述沟道区之间，并且所述栅极间隔体位于所述栅极电极的侧面上；
源极区和漏极区，所述沟道区位于所述源极区与所述漏极区之间，并且所述源极区和所述漏极区中的每一个包含尖端区，所述尖端区在对应的一个所述栅极间隔体的下方延伸；以及
在所述尖端区中的硼掺杂的含锗层，所述硼掺杂的含锗层具有超过50原子％的锗浓度以及超过5E20cm-3的硼浓度，
其中，所述硼掺杂的含锗层包括：
硼掺杂硅锗部分；以及
位于所述硼掺杂硅锗部分上的硼掺杂锗帽层，并且
其中，所述硼掺杂硅锗部分具有被分级为从40原子％或更低的基准级别浓度到相对较高级别的锗浓度；
所述硼掺杂硅锗部分具有被分级为从相对较低的基准级别浓度到超过5E20cm-3的硼浓度；和/或
所述硼掺杂锗帽层具有超过95原子％的锗浓度。
7.根据权利要求6所述的集成电路晶体管，进一步包括：
在所述半导体主体与所述硼掺杂的含锗层之间的缓冲部，其中，所述缓冲部包括包含硅和锗的层，所述包含硅和锗的层具有
被分级为从40原子％或更低的基准级别浓度到相对较高级别的锗浓度，和/或
被分级为从相对较低的基准级别浓度到超过1E20cm-3的硼浓度。
8.根据权利要求7所述的集成电路晶体管，其中，所述缓冲部在所述沟道区与所述硼掺杂的含锗层之间的厚度在2nm到10nm的范围内。
9.根据权利要求6所述的集成电路晶体管，其中，所述集成电路晶体管进一步包括在所述硼掺杂硅锗部分与所述硼掺杂锗帽层之间的缓冲部，所述缓冲部具有
被分级为从40原子％或更低的基准级别浓度到相对较高级别的锗浓度，以及
被分级为从相对较低的基准级别浓度到超过1E20cm-3的硼浓度。
10.根据权利要求6所述的集成电路晶体管，其中所述栅极结构相邻于所述半导体主体的三个表面以提供三栅极晶体管构造。
11.根据权利要求6所述的集成电路晶体管，其中，所述集成电路晶体管是非平面PMOS晶体管。
12.根据权利要求6所述的集成电路晶体管，其中，所述源极区和所述漏极区被刻面并且填充有在所述沟道区上方延伸的材料。
13.根据权利要求6所述的集成电路晶体管，进一步包括源极接触部和漏极接触部，所述源极接触部和所述漏极接触部包含金属-锗化物。
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