CN107369644B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN107369644B
CN107369644B CN201610313243.XA CN201610313243A CN107369644B CN 107369644 B CN107369644 B CN 107369644B CN 201610313243 A CN201610313243 A CN 201610313243A CN 107369644 B CN107369644 B CN 107369644B
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layer
semiconductor material
semiconductor
metal
epitaxial
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CN107369644A (zh
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谢明修
杨钧耀
刘仕佑
林荣信
颜瀚廷
陈意维
胡益诚
林钰书
杨能辉
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201610313243.XA priority Critical patent/CN107369644B/zh
Priority to US15/175,045 priority patent/US9722030B1/en
Priority to US15/632,399 priority patent/US9966434B2/en
Publication of CN107369644A publication Critical patent/CN107369644A/zh
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Abstract

本发明公开一种半导体元件及其制作方法。其中该半导体元件包含有一其上形成有多个晶体管元件的基底、至少一设置于该多个晶体管元件之间的外延结构、以及一设置于该外延结构之上的三层结构。该外延结构包含有一第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数大于该第一半导体材料的一晶格常数。该三层结构包含有一未掺杂外延层、一金属‑半导体化合物层、以及一夹设于该未掺杂外延层与该金属‑半导体化合物层之间的掺杂外延层。该未掺杂外延层与该掺杂外延层包含有至少该第二半导体材料。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件，尤其是涉及一种包含有硅锗合金 (silicon/germanium alloy，以下简称为SiGe)的半导体元件。
背景技术
作为目前集成电路中的主要电路元件，数以百万计的晶体管可设置于一基底上，已组成所需的复杂集成电路，例如微处理器、中央处理单元、存储芯片等等。由此可知，晶体管尺寸大小，以及个别晶体管元件之间的间距是成为集成电路的关键。也就是说，集成电路里的晶体管尺寸以及间距都要尽可能的小，以达成高积集密度的目标。
而集成电路中的个别装置，例如金氧半导体场效晶体管 (metal-oxide-semiconductor field effect transistor，MOSFET)元件和其它被动和有源电路元件，都必须通过金属或其它导电体电连接，以实施所欲获得的电路功能。而这些电路装置与导电体之间的接触，存在一接触电阻。随着特征尺寸减小，接触电阻会增加而占了总电路电阻中越来越多的百分比。当特征尺寸从150纳米(nanometer，以下简称为nm)缩减到90nm，然后到45nm以及以下时，接触电阻变得越来越重要。在特征尺寸为32nm时，接触电阻甚至可能将支配芯片效能。因此，如何降低接触电阻，一直是业界致力之处。
发明内容
因此，本发明的一目的在于提供一种可降低接触电阻的半导体元件及其制作方法。
为达上述目的，本发明提供一种半导体元件，该半导体元件包含有一其上形成有多个晶体管元件的基底、至少一设置于该多个晶体管元件之间的外延结构、以及一设置于该外延结构之上的三层结构。该外延结构包含有一第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数大于该第一半导体材料的一晶格常数。该三层结构包含有一未掺杂外延层、一金属-半导体化合物层、以及一夹设于该未掺杂外延层与该金属-半导体化合物层之间的掺杂外延层。该未掺杂外延层与该掺杂外延层包含有至少该第二半导体材料。
根据本发明所提供的权利要求，更提供一种半导体元件的制作方法，该制作方法包含有以下步骤。首先，提供一基底，该基底上形成有多个晶体管元件、一介电层、以及至少一外延结构。该外延结构设置于该多个晶体管元件之间，且包含有一第一半导体材料与一第二半导体材料，该第二半导体材料的一晶格结构大于该第一半导体材料的一晶格结构。接下来，于该多个晶体管元件之间的该介电层内形成至少一开口，且该外延结构暴露于该开口的一底部。在形成该开口之后，于该开口内形成一未掺杂外延层，且该未掺杂外延层包含有至少该第二半导体材料。随后于该未掺杂外延层上形成一掺杂外延层，以及于该掺杂外延层上形成一金属-半导体化合物层。
根据本发明所提供的半导体元件及其制作方法，于该外延结构上形成该三层结构，且此三层结构由下而上依序包含有该未掺杂外延层、该掺杂外延层、以及该金属-半导体化合物层。更重要的是，未掺杂外延层、该掺杂外延层、以及该金属-半导体化合物层都包含有至少该第二半导体材料，例如锗。通过此一三层结构的设置，可有效降低外延结构与后续形成的接触插塞之间的接触电阻，至终达到提升晶体管元件以及集成电路的整体效能的目的。
附图说明
图1至图8为本发明所提供的半导体元件的制作方法的一较佳实施例的示意图；
图9为本发明所提供的半导体元件的制作方法的一变化型的示意图。
主要元件符号说明
100 基底
102 隔离结构
110 晶体管元件
112 金属栅极
114 高介电常数栅极介电层
116 间隙壁
118 绝缘覆盖层
120 外延结构、第一结构
122 第二结构
124 盖层
130、132 介电层
134 开口
140 三层结构
142 未掺杂外延层
144 掺杂外延层
146 金属-半导体化合物层
150 离子注入制作工艺
152 热处理制作工艺
154 金属层
156 热处理制作工艺
158 金属层
160 金属接触插塞
T1 第一厚度
T2 第二厚度
T3 第三厚度
具体实施方式
请参阅图1至图8，图1至图8为本发明所提供的半导体元件的制作方法的一较佳实施例的示意图。如图1所示，首先提供一基底100，如一硅基底、含硅基底、或硅覆绝缘(silicon-on-insulator，以下简称为SOI)基底等，且基底100内形成有多个隔离结构102，隔离结构102可以是浅沟绝缘(shallow trench isolation，STI)，用以于基底100内定义出用以容置p型和/ 或n型场效晶体管(FET)元件的有源区域，并提供电性隔离。另外，本较佳实施例也可提供一半导体层，此一半导体层可为一鳍式场效晶体管(fin field effecttransistor，FinFET)的鳍片结构。熟悉该项技术的人士应知，鳍片结构的形成可利用蚀刻光刻暨蚀刻(photolithographic etching pattern，PEP)、多重曝光(multi patterning)等制作工艺，较佳可利用间隙壁自对准双图案法(spacer self-aligned double-patterning，SADP)，也就是侧壁影像转换(sidewall image transfer，SIT)等方式图案化一块硅(bulk silicon)基底或SOI基底表面的单晶硅层，而于块硅基底或SOI基底中形成一鱼鳍状的硅薄膜，此一硅薄膜即为本较佳实施例中的基底100。基底100上形成有多个晶体管元件110，在本发明的不同实施例中，晶体管元件110可以依需要为一p型晶体管元件，或为一n型晶体管元件。
在本较佳实施例中，可与取代栅极(replacement gate)制作工艺整合。故晶体管元件110分别包含一金属栅极112与一高介电常数(以下简称为high-k) 栅极介电层114。另外，在本发明的不同实施例中，金属栅极112可与前栅极介电层(high-k first)制作工艺或后栅极介电层(high-k last)制作工艺整合，且 high-k栅极介电层114与基底100之间可另设置一界面层(interfacial layer，IL) (图未示)。界面层可在基底100与high-k栅极介电层114之间提供一良好的界面。在本较佳实施例中，晶体管元件110为p型晶体管元件，故金属栅极112至少包含一满足p型晶体管所需功函数要求的功函数金属层(图未示) 与一填充金属层(图未示)。在本较佳实施例中，功函数金属层可包含任何满足p型金属栅极的功函数需求(功函数介于4.8eV与5.2eV之间)的金属材料，该些金属材料应为熟悉该项技术的人士所熟知，故于此不再赘述。此外，功函数金属层可以是单层结构或复合层结构。填充金属层为具有较佳填洞能力的单层金属层或复合金属层。除此之外，依不同的产品或制作工艺需要，金属栅极112还可包含一底部阻障层(bottom barrier layer)(图未示)、一蚀刻停止层(etch stop layer)(图未示)、和/或一顶部阻障层(top barrier layer)(图未示)。此外，金属栅极112的顶部表面上，设置有一绝缘覆盖层(insulating cap layer)118。在本发明的其他实施例中，由于绝缘覆盖层118的宽度较佳大于金属栅极112的宽度，因此在制作自对准接触插塞(self-aligned contact，SAC) 的接触插塞开口的制作工艺中，当蚀刻剂向下蚀刻至金属栅极112周围的上方时，绝缘覆盖层118可作为一坚硬的保护伞，用以保护其下方的金属栅极 112。
请继续参阅图1。根据本较佳实施例，晶体管元件110可更分别包含轻掺杂漏极(light doped drain，LDD)(图未示)、一形成在金属栅极112的侧壁上的间隙壁116、与一源极/漏极(图未示)。在本发明的其他实施例中，间隙壁116可为一如图1所示的复合膜层的结构，但不限于此。更重要的是，在本较佳实施例中，也可利用选择性外延成长(selectiveepitaxial growth，以下简称为SEG)方法来制作源极/漏极，以利用外延层与栅极通道硅之间的应力作用更改善电性表现。举例来说，在本较佳实施例中晶体管元件110为p型晶体管元件，故晶体管元件110之间，更可设置至少一个外延结构120。外延结构120包含有一第一半导体材料与一第二半导体材料，且该第二半导体材料的一晶格常数大于该第一半导体材料的一晶格常数。举例来说，第一半导体材料为硅，而第二半导体材料为锗。也就是说，本较佳实施例是利用包含有锗化硅(SiGe)的外延结构形成源极/漏极。此外，根据本发明的其他实施例，外延结构120的厚度可以是450埃
Figure BDA0000988135700000051
且外延结构120中第二半导体材料的浓度可介于32％与46％之间，但不限于此。另外，熟悉该项技术的人士应知，外延结构120可包含掺杂质，例如硼(boron，B)，且外延结构120中硼的浓度可以是6E20cm-3，但不限于此。此外如图1所示，外延结构120的高度可高于基底100的表面，但不限于此。
另外须注意的是，在本发明的实施例中，外延结构120可以是复合结构。举例来说，外延结构可包含一第一结构120与一第二结构122。第一结构120 作为主要的应力提供者，而第二结构122则用以降低第一结构120与周围材料的接触电阻。第二结构122也可包含第一半导体材料与第二半导体材料，故第二结构122也可为SiGe，且第二结构122中第二半导体材料的浓度较佳可低于第一结构120中第二半导体材料的浓度，以更避免第一结构120中发生排差缺陷(dislocation defect)。第二结构122的厚度可以介于
Figure BDA0000988135700000052
与
Figure BDA0000988135700000053
之间，但不限于此。另外，熟悉该项技术的人士应知，外延结构120可包含掺杂质，例如氟化硼(boronfluoride，BF)，但不限于此。
请仍然参阅图1。基底100表面上，更形成有介电层130、132。在本发明的实施例中，介电层130、132可作为内层介电层(inter layer dielectric，ILD) 层。且如图1所示，晶体管元件110埋设于介电层130之内。换句话说，介电层130环绕晶体管元件110，而介电层132则覆盖晶体管元件110与介电层130，但不限于此。
接下来请参阅图2。接下来，于介电层132、130内形成至少一开口134。值得注意的是，开口134形成于晶体管元件110之间，且外延结构120暴露于开口134的一底部。开口134可为一前述的自对准接触插塞(SAC)的接触插塞开口，但不限于此。此外，如图2所示，开口134的宽度，尤其是底部宽度，可小于外延结构120的宽度，但不限于此。
请参阅图3。在形成开口134之后，可利用SEG方法于开口134内形成一未掺杂外延层142，其包含有一第一高度T1，且第一高度T1约为
Figure BDA0000988135700000061
但不限于此。在本发明的一实施例中，未掺杂外延层142包含至少有第二半导体材料，即锗。值得注意的是，未掺杂外延层142中第二半导体材料包含一浓度，且该浓度可介于50％与100％之间。此外未掺杂外延层142也可包含第一半导体材料，即硅，且未掺杂外延层142中的硅浓度介于50％与0％间。另外须注意的是，未掺杂外延层142中第一半导体材料与第二半导体材料的浓度彼此相关。举例来说，当未掺杂外延层142中的锗浓度为100％时，硅浓度即为0％。此外，未掺杂半导体层142中第二半导体材料的浓度可以是固定的，或由下而上增加。举例来说，未掺杂半导体层142中的锗浓度可以固定为100％，或者由下而上自50％增加至100％。由此可知，相对于其下的外延结构120，未掺杂外延层142为一高浓度锗层。
请参阅图4。在形成未掺杂外延层142之后，进行一离子注入制作工艺 150与一热处理制作工艺152。离子注入制作工艺150用以将掺杂质注入进入未掺杂外延层142之内，而热处理制作工艺152则用以使掺杂质扩散，而于未掺杂外延层142内形成一掺杂外延层144。在本发明的实施例中，可将硼掺杂进入未掺杂外延层142之内，且硼的浓度大于1E20cm-3，但不限于此。热处理制作工艺152可以是任何适合热处理方法，例如动态表面热处理(dynamicsurface anneal，DSA)，但不限于此。此外值得注意的是，由于掺杂质由掺杂进入的表面向下扩散，因此最终形成的掺杂外延层144也可视为是形成在未掺杂外延层142之上，如图4所示。是以，未掺杂外延层142在热处理制作工艺152之前包含有前述的第一厚度T1，而在热处理制作工艺152 之后则包含有一第二厚度T2，且该第二厚度T2小于第一厚度T1。又或者，掺杂外延层144具有一第三厚度T3，而掺杂外延层144的第三厚度T3与未掺杂外延层142的第二厚度T2的和等于未掺杂外延层142的第一厚度T1。在本发明的一实施例中，掺杂外延层144的第三厚度T3举例来说可大于
Figure BDA0000988135700000063
但小于
Figure BDA0000988135700000062
请参阅图5。在形成掺杂外延层144之后，在基底100上，即介电层132 与开口134之内的掺杂外延层144上形成一金属层154。在本发明的实施例中，金属层154包含有钛/氮化钛(Ti/TiN)，且可为一双层(dual-layered)结构，但不限于此。
请参阅图6。在形成金属层154之后，进行一热处理制作工艺156，以形成一金属-半导体化合物层146。值得注意的是，在热处理制作工艺156中，金属层154中的金属与掺杂外延层144中的锗反应，故金属-半导体化合物层146可以是一金属锗化物(metal germanide)层，例如一锗化钛层(titanium germanide，TiGe)。至此，本较佳实施例于外延结构120上形成一三层 (tri-layered)结构140，其包含有金属-半导体化合物层146、未掺杂外延层142、以及夹设于金属-半导体化合物层146与未掺杂外延层142之间的掺杂外延层144，且此三层结构140的一宽度，尤其是其底部的宽度，小于外延结构 120的宽度，如图6所示。
请参阅图7。在形成金属-半导体化合物层146之后，即形成三层结构 140之后，于开口134内填入一金属层158，例如一钨(tungsten，W)层，但熟悉该项技术的人士应知不限于此。
请参阅图8。接下来，进行一平坦化制作工艺，利如一化学机械研磨 (chemicalmechanical polishing，CMP)制作工艺，并通过平坦化制作工艺移除多余的金属层158，而于各开口134内分别形成一金属接触插塞160，且金属接触插塞160形成于介电层130/132内，且设置于晶体管元件110之间。如图8所示，在金属接触插塞160的侧壁与介电层130/132之间，以及金属接触插塞160与晶体管元件110之间，仍留有金属层154。更重要的是，三层结构140夹设于金属接触插塞160与外延结构120之间。
另外，请参阅图9，图9为本发明所提供的半导体元件的制作方法的一变化型的示意图。在本变化型中，与前述实施例相同的组成元件包含相同的符号说明，且可利用相同的制作工艺完成，并可具有相同的材料选择，故该些相同的组成元件的相关细节不再予以赘述。本变化型与前述实施例不同之处在于，在外延结构120与三层结构140之间，可更设置一盖层(cap layer) 124，其厚度可介于
Figure BDA0000988135700000071
与
Figure BDA0000988135700000072
之间。盖层124可包含前述的第一半导体材料与第二半导体材料，故盖层124可为一SiGe层。此外，盖层124中，第二半导体材料的一浓度可以是25％，但不限于此。盖层124可具有前述的掺杂质，即硼。SiGe盖层124中硼的掺杂浓度可以是8E20cm-3，但不限于此。
根据本发明所提供的半导体元件及其制作方法，于外延结构与金属插塞结构之间形成一三层结构，且此三层结构由下而上依序包含有未掺杂外延层、掺杂外延层、以及金属-半导体化合物层。更重要的是，未掺杂外延层、掺杂外延层、以及金属-半导体化合物层都包含有高浓度的第二半导体材料，即包含高浓度锗。因此，通过此一三层结构的设置，可有效降低外延结构与金属接触插塞之间的接触电阻，至终达到提升晶体管元件以及集成电路的整体效能的目的。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (19)

1.一种半导体元件，包含有：
基底，包含有多个晶体管元件，形成于该基底上；
至少一外延结构，设置于该多个晶体管元件之间，该外延结构包含有第一半导体材料与第二半导体材料，且该第二半导体材料的一晶格常数大于该第一半导体材料的一晶格常数；以及
三层结构，设置于该外延结构之上，且该三层结构包含有：
未掺杂外延层，包含有至少该第二半导体材料，该未掺杂半导体层的该第二半导体材料的浓度由下而上增加；
金属-半导体化合物层，包含有至少该第二半导体材料；以及
掺杂外延层，夹设于该未掺杂外延层与该金属-半导体化合物层之间，且该掺杂外延层包含有至少该第二半导体材料，
其中，该未掺杂外延层中的第二半导体材料的浓度高于该外延结构中的第二半导体材料的浓度，且该三层结构中的第二半导体材料的浓度由下而上增加。
2.如权利要求1所述的半导体元件，其中该第一半导体材料为硅，该第二半导体材料为锗。
3.如权利要求2所述的半导体元件，其中该三层结构中的该未掺杂半导体层的该第二半导体材料的该浓度介于50％与100％之间。
4.如权利要求3所述的半导体元件，其中该未掺杂外延层还包含该第一半导体材料，且该第一半导体材料的一浓度介于0％与50％之间。
5.如权利要求2所述的半导体元件，其中该三层结构的该掺杂半导体层至少包含有硼(boron，B)。
6.如权利要求2所述的半导体元件，其中该三层结构的该金属-半导体层包含有金属锗化物(metal germanide)。
7.如权利要求1所述的半导体元件，其中该三层结构的一宽度小于该外延结构的一宽度。
8.如权利要求1所述的半导体元件，还包含介电层，形成于该基底上。
9.如权利要求8所述的半导体元件，还包含至少一金属接触插塞，形成于该介电层内，该金属接触插塞设置于该多个晶体管元件之间，且该三层结构夹设于该金属接触插塞与该外延结构之间。
10.如权利要求9所述的半导体元件，还包含金属层，形成于该金属接触插塞的侧壁与该介电层之间，以及形成于该金属接触插塞的侧壁与该多个晶体管元件之间。
11.如权利要求10所述的半导体元件，其中该金属层包含有钛/氮化钛(Ti/TiN)。
12.一种半导体元件的制作方法，包含有：
提供一基底，该基底上形成有多个晶体管元件、一介电层、以及至少一外延结构，该外延结构设置于该多个晶体管元件之间，且包含有第一半导体材料与第二半导体材料，该第二半导体材料的一晶格结构大于该第一半导体材料的一晶格结构；
于该多个晶体管元件之间的该介电层内形成至少一开口，且该外延结构暴露于该开口的一底部；
于该开口内形成一未掺杂外延层，且该未掺杂外延层包含有至少该第二半导体材料，该未掺杂半导体层的该第二半导体材料的浓度由下而上增加，且该未掺杂外延层中的第二半导体材料的浓度高于该外延结构中的第二半导体材料的浓度；
于该未掺杂外延层上形成一掺杂外延层；以及
于该掺杂外延层上形成一金属-半导体化合物层。
13.如权利要求12所述的半导体元件的制作方法，其中该未掺杂外延层的该第二半导体材料包含一浓度，且该浓度介于50％与100％之间。
14.如权利要求12所述的半导体元件的制作方法，其中形成该掺杂外延层的步骤还包含：
进行一离子注入制作工艺，以将掺杂质注入进入该未掺杂外延层；以及
进行一热处理制作工艺，以形成该掺杂外延层。
15.如权利要求14所述的半导体元件的制作方法，其中该未掺杂外延层在该热处理制作工艺之前包含有第一厚度，而在该热处理制作工艺之后包含有第二厚度，且该第二厚度小于该第一厚度。
16.如权利要求14所述的半导体元件的制作方法，其中该掺杂质包含硼。
17.如权利要求12所述的半导体元件的制作方法，其中形成该金属-半导体化合物层的步骤还包含：
在该掺杂外延层上形成一金属层；以及
进行一热处理制作工艺，以形成该金属-半导体化合物层。
18.如权利要求12所述的半导体元件的制作方法，其中该开口的宽度小于该外延结构的宽度。
19.如权利要求12所述的半导体元件的制作方法，还包含于该开口内形成一金属接触插塞的步骤，进行于形成该金属-半导体化合物层之后。
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