CN102201343A - 纳米mos器件制备方法及纳米mos器件 - Google Patents

纳米mos器件制备方法及纳米mos器件 Download PDF

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CN102201343A
CN102201343A CN201110106317XA CN201110106317A CN102201343A CN 102201343 A CN102201343 A CN 102201343A CN 201110106317X A CN201110106317X A CN 201110106317XA CN 201110106317 A CN201110106317 A CN 201110106317A CN 102201343 A CN102201343 A CN 102201343A
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metal
semiconductor layer
nanometer mos
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吴东平
胡成
朱伦
朱志炜
张世理
张卫
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Fudan University
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Fudan University
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Priority to US13/519,315 priority patent/US20140034955A1/en
Priority to PCT/CN2011/081565 priority patent/WO2012146018A1/zh
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Abstract

本发明公开了一种纳米MOS器件的制备方法，其制备的栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能；并且该方法是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层的侧壁表面扩散，经过退火后，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线(即金属栅)，而不需要利用高分辨率的光刻技术来形成金属半导体化合物纳米线，因而大大节约了成本；同时，还公开了一种纳米MOS器件，其栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能。

Description

纳米MOS器件制备方法及纳米MOS器件
技术领域
本发明涉及半导体工艺技术领域，尤其涉及一种纳米MOS器件制备方法及纳米MOS器件。
背景技术
自从第一个晶体管发明以来，经过几十年的飞速发展，晶体管的横向和纵向尺寸都迅速缩小。据国际半导体技术蓝图(ITRS，International TechnologyRoadmap for Semiconductors)在2004年的预测，到2018年晶体管的特征尺寸将达到7nm。尺寸的持续缩小使晶体管的性能(速度)不断提高，也使得我们能够在相同面积的芯片上集成更多的器件，集成电路的功能越来越强，同时也降低了单位功能成本。
然而器件特征尺寸的不断减小也带来了一系列的挑战。由于传统的MOS器件的栅极大多采用多晶硅，而当传统的多晶硅栅晶体管的尺寸缩小到一定程度后，将出现多晶硅栅耗尽效应(PDE，Poly Depletion Effect)，从而阻碍晶体管性能的提升。所谓多晶硅栅耗尽效应，是指当晶体管处于导通状态时，在多晶硅栅极中形成耗尽层，由于该耗尽层和栅氧化层之间是叠加关系，因此从电性能角度观察到的栅氧化层的有效厚度为栅氧化层实际厚度与耗尽层厚度之和，从而使得栅氧化层的有效厚度增加，导致晶体管导通电流减小。
为了解决上述的多晶硅栅耗尽效应问题，金属栅应运而生。所谓金属栅是指用金属来作为MOS晶体管的栅极。由于金属具有高的电导，因此金属栅能避免栅极耗尽效应，从而使MOS器件具有更好的性能。
但是，目前纳米尺度的金属栅的制备还存在一定的技术难点。这是因为目前金属栅能达到的最小尺寸主要依赖于光刻技术，而光刻系统的分辨率目前还达不到几纳米的程度，并且光刻系统价格昂贵，工艺成本太高。
因此，如何制备出纳米级的金属栅及MOS器件，已成为目前业界亟需解决的技术问题。
发明内容
本发明的目的在于提供一种纳米MOS器件制备方法及纳米MOS器件，以减小MOS器件的特征尺寸，提高MOS器件的性能。
为解决上述问题，本发明提出一种纳米MOS器件的制备方法，该方法包括如下步骤：
(1)提供半导体衬底；
(2)在所述半导体衬底上制备栅氧化层；
(3)在所述栅氧化层上制备栅极，并在所述栅极的两侧形成侧墙，其中，所述栅极为金属半导体化合物纳米线；
(4)进行源漏注入，在所述半导体衬底内形成源漏区；
其中，步骤(3)具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀，去掉两侧的绝缘层以及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模，对所述栅氧化层进行刻蚀；以及
在所述金属半导体化合物纳米线的两侧形成侧墙。
可选的，所述栅极的长度为2～11nm。
可选的，所述金属薄膜是通过PVD法沉积在所述多晶半导体层两侧的侧壁上的。
可选的，在所述PVD法沉积金属薄膜的过程中，将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层上加第一偏压。
可选的，所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的。
可选的，所述第一偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
可选的，所述第二偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
可选的，所述栅氧化层为高K介质层。
可选的，所述半导体衬底为硅或绝缘层上硅，所述多晶半导体层为多晶硅层，所述金属半导体化合物纳米线为金属硅化物纳米线。
可选的，所述半导体衬底为锗或绝缘层上锗，所述多晶半导体层为多晶锗层，所述金属半导体化合物纳米线为金属锗化物纳米线。
可选的，所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生成，其中，所述金属为镍、钴、钛、镱中的任一种，或镍、钴、钛、镱中的任一种并掺入铂。
可选的，所述金属中还掺入了钨和/或钼。
可选的，在所述多晶半导体层两侧的侧壁上沉积金属薄膜时的衬底温度为0～300℃。
可选的，所述退火的温度为200～900℃。
同时，为解决上述问题，本发明还提出一种利用上述纳米MOS器件的制备方法得到的纳米MOS器件，所述纳米MOS器件包括：
半导体衬底；
栅氧化层，形成于所述半导体衬底上；
栅极，形成于所述栅氧化层上，并且所述栅极的两侧形成有侧墙；以及
源漏区，形成于所述栅极两侧的所述半导体衬底内。
可选的，所述栅极的长度为2～11nm。
可选的，所述栅氧化层为高K介质层。
可选的，所述半导体衬底为硅或绝缘层上硅，所述金属半导体化合物纳米线为金属硅化物纳米线。
可选的，所述半导体衬底为锗或绝缘层上锗，所述金属半导体化合物纳米线为金属锗化物纳米线。
与现有技术相比，本发明提供的纳米MOS器件的制备方法，其制备的栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能；并且该方法是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层的侧壁表面扩散，经过退火后，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线(即金属栅)，而不需要利用高分辨率的光刻技术来形成金属半导体化合物纳米线，因而大大节约了成本。
与现有技术相比，本发明提供的纳米MOS器件，其栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能。
附图说明
图1为本发明实施例提供的纳米MOS器件的制备方法的流程图；
图2A至图2J为本发明实施例提供的纳米MOS器件的制备方法的各步骤对应的器件剖面图；
图3为本发明实施例提供的纳米MOS器件的剖面图。
具体实施方式
以下结合附图和具体实施例对本发明提出的纳米MOS器件及其制备方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用于方便、明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于，提供一种纳米MOS器件的制备方法，其制备的栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能；并且该方法是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层的侧壁表面扩散，经过退火后，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线(即金属栅)，而不需要利用高分辨率的光刻技术来形成金属半导体化合物纳米线，因而大大节约了成本；同时，还提供一种纳米MOS器件，其栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能。
请参考图1，以及图2A至图2J，其中，图1为本发明实施例提供的纳米MOS器件的制备方法的流程图，图2A至图2J为本发明实施例提供的纳米MOS器件的制备方法的各步骤对应的器件剖面图。结合图1，以及图2A至图2J，本发明实施例提供的纳米MOS器件100的制备方法包括如下步骤：
S101、提供半导体衬底101；
S102、在所述半导体衬底101上制备栅氧化层102；其中，所述栅氧化层102为高K介质层；
S103、在所述栅氧化层102上制备栅极，并在所述栅极的两侧形成侧墙104；其中，所述栅极为金属半导体化合物纳米线103；具体地，在所述栅氧化层102上制备栅极包括以下步骤：
在所述栅氧化层102上依次形成多晶半导体层110以及绝缘层120，如图2A所示；
依次对所述绝缘层120以及所述多晶半导体层110进行刻蚀，去掉两侧的绝缘层120以及多晶半导体层110，如图2B所示；
在所述多晶半导体层110两侧的侧壁上沉积金属薄膜130，如图2C所示；所述金属薄膜130中的金属向所述多晶半导体层110扩散；
去除所述多晶半导体层110侧壁表面剩余的金属薄膜130，如图2D所示，所述金属扩散至所述多晶半导体层110表面后，在所述多晶半导体层110的表面形成含有金属的半导体薄层140；
对所述多晶半导体层110进行退火，在所述多晶半导体层110的侧壁表面形成金属半导体化合物纳米线103，如图2E所示；
去除所述绝缘层120及所述多晶半导体层110，如图2F所示；
以所述金属半导体化合物纳米线103为掩模，对所述栅氧化层102进行刻蚀；刻蚀后的器件剖面图如图2G所示；以及
在所述金属半导体化合物纳米线103的两侧形成侧墙104，如图2H所示。
S104、进行源漏注入，在所述半导体衬底101内形成源漏区，具体地，在所述栅极两侧的半导体衬底101内形成源区106以及漏区107，完成纳米MOS器件100的制备，如图2I所示。
进一步地，所述栅极的长度为2～11nm。
进一步地，所述金属薄膜130是通过PVD法沉积在所述多晶半导体层110两侧的侧壁上的。并且，在所述PVD法沉积金属薄膜130的过程中，还可以选择将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层110上加第一偏压；其中，所述将靶材部分离化成离子状态可通过在所述靶材上加第二偏压实现；并且，所述第一偏压为直流偏压、交流偏压或脉冲偏压中的任一种，所述第二偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
通过将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层110上加第一偏压，使得所述金属离子加速向所述多晶半导体层110的侧壁运动，并进入所述多晶半导体层110的侧壁，从而使得扩散至所述多晶半导体层110的侧壁的金属离子更多，扩散深度更深，因而最终形成的金属半导体化合物纳米线103的宽度加宽，从而使得本发明实施例提供的纳米MOS器件100的栅极长度加长，特征尺寸加大；因此本发明实施例提供的纳米MOS器件100的栅极长度是可调的。具体地，所述纳米MOS器件100的栅极长度可为2～11nm。
需要说明的是，在本发明的一个具体实施例中，所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的，然而本发明并不以此为限，任何使得靶材的一部分离化成离子状态的方式都在本发明的保护范围之内。
进一步地，所述半导体衬底101为硅或绝缘层上硅，所述多晶半导体层110为多晶硅层，所述金属半导体化合物纳米线103为金属硅化物纳米线。
进一步地，所述半导体衬底101为锗或绝缘层上锗，所述多晶半导体层110为多晶锗层，所述金属半导体化合物纳米线103为金属锗化物纳米线。
需要说明的是，在本发明的一个具体实施例中，所述半导体衬底101可为硅或绝缘层上硅、以及锗或绝缘层上锗，然而应该认识到，本发明并不以此为限，所述半导体衬底101还可为其它类型的半导体衬底，如砷化镓等三五族半导体衬底。
进一步地，所述金属半导体化合物纳米线103由金属与所述多晶半导体层110反应生成，其中，所述金属为镍、钴、钛、镱中的任一种，或镍、钴、钛、镱中的任一种并掺入铂；掺入铂是因为纯的一硅化镍在高温条件下稳定性差，或出现薄膜厚度变得不均匀并结块，或生成电阻率高的二硅化镍NiSi2，严重影响器件的性能，因此，为了减慢硅化镍的生长速度以及防止硅化镍薄层遇到高温时发生结块或形成二硅化镍，可以在镍中掺入一定比例的铂；其它金属中掺铂作类似解释。
进一步地，所述金属中还掺入了钨和/或钼；以进一步控制硅化镍或掺铂硅化镍的生长和镍/铂的扩散，并增加硅化镍或掺铂硅化镍的稳定性；其它金属中掺钨和/或钼作类似解释。
进一步地，在所述多晶半导体层110两侧的侧壁上沉积金属薄膜130时的衬底温度为0～300℃；这是因为对金属镍来说，沉积温度超过300℃会造成在超量的镍扩散的同时镍会和多晶半导体层110(例如多晶硅)直接反应形成硅化镍，导致厚度控制的失败；在该特定温度下，镍会经多晶硅侧壁表面向多晶硅侧壁进行扩散，这种扩散具有自饱和特性：镍向多晶硅侧壁进行扩散仅在硅的表面薄层中发生，形成一定硅/镍原子比例的薄层镍，该薄层镍的厚度和淀积时的衬底温度有关，温度越高，该薄层镍的厚度也越大，在室温下，该薄层镍的等效镍厚度为2纳米左右。
进一步地，所述退火的温度为200～900℃。
由于本发明实施例提供的金属半导体化合物纳米线103是通过在多晶半导体层110两侧的侧壁表面沉积金属薄膜130，所述金属薄膜130中的金属向所述多晶半导体层110的侧壁表面扩散，经过退火后，在所述多晶半导体层110的侧壁表面形成金属半导体化合物纳米线103(即金属栅)，而不需要利用高分辨率的光刻技术来形成如此细的金属半导体化合物纳米线103，因而大大节约了成本。
需要说明的是，在本发明的一个具体实施例中，利用上述方法形成了两个纳米MOS器件100，然而应该认识到，由于一般实际应用中的晶体管可能是多指栅(multi-finger)结构，因而利用本发明提供的方法也可以只形成一个晶体管200，如图2J所示，即利用本发明提供的方法形成的两个金属半导体化合物纳米线203共同构成MOS晶体管200的栅极，所述栅极位于栅氧化层202上，且所述栅极的两侧形成有侧墙204，在所述栅极两侧的半导体衬底201内形成源区205以及漏区206，其中，所述两个金属半导体化合物纳米线203通过一电极207连接在一起。
请参考图3，图3为本发明实施例提供的纳米MOS器件的剖面图，如图3所示，本发明实施例提供的纳米MOS器件100的栅极为金属栅，且所述栅极的长度为2～11nm；其中，所述金属栅为金属半导体化合物纳米线103。具体地，本发明实施例提供的纳米MOS器件100包括：
半导体衬底101；
栅氧化层102，形成于所述半导体衬底101上；其中，所述栅氧化层102为高K介质层；
栅极，形成于所述栅氧化层102上，并且所述栅极的两侧形成有侧墙104；以及
源漏区，形成于所述栅极两侧的所述半导体衬底101内；具体地，包括形成于所述栅极两侧的所述半导体衬底101内的源区105以及漏区106。
需说明的是，由于本发明实施例提供的纳米MOS器件，其栅极的长度只有2～11纳米，根据集成电路的按等比例缩小规则(scaling rule)，该纳米MOS器件的其它参数值也应相应缩小，例如所述源区105以及漏区106应为超浅源区及超浅漏区。
进一步地，所述半导体衬底101为硅或绝缘层上硅，所述金属半导体化合物纳米线为金属硅化物纳米线。
进一步地，所述半导体衬底101为锗或绝缘层上锗，所述金属半导体化合物纳米线为金属锗化物纳米线。
需要说明的是，在本发明的一个具体实施例中，所述半导体衬底101可为硅或绝缘层上硅、以及锗或绝缘层上锗，然而应该认识到，本发明并不以此为限，所述半导体衬底101还可为其它类型的半导体衬底，如砷化镓等三五族半导体衬底。
综上所述，本发明提供了一种纳米MOS器件的制备方法，其制备的栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能；并且该方法是通过在多晶半导体层两侧的侧壁表面沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层的侧壁表面扩散，经过退火后，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线(即金属栅)，而不需要利用高分辨率的光刻技术来形成金属半导体化合物纳米线，因而大大节约了成本；同时，还提供了一种纳米MOS器件，其栅极为金属栅，因而可避免多晶栅极的耗尽效应，提高MOS器件的性能。
显然，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (19)

1.一种纳米MOS器件的制备方法，其特征在于，包括如下步骤：
(1)提供半导体衬底；
(2)在所述半导体衬底上制备栅氧化层；
(3)在所述栅氧化层上制备栅极，并在所述栅极的两侧形成侧墙，其中，所述栅极为金属半导体化合物纳米线；
(4)进行源漏注入，在所述半导体衬底内形成源漏区；
其中，步骤(3)具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀，去掉两侧的绝缘层以及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜，所述金属薄膜中的金属向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火，在所述多晶半导体层的侧壁表面形成金属半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模，对所述栅氧化层进行刻蚀；以及
在所述金属半导体化合物纳米线的两侧形成侧墙。
2.如权利要求1所述的纳米MOS器件的制备方法，其特征在于，所述栅极的长度为2～11nm。
3.如权利要求1所述的纳米MOS器件的制备方法，其特征在于，所述金属薄膜是通过PVD法沉积在所述多晶半导体层两侧的侧壁上的。
4.如权利要求3所述的纳米MOS器件的制备方法，其特征在于，在所述PVD法沉积金属薄膜的过程中，将靶材部分离化成离子状态，使其产生金属离子，并在所述多晶半导体层上加第一偏压。
5.如权利要求4所述的纳米MOS器件的制备方法，其特征在于，所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的。
6.如权利要求5所述的纳米MOS器件的制备方法，其特征在于，所述第一偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
7.如权利要求5所述的纳米MOS器件的制备方法，其特征在于，所述第二偏压为直流偏压、交流偏压或脉冲偏压中的任一种。
8.如权利要求1所述的纳米MOS器件的制备方法，其特征在于，所述栅氧化层为高K介质层。
9.如权利要求8所述的纳米MOS器件的制备方法，其特征在于，所述半导体衬底为硅或绝缘层上硅，所述多晶半导体层为多晶硅层，所述金属半导体化合物纳米线为金属硅化物纳米线。
10.如权利要求8所述的纳米MOS器件的制备方法，其特征在于，所述半导体衬底为锗或绝缘层上锗，所述多晶半导体层为多晶锗层，所述金属半导体化合物纳米线为金属锗化物纳米线。
11.如权利要求9或10所述的纳米MOS器件的制备方法，其特征在于，所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生成，其中，所述金属为镍、钴、钛、镱中的任一种，或镍、钴、钛、镱中的任一种并掺入铂。
12.如权利要求11所述的纳米MOS器件的制备方法，其特征在于，所述金属中还掺入了钨和/或钼。
13.如权利要求1所述的纳米MOS器件的制备方法，其特征在于，在所述多晶半导体层两侧的侧壁上沉积金属薄膜时的衬底温度为0～300℃。
14.如权利要求1所述的纳米MOS器件的制备方法，其特征在于，所述退火的温度为200～900℃。
15.一种根据权利要求1所述的纳米MOS器件的制备方法得到的纳米MOS器件，其特征在于，所述纳米MOS器件包括：
半导体衬底；
栅氧化层，形成于所述半导体衬底上；
栅极，形成于所述栅氧化层上，并且所述栅极的两侧形成有侧墙；以及
源漏区，形成于所述栅极两侧的所述半导体衬底内。
16.如权利要求15所述的纳米MOS器件，其特征在于，所述栅极的长度为2～11nm。
17.如权利要求15所述的纳米MOS器件，其特征在于，所述栅氧化层为高K介质层。
18.如权利要求17所述的纳米MOS器件，其特征在于，所述半导体衬底为硅或绝缘层上硅，所述金属半导体化合物纳米线为金属硅化物纳米线。
19.如权利要求17所述的纳米MOS器件，其特征在于，所述半导体衬底为锗或绝缘层上锗，所述金属半导体化合物纳米线为金属锗化物纳米线。
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