TW201724215A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201724215A
TW201724215A TW105128816A TW105128816A TW201724215A TW 201724215 A TW201724215 A TW 201724215A TW 105128816 A TW105128816 A TW 105128816A TW 105128816 A TW105128816 A TW 105128816A TW 201724215 A TW201724215 A TW 201724215A
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Taiwan
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gate
layer
gate stack
dielectric layer
isolation
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TW105128816A
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English (en)
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汪柏澍
陳建茂
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台灣積體電路製造股份有限公司
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Publication of TW201724215A publication Critical patent/TW201724215A/zh

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本揭示揭露一種半導體裝置以及其製造方法。此半導體裝置包含：半導體基板，其具有由複數個隔離特徵定義出來的主動區；閘極堆疊位於主動區上並延伸橫跨隔離特徵的一部分上，其中閘極堆疊包含閘極介電層位於主動區上及部分之隔離特徵上，以及閘電極位於閘極介電層上；以及保護密封層，包含垂直部分位於閘極堆疊襯層的側壁以及水平部分延伸至隔離特徵的上表面，其中水平部分在上視圖中係環繞主動區外之部分的閘極堆疊。

Description

半導體裝置及其製造方法
本發明實施例係關於一種半導體裝置。
積體電路(IC)產業經歷了快速的發展。IC材料及設計技術的進步創造出IC世代，其中每一代皆具有比上一代更微小和更複雜的電路。然而，這些進步增加了IC製程和製造的複雜性，並且為了實現這些進步，需要在IC製程及製造中有類似的發展。當半導體裝置例如金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor，MOSFET)通過各種技術節點按照比例縮小的同時，已經採用若干策略來改善裝置性能，例如使用高介電常數(high-k，HK)介電材料及金屬閘電極結構(metal gate，MG)，應變工程(strain engineering)，3-D閘極電晶體以及超薄體(ultra-thin body，UTB)。儘管製造MOSFET裝置的現有方法以實質上足以應用於其預期的目的，但是就各方面來說並不是完全令人滿意。繼續尋找具有改善可靠性及增加性能的改良製造方法。
根據本發明實施例之一態樣，半導體裝置包含：一半導體基板，其具有由一複數個隔離特徵定義而成的一主動區；一閘極堆疊延伸橫跨該主動區並位於該隔離特徵的一部分上，其中該閘極堆疊包含一閘極介電層位於該主動區上及部分之該隔離特徵上，以及一閘電極位於該閘極介電層上；以及一保護密封層，包含一垂直部分位於該閘極堆疊襯層的側壁以及一水平部分延伸至該隔離特徵的上表面，其中該水平部分在一上視圖中係環繞該主動區外之該一部分的閘極堆疊。
100‧‧‧方法
110、120、130、140、150、160‧‧‧操作步驟
200‧‧‧半導體裝置
210‧‧‧半導體基板
220‧‧‧主動區
230‧‧‧隔離特徵
240‧‧‧閘極堆疊
250‧‧‧假性閘極
260‧‧‧保護密封層
260’‧‧‧密封材料
2601‧‧‧垂直部分
2602‧‧‧水平部分
280‧‧‧閘電極
290‧‧‧層間介電層
300‧‧‧溝槽式閘極
當結合隨附圖式進行閱讀時，本揭示之詳細描述將能被充分地理解。應注意，根據業界標準實務，各特徵並非按比例繪製且僅用於圖示目的。事實上，出於論述清晰之目的，可任意增加或減小各特徵之尺寸。
第1圖繪示了根據本揭示內容之一實施例，一種製造半導體裝置之方法的流程示意圖。
第2圖至第9圖繪示了根據本揭示內容之實施例，一種製造半導體裝置之各階段的結構剖面示意圖。
第10圖繪示了本揭示內容之實施例，一種半導體裝置的上視示意圖。
應理解，以下揭示內容提供許多不同實施例或實例，以便實施本揭示之不同特徵。下文描述組件及排列之特定實施例或實例以簡化本揭示。當然，此等實例僅為示例性且並不欲為限制性。舉例而言，元件之尺寸並不受限於所揭示之範圍或值，但可取決於製程條件及/或裝置之所欲特性。此外，以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間插入形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。為了簡明性及清晰性，可以不同尺度任意繪製各特徵。
另外，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示之一元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含使用或操作中裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向上)且因此可同樣解讀本文所使用之空間相對性描述詞。
在具體說明本發明實施例之前，通常會敘述本發明實施例之某些特徵及態樣。具體來說，本揭示一種半導體裝置及其製造方法，以提供簡單以及節省成本的製作流程即可據以實施一種保護密封層，從而避免隔離特徵因濕式蝕刻劑產生損耗，進而滲入至閘極介電層中例如高介電常數 (high-k,HK)介電層，因此可免除閘極介電層在蝕刻製程中造成的毀損。
第1圖繪示了本發明實施例之一種半導體裝置的製造方法100，根據本揭示之一態樣，一種半導體裝置具有一保護密封層，其能夠避免一閘極介電層在蝕刻製程中受到損壞。第2圖至第8圖係繪示本發明實施例之一種半導體裝置200在各個製造階段的結構剖面圖。半導體裝置200及其製造方法100可參照第1圖至第9圖互相搭配描述。可以理解的是，可在方法100之前、期間及之後可提供額外操作，且在方法之額外實施方式中，下文所描述之一些操作可被替換或刪除。
參照第1圖，其製造半導體裝置200的方法100始於步驟110，提供一具有主動區220及複數個隔離特徵230之半導體基板210，進而得到如第2圖所示之結構。在一些實施例中，半導體基板210可以是示例性的塊狀矽基板(bulk silicon substrate)，又或者，半導體基板210可以是示例性的包含元素半導體，例如晶體結構中的矽或鍺；化合物半導體例如為矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；或及其組合。半導體基板210可以更進一步示例性的包含各種主動區220，例如由N型金屬氧化物半導體電晶體(N-type metal-oxide-semiconductor transistor)裝置配置的區域以及由P型金屬氧化物半導體電晶體(P-type metal-oxide-semiconductor transistor)裝置配置的區域。此外，半導體基板210亦可以示例性的摻 雜P型或N型雜質。摻雜區可以摻雜P型雜質例如硼或BF2；N型雜質例如磷或砷；或及其組合。依據習知技術例如P型井(P-type wells)或N型井(N-type wells)所熟知的設計需求，半導體基板210可以示例性的包含各種摻雜區。摻雜區可以直接形成於半導體基板210上、P型井結構中、N型井結構中、雙井構中或使用凸起結構(raised structure)。更進一步來說，此半導體基板210可以增強應變性能。舉例來說，磊晶層可以包含不同於塊狀半導體的材料，例如覆蓋塊體矽的矽鍺層或覆蓋藉由包含選擇性磊晶成長(selective epitaxial growth，SEG)流程之塊體矽鍺的矽層。再者，半導體基板210可以示例性的包含絕緣底半導體(semiconductor-on-insulator，SOI)結構例如深埋介電層(buried dielectric layer)。又或者，半導體基板可以示例性的包含深埋介電層例如深埋氧化物(buried oxide，BOX)層，比如通過一種稱為氧離子植入分離(separation by implantation of oxygen，SIMOX)技術、晶圓接合(wafer bonding)、SEG或其他合適的方法而形成。事實上，各個實施例可以包含多種基底結構及材料的任何一種。
在一些實施例中，半導體基板210也示例性的包含各種隔離特徵230，例如淺溝槽隔離(shallow trench isolation，STI)形成於半導體基板210中用以定義及隔開各個裝置，例如為主動區220。形成隔離特徵230可以示例性的包含在半導體基板中蝕刻一溝槽並且使用絕緣材料例如氧化矽、氮化矽或氮氧化矽將溝槽填滿。被填充的溝槽可 以具有多層結構例如具有填充氮化矽的溝槽的熱氧化物內墊層。在一些實施例中，隔離特徵230可以使用以下示例性的製程順序生成例如：生成襯墊氧化層(pad oxide)，形成低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)的氮化物層，使用光阻劑及光罩於隔離特徵230上圖案化形成開口，於半導體基板中蝕刻出一溝槽，可選擇性生成熱氧化物溝槽內墊層以改善溝槽的介面，使用CVD氧化物填充溝槽，以及使用化學機械平坦化(chemical mechanical planarization，CMP)以移除過多的介電金屬層。
在方法100中進行步驟120以及步驟130，其形成複數個閘極堆疊於半導體基板上，以獲得如第3圖及第4圖所示之結構。在一些實施例中，閘極堆疊240、250延伸橫跨主動區220並位於隔離特徵230的一部分上。在一些實施例中，閘極堆疊包含閘極介電層240位於該主動區220上及部分之該隔離特徵230上，以及假性閘極250位於閘極介電層240上。在一些實施例中，閘極介電層240可以示例性包含選自以下群組的高介電常數(high-k，HK)介電材料：氧化鉿、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鉿-氧化鋁(HfO2-Al2O3)合金，及其組合。在一些實施例中，閘極介電層240可以示例性的藉由合適的製程例如ALD而形成。其他可以形成高介電常數介電材料層的方法包含金屬有機化學氣相沉積(metal organic chemical vapor deposition，MOCVD)、物理氣 相沉積(physical vapor deposition，PVD)、UV-臭氧氧化(UV-ozone oxidation)或分子束外延(molecular beam epitaxy，MBE)。在一些實施例中，介面層(未示出)可以形成於半導體基板210上。介面層可以包含由合適技術所形成的氧化矽，例如原子層沉積(atomic layer deposition，ALD)、熱氧化或UV-臭氧氧化。在一些實施例中，閘極介電層240可以示例性的形成於主動區220上及部分的隔離特徵230上，然後假性閘極250形成於閘極介電層上。在一些實施例中，於步驟130中，可以示例性的在高介電常數/金屬閘極的最後製程中製造半導體裝置200。在一些實施例中，在高介電常數/金屬閘極的最後製程中，首先形成如第4圖所示之假性閘極250，接著其可以被移除及置換成金屬閘極，此過程將詳述如後。
在一些實施例中，於步驟120及步驟130中，複數個閘極堆疊240、250形成於半導體基板上。複數個閘極堆疊可以包含介電層以及假性閘極。在一些實施例中，覆蓋層(未示出)可以形成於閘極介電層240上。覆蓋層可以包含透過習知技術已知的合適製程形成的耐熔金屬及其氮化物(例如TiN，TaN，W2N，TiSiN，TaSiN)。假性閘極250(例如多晶矽層)可以形成於覆蓋層上。通過適當的技術例如以常規方式的CVD形成假性閘極250(例如多晶矽層)。在一些實施例中，假性閘極250可以示例性的選自由多晶矽，非晶矽，微晶矽及其組合所組成之群組中之一。閘極堆疊可以示例性的形成於基板的不同區域中，例如由NFET裝置定義的 區域，由PFET裝置定義的區域，由高電阻電晶體定義的區域，由非功能性電晶體(亦稱為假性電晶體，dummy transistors)定義的區域，以及/或其他設計適合積體電路所定義的區域。
在一些實施例中，可以在假性閘極250(例如多晶矽層)上形成圖案化的硬式遮罩(未示出)，以定義各種閘極堆疊區域以及可以被移除的各個開口使得閘極堆疊料層可以露出。圖案化的硬式遮罩包含氮化鈦，氮化矽和/或氧化矽，或可以為光阻劑。圖案化的硬式遮罩可以包含雙層。 在一些實施例中，圖案化的硬式遮罩可以包含就由CVD製程沉積的氮化鈦，氧化矽以及氮化矽的雙層。使用光刻製程進一步圖案化氮化鈦，氮化矽和氧化矽層以形成圖案化的光阻層，以及藉由蝕刻製程蝕刻圖案化的光阻層開口內的氮化鈦，氮化矽和氧化矽。
在一些實施例中，通過使用圖案化的硬式遮罩作為蝕刻遮幕，可以應用於蝕刻製程通過蝕刻假性閘極250(例如多晶矽層)，覆蓋層(未示出)，閘極介電層240以及介面層(未示出)以形成閘極堆疊。蝕刻製程包含乾式蝕刻，濕式蝕刻，或乾式蝕刻及濕式蝕刻的組合。乾式蝕刻製程可以實施含氟氣體(例如CF4，SF6，CH2F2，CHF3及/或C2F6)，含氯氣體(例如Cl2，CHCl3，CCl4及/或BCl3)，含溴氣體(例如HBr及/或CHBR3)，含碘氣體，其他合適氣體及/或電漿，以及/或其組合。蝕刻製程可以包含多步驟蝕 刻以獲得蝕刻選擇性，彈性以及預期的蝕刻輪廓。在一些實施例中，傳統方式大多採用多步驟的乾式蝕刻。
於方法100中進行至步驟140，其形成保護密封層260。在一些實施例中，於步驟140中，一致地沉積密封材料260’如第5圖所示，覆蓋於閘極堆疊240、250以及隔離特徵230的上表面。接著，參照第6圖，形成蝕刻遮幕270覆蓋隔離特徵230上表面的密封材料260’，其中在上視圖中密封材料260’係環繞主動區220外之一部分的閘極堆疊240、250，同時露出閘極堆疊240、250上表面上的密封材料260’。在一些實施例中，蝕刻遮幕270可以藉由微影製程形成圖案化的光阻層。微影製程可以示例性的包含旋轉塗佈基材上的光阻層，在光阻層上曝光形成圖案，接著實施曝光後烘烤製程，以及使光阻層顯像而形成圖案化光阻層。在其他實施例中，蝕刻遮幕270可以是圖案化的硬式遮罩，其包含氮化矽，氧化矽，氮氧化矽或其組合，但不限於此。圖案化的硬式遮罩可以藉由CVD製程沉積，然後通過光刻以及蝕刻製程形成圖案化。
參照第7圖，形成蝕刻遮幕270後，接著先實施蝕刻製程依蝕刻遮幕270圖案去除密封材料260’，最後再移除蝕刻遮幕270以獲得保護密封層260。可藉由灰化製程(ashing)或選擇性濕式蝕刻移除蝕刻遮幕270。如第7圖所示，在一些實施例中，保護密封層260示例性的包含一垂直部分2601位於閘極堆疊240、250襯層的側壁以及一水平部分2602延伸至隔離特徵230的上表面。請參照第10圖，值 得注意的是，水平部分2602在上視圖中係環繞主動區220外之一部分的閘極堆疊。在一些實施例中，保護密封層示例性的包含氮化矽，氮氧化矽或其組合。在一些實施例中，蝕刻製程係使用包含稀釋的氟化氫(dilute HF，DHF)溶液，氧化物的蝕刻緩衝(buffered oxide etch，BOE)溶液，熱磷酸或H2O2溶液的濕式蝕刻。保護密封層260可以防止閘極介電層240及隔離特徵230(例如STI)在後續的處理製程期間受到損壞。舉例來說，在用於形成閘極間隔的濕式蝕刻製程中，已經觀察到濕式蝕刻劑可消耗隔離特徵，穿透至閘極堆疊並損壞閘極介電層240。然而，保護密封層260可以防止濕式蝕刻劑在後續處理期間滲入至閘極介電層240及隔離特徵230，例如形成間隔，移除假性閘極等。如此一來，可以製造具有改善可靠性和操作性能的半導體裝置200。
在形成閘極堆疊後，半導體裝置200可以經歷額外的互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，CMOS)處理以形成習知技術所熟知的NFET及PFET裝置的各種特徵。因此，在此僅簡要討論各種特徵。各種特徵可以包含輕摻雜源極/汲極區(lightly doped source/drain regions，N型及P型LDD)，側壁或閘極間隔，源極/汲極區(S/D)，矽化物特徵，接觸蝕刻停止層(contact etch stop layer，CESL)，以及層間介電層(interlayer dielectric，ILD)。值得注意的是，諸如矽鍺(SiGe)和碳化矽(SiC)特徵的應變結構可以分別形成在PFET和NFET裝置中，以促進及增強裝置的性能。
在一些實施例中，可以在形成源極/汲極區(或其部分)之前或之後鄰接閘極堆疊240、250的側壁形成閘極間隔(未示出)。閘極間隔可以包含一種或多種介電材料，例如氧化矽，氮化矽，氮氧化矽或其組合。間隔元件可以通過沉積介電材料然後進行均向性(isotropic)蝕刻製程來形成，然而其他實施方式也可以實施。在一些實施例中，保護密封層260形成在閘極堆疊的側壁上並且主間隔形成於保護密封層260上。在一些實施例中，間隔包含附加層。舉例來說，首先在保護密封層上形成介電層(未示出)，然後在介電層上形成主間隔。因此，主間隔可以視為具有間隔的雙層間隔。在一些實施例中，保護密封層包含氮化矽，介電層包含氧化矽，且主間隔包含氮化矽。藉由常規的沉積，微影和蝕刻製程形成間隔。
在一些實施例中，通過合適的技術例如一個或多個離子注入，形成源極和汲極區(未示出)。源極/汲極區可以包含引入適當的摻雜劑類型：N型或P型摻雜劑。源極/汲極區可以包含暈環(Halo)或輕摻雜源極/汲極區(low-dose drain，LDD)的植入，源極/汲極的植入，源極/汲極的激活，以及/或其他合適的製程。在一些實施例中，源極/汲極區可以包含增高式源極/汲極區(raised source/drain regions)，應變區，外延成長區(epitaxially grown regions)，以及/或其他合適的技術。在一實施例中，源極/汲極的激活製程可以包含快速熱回火(rapid thermal anneal)。在一些實施例中，可以對摻雜的源極/汲極區進行 矽化(silicidation)。矽化物材料可以包含矽化鎳(NiSi)，鎳-鉑矽化物(NiPtSi)，鎳-鉑-矽化鍺(NiPtGeSi)，鎳-矽化鍺(NiGeSi)，鐿矽化物(YbSi)，鉑矽化物(PtSi)，銥矽化物(IrSi)，鉺矽化物(ErSi)，鈷矽化物(CoSi)，其他合適的導電材料，以及/或其組合。矽化物特徵可以通過包含以下步驟的製程形成：沉積金屬層，回火金屬層，使得金屬層能夠與矽反應而形成矽化物，然後去除未反應的金屬層。
在一些實施例中，在形成源極/汲極(S/D)區後，可以進行一個或多個回火製程以激活S/D區。回火製程包含快速熱回火(rapid thermal annealing，RTA)，雷射回火製程，或其他合適的回火製程。舉例來說，可以施加900℃至1100℃範圍內的任何溫度的高溫熱回火步驟，即便其他實施例可以使用不同範圍內的溫度。另舉例來說，高溫回火包含具有非常短的持續時間的脈衝回火過程(spike annealing process)。
在一些實施例中，源極和汲極區可以包含用於適當應變效應的外延生長的半導體材料，導致通道中的載子的遷移率增強。在一實施例中，矽化鍺是用於P型FET(PFET)區和源極區的外延成長。在其他實施例中，碳化矽是用於N型FET(NFET)區和源極區的外延成長。形成應變結構的方法包含在半導體基板中蝕刻以形成凹陷，並且在凹陷中外延成長以形成晶體半導體材料。
參照第8圖，在形成源極/汲極區後，在半導體基板上和閘極堆疊之間形成沉積層間介電層 290(interlayer dielectric，ILD)。ILD層290的沉積填充了相鄰閘極堆疊之間的間隙。此後，可以在ILD層290上進行化學機械拋光(chemical mechanical polishing，CMP)和/或蝕刻製程，以平坦化ILD層290，直至露出假性閘極250。ILD層290可以包含諸如四乙氧基矽烷(tetraethylorthosilicate，TEOS)氧化物，未摻雜的矽酸鹽玻璃或摻雜的氧化矽例如硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)，熔凝石英玻璃(fused silica glass，FSG)，磷矽酸鹽玻璃(phosphosilicate glass，PSG)，硼摻雜矽玻璃(boron doped silicon glass，BSG)，以及/或其他合適的介電材料。ILD層290可以通過PECVD製程或其他適合的沉積技術來沉積。在一些實施例中，ILD層290可以包含通過高縱橫比製程(high aspect ratio process，HARP)及/或高密度電漿(high density plasma，HDP)沉積製程形成的氧化物。
方法100通過執行置換閘極的方法來進行步驟150及160以形成HK/金屬閘極堆疊。繼續參照第8圖，在暴露假性閘極250之後，通過乾式蝕刻，濕式蝕刻，乾式和濕式蝕刻的組合或其他合適的製程去除閘極堆疊內的假性閘極250，從而在閘極結構中形成溝槽式閘極300。例如，可以使用濕式蝕刻製程來去除假性閘極250。濕式蝕刻製程可以包含暴露於含氫氧化物的溶液(例如氫氧化銨)，去離子水 和/或其他合適的蝕刻劑溶液。可以理解的是，可以使用其他蝕刻化學製品來選擇性地去除假性閘極250。
在方法100中繼續進行至步驟160，其中如第9圖所示方法100之步驟150中所提供的溝槽式閘極內形成閘電極280。在一些實施例中，閘電極280可以示例性的包含金屬閘極，並且還可以包含閘極介電層，覆蓋層，填充層和/或其他合適的層(未示出)。在金屬閘極中的功函數金屬層(未示出)可以包含N型或P型功函數層。P型功函數金屬可以示例性的包含TiN，TaN，Ru，Mo，Al，WN，ZrSi2，MoSi2，TaSi2，NiSi2，WN，其他合適的P型功函數材料，或其組合。N型功函數金屬可以示例性的包含Ti，Ag，TaAl，TaAlC，TiAlN，TaC，TaCN，TaSiN，Mn，Zr，其他合適的n型功函數材料，或其組合。功函數層可以包含多個層。可以通過CVD，PVD和/或其他合適的製程來沉積功函數層。在一實施例中，形成閘電極280的是包含P型功函數層的P型金屬閘極。
閘電極280(金屬閘極堆疊)的介電層(未示出)可以包含高介電常數介電層例如氧化鉿(HfO2)。或者，高介電常數介電層可以選擇性的包含其他高介電常數介電質，例如TiO2，HfZrO，Ta2O3，HfSiO4，ZrO2，ZrSiO2，其組合或其他合適的材料。介電層可以通過ALD和/或其他適合的方法形成。介電層相較於如上述方法100的步驟120中的閘極結構中形成的閘極介電層240的組成可以是相同或相異。
在一些實施例中，閘電極280的填充層(未示出)可以包含Al，W或Cu，以及/或其他合適的材料。填充金屬可以通過CVD，PVD，電鍍，以及/或其他合適的製程形成。填充金屬可以沉積在功函數金屬層上，從而填充剩餘的部分溝槽或開口。
在一些實施例中，執行平坦化製程以暴露閘極結構的上表面。平坦化製程可以包含化學機械平坦化(chemical mechanical planarization，CMP)。在一些實施例中，可以進行金屬CMP以去除過多的金屬層。CMP製程提供閘極堆疊以及ILD層290實質上平坦的的表面。
在一些實施例中，用於製造半導體裝置的方法可以進一步包含形成多層互連。多層互連(未示出)可以包含垂直式互連例如常規的通孔或接點，以及水平式互連例如金屬線。各種互連特徵可以實施各種導體材料，包含銅，鎢及矽化物。在一示例中，鑲嵌製程(damascene process)用於形成銅相關的多層互連結構。在另一實施例中，鎢用於在接觸孔中形成鎢插栓(tungsten plug)。因此，可以使用常規的製程步驟形成上述的附加特徵，例如層間介電層，互連等，以完成半導體裝置200的製造。
因此，可獲得本發明實施例揭露的半導體裝置200。如第8圖及第9圖所示，其至少可以包含具有複數個隔離特徵230(例如淺溝槽隔離特徵，STI)定義而成之主動區220的半導體基板210；閘極堆疊延伸橫跨主動區220並位於隔離特徵230的一部分上，其中閘極堆疊包含閘極介電層 240(高介電常數(HK)介電材料)位於主動區220及部分的隔離特徵230上，以及閘電極280位於高介電常數(HK)介電材料240上；以及保護密封層260，其包含垂直部分2601位於閘極堆疊(240+280)襯層的側壁以及水平部分2602延伸至隔離特徵230的上表面，其中水平部分2602在一上視圖中係環繞主動區220外之一部分的閘極堆疊，並且其中保護密封層260暴露閘極堆疊(240+280)的上表面。在一些實施例中，如第10圖所示，保護密封層260的水平部分2602於上視圖中可以具有「工」形或「ㄈ」形。需注意的是，第10圖省略了ILD層290，以便清楚的看到保護密封層260。
雖然本發明實施例實施方式如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾。在一實施例中，閘極電極可以選擇性或額外的包含其他合適的金屬。
基於上述，應理解本發明實施例揭露一種半導體裝置及其製造方法，以提供簡單且能夠降低成本的製造流程來實施保護密封層，以避免濕式蝕刻劑損耗淺溝槽隔離(shallow trench isolation，STI)特徵，然後滲入至高介電常數(high-k，HK)介電材料中，從而防止高介電常數(high-k，HK)介電材料在蝕刻過程中損壞，進而可以改善產率。
根據本揭示之一態樣，半導體裝置包含：一半導體基板，其具有由一複數個隔離特徵定義而成的一主動區；一閘極堆疊延伸橫跨該主動區並位於該隔離特徵的一部 分上，其中該閘極堆疊包含一閘極介電層位於該主動區上及部分之該隔離特徵上，以及一閘電極位於該閘極介電層上；以及一保護密封層，包含一垂直部分位於該閘極堆疊襯層的側壁以及一水平部分延伸至該隔離特徵的上表面，其中該水平部分在一上視圖中係環繞該主動區外之該一部分的閘極堆疊。
根據本揭示之另一態樣，半導體裝置的製造方法包含：提供一半導體基板，其具有一主動區以及複數個隔離特徵；形成一閘極介電層於該主動區及部分之該隔離特徵上；形成一假性閘極於該閘極介電層上；形成一保護密封層，包含一垂直部分位於該閘極堆疊襯層的側壁以及一水平部分延伸至該隔離特徵的上表面，其中該水平部分在一上視圖中係環繞該主動區外之該一部分的閘極堆疊；藉由蝕刻移除該假性閘極以形成一溝槽式閘極，其中該保護密封層保護該閘極介電層在蝕刻時免於受到損害；以及使用閘電極填充該溝槽式閘極。
根據本揭示之又另一態樣，一半導體裝置包含：一半導體基板，其具有由一複數個淺溝槽隔離(STI)特徵定義而成的一主動區；一閘極堆疊位於該主動區上並延伸橫跨該淺溝槽隔離(STI)特徵的一部分上，其中該閘極堆疊包含一高介電常數(HK)介電材料位於該主動區上及部分之該淺溝槽隔離(STI)特徵上，以及一閘電極位於該高介電常數(HK)介電材料上；以及一保護密封層，包含一垂直部分位於該閘極堆疊襯層的側壁以及一水平部分延伸至該淺溝 槽隔離(STI)特徵的上表面，其中該水平部分在一上視圖中係環繞該主動區外之該一部分的閘極堆疊，且其中該保護密封層露出該閘極堆疊的上表面。
上文概述若干實施例或實例之特徵，以使熟習此項技術者可更好地理解本揭示之態樣。熟習此項技術者應瞭解，可輕易使用本揭示作為設計或修改其他製程及結構的基礎，以便實施本文所介紹之實施例或實例的相同目的及/或達成相同優勢。熟習此項技術者亦應認識到，此類等效結構並未脫離本揭示之精神及範疇，且可在不脫離本揭示之精神及範疇的情況下產生本文的各種變化、替代及更改。
200‧‧‧半導體裝置
210‧‧‧半導體基板
220‧‧‧主動區
230‧‧‧隔離特徵
240‧‧‧閘極堆疊
260‧‧‧保護密封層
2601‧‧‧垂直部分
2602‧‧‧水平部分
280‧‧‧閘電極
290‧‧‧層間介電層

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  1. 一種半導體裝置，包含：一半導體基板，其具有由複數個隔離特徵定義而成的一主動區；一閘極堆疊延伸橫跨該主動區並位於該隔離特徵的一部分上，其中該閘極堆疊包含一閘極介電層位於該主動區上及部分之該隔離特徵上，以及一閘電極位於該閘極介電層上；以及一保護密封層，包含一垂直部分位於該閘極堆疊襯層的側壁以及一水平部分延伸至該隔離特徵的上表面，其中該水平部分在一上視圖中係環繞該主動區外之該一部分的閘極堆疊。
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