JP5580355B2 - 半導体装置 - Google Patents
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- JP5580355B2 JP5580355B2 JP2012054541A JP2012054541A JP5580355B2 JP 5580355 B2 JP5580355 B2 JP 5580355B2 JP 2012054541 A JP2012054541 A JP 2012054541A JP 2012054541 A JP2012054541 A JP 2012054541A JP 5580355 B2 JP5580355 B2 JP 5580355B2
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- 239000004065 semiconductor Substances 0.000 title claims description 180
- 239000010410 layer Substances 0.000 claims description 305
- 239000011229 interlayer Substances 0.000 claims description 79
- 239000000758 substrate Substances 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 30
- 230000008859 change Effects 0.000 claims description 14
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 88
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- 239000002070 nanowire Substances 0.000 description 30
- 238000009792 diffusion process Methods 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229920001709 polysilazane Polymers 0.000 description 18
- 230000004048 modification Effects 0.000 description 17
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- 150000002500 ions Chemical class 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 11
- 238000001039 wet etching Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 6
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- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
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- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
図1は、第1実施形態の半導体装置の構造を示す平面図と断面図である。図1(a)は、半導体装置の平面構造を示す平面図に相当し、図1(b)、図1(c)はそれぞれ、図1(a)に示すI−I’線、J−J’線に沿った断面図に相当する。
次に、図2、図3を参照し、層間絶縁膜151の詳細について説明する。
次に、図4〜図30を参照し、第1実施形態の半導体装置の製造方法を説明する。
最後に、第1実施形態の効果について説明する。
図33は、第2実施形態の半導体装置の構造を示す平面図と断面図である。
次に、図34〜図37を参照し、第2実施形態の半導体装置の製造方法を説明する。
最後に、第2実施形態の効果について説明する。
図39は、第3実施形態の半導体装置の構造を示す平面図と断面図である。
次に、図40〜図43を参照し、第3実施形態の半導体装置の製造方法を説明する。
最後に、第3実施形態の効果について説明する。
図45は、第4実施形態の半導体装置の構造を示す平面図と断面図である。
次に、図46〜図54を参照し、第4実施形態の半導体装置の製造方法を説明する。
最後に、第4実施形態の効果について説明する。
図55は、第5実施形態の半導体装置の構造を示す断面図である。図55(a)、図55(b)はそれぞれ、上述のI−I’線、J−J’線に沿った断面図に相当する。また、図55(c)は、フィン111をX方向に垂直な断面で切断した断面図に相当する。
次に、図56〜図58を参照し、第5実施形態の半導体装置の製造方法を説明する。
最後に、第5実施形態の効果について説明する。
112:パンチスルーストッパ拡散層、113:ソース/ドレイン拡散層、
121:ハードマスク層、131:ゲート絶縁膜、132:ゲート電極、
133:キャップ層、134:側壁絶縁膜、
141:エピタキシャル層、142:シリサイド層、
151:層間絶縁膜、161:絶縁膜、162:保護膜、163:保護膜、
201:SiGe層、202:Si層、
301:絶縁膜、302:パッド部、303:SiGe残存領域、
401:ナノワイヤ、501:絶縁膜
Claims (14)
- 半導体基板と、
前記半導体基板の表面に形成され、(110)面である側面を有するフィンと、
前記フィンの側面に形成されたゲート絶縁膜と、
前記フィンの側面および上面に、前記ゲート絶縁膜を介して形成されたゲート電極と、
前記フィンの側面に、フィン高さ方向に沿って順に形成された複数のエピタキシャル層と、
前記半導体基板上に前記フィンを覆うように形成され、前記フィンと前記エピタキシャル層とに応力を印加する層間絶縁膜とを備え、
前記フィン高さ方向に隣接する前記エピタキシャル層間の隙間の間隔と、最下層の前記エピタキシャル層と前記層間絶縁膜の底面との間の隙間の間隔は、前記隙間の位置が高くなるほど狭くなるまたは広くなり、
前記層間絶縁膜は、前記フィンに対し、前記フィン高さ方向の圧縮応力または引張応力印加する、半導体装置。 - 半導体基板と、
前記半導体基板の表面に形成されたフィンと、
前記フィンの側面に形成されたゲート絶縁膜と、
前記フィンの側面および上面に、前記ゲート絶縁膜を介して形成されたゲート電極と、
前記フィンの側面に、フィン高さ方向に沿って順に形成された複数のエピタキシャル層と、
前記半導体基板上に前記フィンを覆うように形成され、前記フィンと前記エピタキシャル層とに応力を印加する層間絶縁膜とを備え、
前記フィン高さ方向に隣接する前記エピタキシャル層間の隙間の間隔と、最下層の前記エピタキシャル層と前記層間絶縁膜の底面との間の隙間の間隔は、前記隙間が位置する高さに応じて変化する、半導体装置。 - 前記フィン高さ方向に隣接する前記エピタキシャル層間の隙間の間隔と、最下層の前記エピタキシャル層と前記層間絶縁膜の底面との間の隙間の間隔は、前記隙間の位置が高くなるほど狭くなるまたは広くなる、請求項2に記載の半導体装置。
- 前記フィンの側面は、(110)面である、請求項2または3に記載の半導体装置。
- 前記層間絶縁膜は、前記フィンに対し、前記フィン高さ方向の圧縮応力または引張応力印加する、請求項2から4のいずれか1項に記載の半導体装置。
- 半導体基板と、
前記半導体基板の表面に形成され、第1材料で形成された1層以上の第1の層と、前記第1材料と異なる第2材料で形成された1層以上の第2の層とを交互に含むフィンと、
前記フィンの側面に形成されたゲート絶縁膜と、
前記フィンの側面および上面に、前記ゲート絶縁膜を介して形成されたゲート電極と、
個々の前記第2の層の側面に形成された複数のエピタキシャル層と、
前記半導体基板上に前記フィンを覆うように形成され、前記フィンと前記エピタキシャル層とに応力を印加する層間絶縁膜とを備え、
フィン高さ方向に隣接する前記エピタキシャル層間の隙間の間隔と、最下層の前記エピタキシャル層と前記層間絶縁膜の底面との間の隙間の間隔は、前記隙間が位置する高さに応じて変化する、半導体装置。 - 前記第1材料は、第1の半導体材料であり、前記第2材料は、前記第1の半導体材料と異なる第2の半導体材料である、請求項6に記載の半導体装置。
- さらに、個々の前記第1の層の側面に形成された複数のエピタキシャル層を備える、請求項7に記載の半導体装置。
- 前記フィン内において、前記第1の層の側面は、前記第2の層の側面に対し後退している、請求項7に記載の半導体装置。
- 前記フィン内において、前記第1の層の側面が後退している領域に、絶縁膜が埋め込まれている、請求項9に記載の半導体装置。
- 前記第1材料は絶縁材料であり、前記第2材料は半導体材料である、請求項6に記載の半導体装置。
- 前記フィン内において、前記第1の層のフィン延伸方向に垂直な側面は、前記第2の層のフィン延伸方向に垂直な側面に対し後退しており、
前記フィン内において、前記第1の層の前記側面が後退している領域に、前記層間絶縁膜が埋め込まれており、
前記第1の層の前記側面の後退量は、前記第1の層が位置する高さに応じて変化する、請求項6に記載の半導体装置。 - 半導体基板と、
前記半導体基板上に、互いに離間して積層された複数本のワイヤ層と、
個々の前記ワイヤ層の上面、下面、および側面に形成された複数のゲート絶縁膜と、
前記複数本のワイヤ層の上面、下面、および側面に、前記複数のゲート絶縁膜を介して形成されたゲート電極と、
個々の前記ワイヤ層の側面に形成された複数のエピタキシャル層と、
前記半導体基板上に前記複数本のワイヤ層を覆うように形成され、前記ワイヤ層と前記エピタキシャル層とに応力を印加する層間絶縁膜とを備え、
高さ方向に隣接する前記エピタキシャル層間の隙間の間隔と、最下層の前記エピタキシャル層と前記層間絶縁膜の底面との間の隙間の間隔は、前記隙間が位置する高さに応じて変化する、半導体装置。 - 半導体基板と、
前記半導体基板の表面に形成され、第1材料で形成された1層以上の第1の層と、前記第1材料と異なる第2材料で形成された1層以上の第2の層とを交互に含むフィンと、
前記フィンの側面に形成されたゲート絶縁膜と、
前記フィンの側面および上面に、前記ゲート絶縁膜を介して形成されたゲート電極と、
個々の前記第2の層の側面に形成された複数のエピタキシャル層と、
前記半導体基板上に前記フィンを覆うように形成され、前記フィンと前記エピタキシャル層とに応力を印加する層間絶縁膜とを備え、
前記フィン内において、前記第1の層のフィン延伸方向に垂直な側面は、前記第2の層のフィン延伸方向に垂直な側面に対し後退しており、
前記フィン内において、前記第1の層の前記側面が後退している領域に、前記層間絶縁膜が埋め込まれており、
前記第1の層の前記側面の後退量は、前記第1の層が位置する高さに応じて変化する、半導体装置。
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