JP2006507681A - 歪みFinFETCMOSデバイス構造 - Google Patents
歪みFinFETCMOSデバイス構造 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000003989 dielectric material Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 47
- 230000006835 compression Effects 0.000 claims description 8
- 238000007906 compression Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000012528 membrane Substances 0.000 claims 16
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 14
- 238000000151 deposition Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
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- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000010405 reoxidation reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 230000009977 dual effect Effects 0.000 description 1
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- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/772—Field effect transistors
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Abstract
【解決手段】本発明によれば、半導体デバイス構造は、基板(1、2)上に配置されたPMOSデバイス(200)およびNMOSデバイス(300)を含み、このPMOSデバイスはこのPMOSデバイスの活性領域に応力を加える圧縮層(6)を含み、このNMOSデバイスはこのNMOSデバイスの活性領域に応力を加える引張り層(9)を含み、この圧縮層は第1の誘電体材料を含み、この引張り層は第2の誘電体材料を含み、これらのPMOSおよびNMOSデバイスはFinFETデバイス(200、300)である。
Description
プロセス温度480℃、圧力6.25トル、ウェハと電極の間の間隔490ミル(12.4mm)、流量は2%希SiH4ガス3000sccm、NH3ガス15sccm、およびNガス1060sccm、340ワットの高周波電力使用。このプロセスは、約23Å/秒の堆積速度、および約500MPaの膜応力を発生させる。
Claims (17)
- 基板1、2上に配置されたPMOSデバイス200およびNMOSデバイス300を含む半導体デバイス構造であって、
前記PMOSデバイス200が、前記PMOSデバイスの活性領域3に応力を加える圧縮層6を含み、
前記NMOSデバイス300が、前記NMOSデバイスの活性領域3に応力を加える引張り層9を含み、
前記圧縮層が第1の誘電体材料6を含み、前記引張り層が第2の誘電体材料9を含み、前記PMOSおよびNMOSデバイスがFinFETデバイス200、300である半導体デバイス構造。 - 前記第1の誘電体材料がSiNを含む、請求項1に記載の半導体デバイス構造。
- 前記第2の誘電体材料がSiNを含む、請求項1に記載の半導体デバイス構造。
- 前記第1の誘電体材料が、−300MPa〜−3000MPaの範囲の実質的に均一な圧縮応力を有する、請求項1に記載の半導体デバイス構造。
- 前記第1の誘電体材料が、200Å〜2000Åの範囲の実質的に均一な厚みを有する、請求項1に記載の半導体デバイス構造。
- 前記第2の誘電体材料が、+200MPa〜+2000MPaの範囲の実質的に均一な引張り応力を有する、請求項1に記載の半導体デバイス構造。
- 前記第2の誘電体材料が、200Å〜2000Åの範囲の実質的に均一な厚みを有する、請求項1に記載の半導体デバイス構造。
- 前記第1の誘電体材料および前記第2の誘電体材料がSiNである、請求項1に記載の半導体デバイス構造。
- 同じ基板1、2上にp−FinFETデバイス領域200およびn−FinFETデバイス領域300を設けるステップと、
前記p−FinFETデバイス領域および前記n−FinFETデバイス領域上に第1のライナー5を配置するステップと、
前記第1のライナー上に圧縮膜6を配置するステップと、
前記p−FinFETデバイス領域上に第1のマスク7を配置するステップと、
前記n−FinFETデバイス領域から前記圧縮膜を除去するステップと、
前記第1のマスク7を除去するステップと、
前記p−FinFETデバイス領域および前記n−FinFETデバイス領域上に第2のライナー8を配置するステップと、
前記第2のライナー上に引張り膜9を配置するステップと、
前記n−FinFETデバイス領域上に第2のマスク10を配置するステップと、
前記p−FinFETデバイス領域から前記引張り膜を除去するステップと、
前記第2のマスクを除去するステップと、
を含む半導体デバイス構造の製造方法。 - 圧縮膜を配置する前記ステップが、約−1400MPaの膜応力を有する圧縮膜を配置するステップを含む、請求項9に記載の方法。
- 引張り膜を配置する前記ステップが、約+500MPaの膜応力を有する引張り膜を配置するステップを含む、請求項9に記載の方法。
- 前記圧縮膜がSiNである、請求項9に記載の方法。
- 前記引張り膜がSiNである、請求項9に記載の方法。
- 200Å〜2000Åの範囲の実質的に均一な厚みを有する前記圧縮膜を配置する、請求項9に記載の方法。
- 200Å〜2000Åの範囲の実質的に均一な厚みを有する前記引張り膜を配置する、請求項9に記載の方法。
- 圧縮膜を配置する前記ステップが、約−1400MPaより大きい膜応力を有する圧縮膜を配置するステップを含む、請求項9に記載の方法。
- 引張り膜を配置する前記ステップが、約+500MPaより大きい膜応力を有する引張り膜を配置するステップを含む、請求項9に記載の方法。
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PCT/US2002/037931 WO2004049406A1 (en) | 2002-11-25 | 2002-11-25 | Strained finfet cmos device structures |
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JP4384988B2 JP4384988B2 (ja) | 2009-12-16 |
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EP (1) | EP1565931B1 (ja) |
JP (1) | JP4384988B2 (ja) |
CN (1) | CN100378901C (ja) |
AT (1) | ATE377841T1 (ja) |
AU (1) | AU2002368388A1 (ja) |
DE (1) | DE60223419T2 (ja) |
TW (1) | TWI233694B (ja) |
WO (1) | WO2004049406A1 (ja) |
Cited By (8)
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JP2007294757A (ja) * | 2006-04-26 | 2007-11-08 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2007329295A (ja) * | 2006-06-08 | 2007-12-20 | Hitachi Ltd | 半導体及びその製造方法 |
WO2008078637A1 (ja) * | 2006-12-25 | 2008-07-03 | National University Corporation Nagoya University | パターン形成方法、および半導体装置の製造方法 |
JP2009259865A (ja) * | 2008-04-11 | 2009-11-05 | Toshiba Corp | 半導体装置、およびその製造方法 |
KR100957820B1 (ko) | 2007-01-17 | 2010-05-13 | 도쿄엘렉트론가부시키가이샤 | 핀형 전계 효과 트랜지스터의 제조 방법 |
JP2010245514A (ja) * | 2009-04-03 | 2010-10-28 | Internatl Business Mach Corp <Ibm> | 半導体構造体およびその形成方法(内部応力を有する半導体ナノワイヤ) |
JP2011199287A (ja) * | 2010-03-17 | 2011-10-06 | Taiwan Semiconductor Manufacturing Co Ltd | フィン型電界効果トランジスタおよびその製造方法 |
JP2013229597A (ja) * | 2012-04-25 | 2013-11-07 | Samsung Electronics Co Ltd | 応力近接効果を有する集積回路 |
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US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
DE102004026149B4 (de) | 2004-05-28 | 2008-06-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen eines Halbleiterbauelements mit Transistorelementen mit spannungsinduzierenden Ätzstoppschichten |
GB2442995B (en) * | 2004-05-28 | 2010-06-30 | Advanced Micro Devices Inc | Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress |
US7084461B2 (en) * | 2004-06-11 | 2006-08-01 | International Business Machines Corporation | Back gate FinFET SRAM |
US20060099763A1 (en) | 2004-10-28 | 2006-05-11 | Yi-Cheng Liu | Method of manufacturing semiconductor mos transistor device |
US7306997B2 (en) * | 2004-11-10 | 2007-12-11 | Advanced Micro Devices, Inc. | Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor |
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Also Published As
Publication number | Publication date |
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ATE377841T1 (de) | 2007-11-15 |
TWI233694B (en) | 2005-06-01 |
TW200425508A (en) | 2004-11-16 |
CN100378901C (zh) | 2008-04-02 |
DE60223419D1 (de) | 2007-12-20 |
CN1695227A (zh) | 2005-11-09 |
EP1565931A4 (en) | 2006-04-19 |
AU2002368388A1 (en) | 2004-06-18 |
JP4384988B2 (ja) | 2009-12-16 |
DE60223419T2 (de) | 2008-09-04 |
EP1565931A1 (en) | 2005-08-24 |
EP1565931B1 (en) | 2007-11-07 |
WO2004049406A1 (en) | 2004-06-10 |
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