JP5009611B2 - Finfetデバイス中の構造を形成する方法 - Google Patents
Finfetデバイス中の構造を形成する方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 34
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 17
- 239000002210 silicon-based material Substances 0.000 claims description 14
- 239000011810 insulating material Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 30
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- -1 structures Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description
したがって、FET性能を改善するとともにさらなるデバイス・スケーリングを可能とすべく、新規なデバイス構造が求められている。
このダブルゲートMOSFETでは、2つのゲートが短チャネル効果をコントロールするために使用される。
FinFETは、短チャネル耐性に優れている最近のダブルゲート構造である。FinFETは、バーティカルフィン(vertical fin)中に形成されたチャネルを含んでいる。このFinFET構造は、従来のプレーナ型のMOFETで使用されるのと同様のレイアウトや製造技術を使用して製造することができる。
この方法は、第1フィン構造を形成すべく絶縁層をエッチングするステップと、アモルファスシリコン層をたい積するステップと、第1フィン構造の第1側面に隣接する第2フィン構造と、第1フィン構造の逆側の第2側面に隣接する第3フィン構造を形成すべく、アモルファスシリコン層をエッチングするステップと、第2フィン構造および第3フィン構造の少なくとも上面にメタル層をたい積するステップと、第2フィン構造と第3フィン構造中のアモルファスシリコンを単結晶シリコン材料に変換すべく、金属誘起結晶化処理を実行するステップと、ソース領域およびドレイン領域を形成するステップと、第1フィン構造ないし第3フィン構造上にゲート材料をたい積するステップと、少なくとも1つのゲート電極を形成すべく、ゲート材料をパターン化しエッチングするステップと、を有する。
1つのFinFETデバイスの製造を以下に記載する。しかしながら、以下に記載する技術は、2つ以上のFinFETデバイスの形成にも同様に適用することができることが認識される。
ある実装の一例においては、基板200はシリコンからなる。
本発明の趣旨に沿った代替的な実装においては、基板200は、ゲルマニウムまたはシリコンゲルマニウムのような半導体材料の化合物(combination)を含んでいてもよい。さらに他の実装においては、基板200は、シリコンまたはゲルマニウム基板上に形成される、酸化膜のようなインシュレータを含んでいてもよい。
絶縁性のフィン構造210は、絶縁性のフィン構造210に隣接して形成されるデュアル・フィン構造中に、かなりの引張応力(負荷)を誘起する絶縁材料を含んでいてもよい。ある実装の一例においては、絶縁性のフィン構造210は酸化物または窒化物を含んでいてもよい。
本発明の趣旨に添った実装の一例においては、アモルファスシリコン層310は、約100Åから約1000Åの範囲の厚みにたい積することができる。
このCMPの間、絶縁性のフィン構造210およびアモルファスシリコンフィン構造410の上面の一部を除去してもよい。この結果、各アモルファスシリコンフィン構造410の上面が露出する。例えば、CMPの後、フィン210および410の高さは約150Åから200Åの範囲とすることができる。
MIC処理は、数時間の間、約500℃から約550℃でニッケル層710をアニーリングするステップを含んでいてもよい。このステップは、図8に示すように、フィン構造410中のアモルファスシリコンを単結晶シリコン810に変換すべく、ニッケルをアモルファスシリコン中に拡散するように働く(ステップ130)。
MIC処理の結果、基板200と単結晶シリコンフィン構造810との間にニッケルシリコン(NiSi)化合物820の薄膜を形成することができる。ある実装の一例においては、NiSi層820の厚みは、約20Åから約200Åの範囲となり得る。
例えば、絶縁層510を除去してもよいし、窒化ケイ素または酸化シリコンのような保護絶縁層をフィン210、810の上表面上に形成してもよい。その後、単結晶シリコンフィン構造810の側面上にゲート絶縁体を形成する。
それから、ソース/ドレイン領域を、フィン210、810各端部に形成することができ、その後、1つ以上のゲートを形成する。例えばゲート材料として、シリコン層、ゲルマニウム層、シリコンおよびゲルマニウムの化合物、または様々な金属を使用することができる。
その後、ゲート電極を形成すべく、ゲート材料をパターン化し、エッチングしてもよい。
図9は、ソース/ドレイン領域およびゲート電極を形成した後の、本発明の趣旨に添った半導体デバイスの典型的な平面図の一例を示す。この図に示すように、半導体デバイスは、フィン210、810、ソースおよびドレイン領域910、920を有するダブルゲート構造、ゲート電極930、940を含んでいる。
さらに、特定の回路必要条件に基づいてソース/ドレイン接合の位置を制御すべく、任意にサイドウォールスペーサをソース/ドレインのイオン注入より先に形成してもよい。
その後、ソース/ドレイン領域910、920を活性化すべく、活性化アニーリングを実行してもよい。
図10ないし図15は、代替的な本発明の趣旨に沿った実装における多数の(mutiple)FinFETデバイスを形成する図の一例を示す図である。
図10に示すように、基板1000上に酸化層1010を有する半導体デバイスから処理を開始することができる(ステップ105)。
基板1000は、シリコン、またはゲルマニウムやシリコンゲルマニウムのような半導体材料の化合物のような他の半導体材料を含んでいてもよい。酸化層1010は、約200Åから約1000Åの範囲の高さを有していもよい。
次に、アモルファスシリコン層310をたい積し、図11に示すようにアモルファスシリコンスペーサ1110を形成すべくエッチングしてもよい(ステップ110)。各アモルファスシリコンスペーサ1110は、約100Åから約1000Åの範囲の幅を有していてもよい。
図12に示すように、アモルファスシリコンスペーサ1110の間のギャップに絶縁材料1210をたい積してもよい。この絶縁材料は、酸化物または他の絶縁材料を含むことができる。
その後、MIC処理を実行してもよい。MIC処理は、図14に示すように、アモルファスシリコンスペーサ1110を単結晶シリコンフィン構造1410に変換すべく、数時間の間、約500℃から約550℃でニッケル層1310をアニーリングするステップを含んでいてもよい。
MIC処理の結果、基板1000と単結晶シリコンフィン構造1410との間にニッケルシリコン(NiSi)化合物1420の薄膜を形成することができる。ある実装の一例においては、NiSi層1420の厚みは、約20Åから約200Åの範囲となり得る。
図16に示すように、半導体デバイスは、基板(図示しない)上に形成された酸化層1610を含んでいてもよい。この基板の上にはシリコン層1620が形成されている。
窒化ケイ素または酸化シリコンのような材料をたい積、パターン化して、ハードマスク1640を形成してもよい。
次に、SiN、SiOその他の材料のようなスペーサ材料をたい積、エッチングして、ハードマスク1640の側面上にスペーサ1630を形成してもよい。
その後、図17に示すように、マスクとしてスペーサ1630およびハードマスク1640を使用してシリコン層1620をエッチングして、狭いトレンチ1710を形成してもよい。
トレンチ1710は、約100Åから約1000Åの範囲の幅を有していてもよい。トレンチ1710は、トレンチ1710の両側に配置したフィン1620間のカップリング効果を提供することができ、有利である。
例えば、上記記載においては、本発明についてよく理解できるように、特定の材料、構造、化学薬品、プロセス等のような多数の特定の詳細を記載している。
しかしながら、特にここに記載した詳細によることなく、本発明を実行することができる。その他、不必要に本発明の内容を不明瞭にしないように、周知のプロセス構造は詳細に記載していない。
本発明を実行する際に、従来のたい積技術、フォトリソグラフィ技術、およびエッチング技術を使用してもよい。なお、このような技術の詳細についてはここでは詳述していない。
Claims (11)
- 絶縁材料を含んでおり、第1側面および前記第1側面に対して反対面である第2側面を含む第1フィン構造と、
単結晶シリコン材料を含んでおり、前記第1フィン構造の第1側面に隣接して形成される第2フィン構造と、
単結晶シリコン材料を含んでおり、前記第1フィン構造の第2側面に隣接して形成される第3フィン構造と、
前記第1フィン構造、第2フィン構造および第3フィン構造の一端に形成されるソース領域と、
前記第1フィン構造、第2フィン構造および第3フィン構造の他端に形成されるドレイン領域と、
少なくとも1つのゲートと、
を含んでおり、
前記第1フィン構造、前記第2フィン構造、および前記第3フィン構造は、半導体の基板の上面に形成されており、前記第2フィン構造及び前記第3フィン構造のそれぞれと前記半導体の基板との間にはニッケルシリコン化合物の薄膜が形成されていることを特徴とする、FinFET半導体デバイス。 - 前記第1フィン構造の前記第1側面および第2側面間の幅は、200Åから1000Åの間である、請求項1記載のFinFET半導体デバイス。
- 前記絶縁材料は、酸化物または窒化物のいずれか一方を含む、請求項1記載のFinFET半導体デバイス。
- 前記第2フィン構造および前記第3フィン構造のそれぞれの幅は、100Åから1000Åの間である、請求項1記載のFinFET半導体デバイス。
- 半導体の基板と、該半導体の基板上に形成される絶縁層とを含んだFinFET半導体デバイスを製造する方法であって、
第1フィン構造を形成すべく絶縁層をエッチングするステップと、
アモルファスシリコン層をたい積するステップと、
前記第1フィン構造の第1側面に隣接する第2フィン構造と、前記第1フィン構造の逆側の第2側面に隣接する第3フィン構造を形成すべく、前記アモルファスシリコン層をエッチングするステップと、
前記第2フィン構造および前記第3フィン構造の少なくとも上面にメタル層をたい積するステップと、
前記第2フィン構造と前記第3フィン構造中のアモルファスシリコンを単結晶シリコン材料に変換するとともに、前記第2フィン構造及び前記第3フィン構造のそれぞれと前記半導体の基板との間にニッケルシリコン化合物の薄膜が形成されるように、金属誘起結晶化処理を実行するステップと、
ソース領域およびドレイン領域を形成するステップと、
前記第1フィン構造、第2フィン構造ないし第3フィン構造上にゲート材料をたい積するステップと、
少なくとも1つのゲート電極を形成すべく、ゲート材料をパターン化しエッチングするステップと、
を有する、方法。 - 前記絶縁層は、酸化物および窒化物の少なくとも一方を含む、請求項5記載の方法。
- 単結晶シリコン材料を含む第1フィン構造と、
前記単結晶シリコン材料を含む第2フィン構造と、
前記第1フィン構造と前記第2フィン構造の間に位置し、絶縁材料を含む第3フィン構造と、含み、
前記第3フィン構造は、前記第1フィン構造および前記第2フィン構造の前記単結晶シリコン材料に応力を誘起し、
前記第1フィン構造及び前記第2フィン構造のそれぞれと半導体の基板との間にはニッケルシリコン化合物の薄膜が形成されていることを特徴とする、
FinFET半導体デバイス。 - 前記第1フィン構造および前記第2フィン構造のそれぞれの幅は、100Åから1000Åの間である、請求項7記載のFinFET半導体デバイス。
- 前記第3フィン構造の幅は、100Åから1000Åの間である、請求項8記載のFinFET半導体デバイス。
- 前記絶縁材料は、酸化物および窒化物の少なくとも一方を含む、請求項9記載のFinFET半導体デバイス。
- 前記第1フィン構造、第2フィン構造および第3フィン構造の一端に位置するソース領域と、
前記第1フィン構造、第2フィン構造および第3フィン構造の他端に位置するドレイン領域と、
少なくとも1つのゲートと、
をさらに含む、請求項7記載のFinFET半導体デバイス。
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US10/405,343 | 2003-04-03 | ||
PCT/US2004/009696 WO2004093197A2 (en) | 2003-04-03 | 2004-03-29 | Method for forming structures in finfet devices |
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Families Citing this family (96)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6709982B1 (en) * | 2002-11-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Double spacer FinFET formation |
US7105894B2 (en) * | 2003-02-27 | 2006-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contacts to semiconductor fin devices |
US6900502B2 (en) | 2003-04-03 | 2005-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
US6882025B2 (en) * | 2003-04-25 | 2005-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained-channel transistor and methods of manufacture |
US7074656B2 (en) * | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
US6867433B2 (en) | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US6909147B2 (en) * | 2003-05-05 | 2005-06-21 | International Business Machines Corporation | Multi-height FinFETS |
KR100521382B1 (ko) * | 2003-06-30 | 2005-10-12 | 삼성전자주식회사 | 핀 전계효과 트랜지스터 제조 방법 |
US6943405B2 (en) * | 2003-07-01 | 2005-09-13 | International Business Machines Corporation | Integrated circuit having pairs of parallel complementary FinFETs |
US20050012087A1 (en) * | 2003-07-15 | 2005-01-20 | Yi-Ming Sheu | Self-aligned MOSFET having an oxide region below the channel |
US6936881B2 (en) * | 2003-07-25 | 2005-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor that includes high permittivity capacitor dielectric |
US6940705B2 (en) | 2003-07-25 | 2005-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor with enhanced performance and method of manufacture |
US7078742B2 (en) * | 2003-07-25 | 2006-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel semiconductor structure and method of fabricating the same |
JP3860582B2 (ja) * | 2003-07-31 | 2006-12-20 | 株式会社東芝 | 半導体装置の製造方法 |
US7301206B2 (en) * | 2003-08-01 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US20050035410A1 (en) * | 2003-08-15 | 2005-02-17 | Yee-Chia Yeo | Semiconductor diode with reduced leakage |
US20050035369A1 (en) * | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
US7112495B2 (en) * | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US7071052B2 (en) * | 2003-08-18 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistor with reduced leakage |
US7888201B2 (en) * | 2003-11-04 | 2011-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US6962843B2 (en) * | 2003-11-05 | 2005-11-08 | International Business Machines Corporation | Method of fabricating a finfet |
US7498225B1 (en) * | 2003-12-04 | 2009-03-03 | Advanced Micro Devices, Inc. | Systems and methods for forming multiple fin structures using metal-induced-crystallization |
US7198995B2 (en) * | 2003-12-12 | 2007-04-03 | International Business Machines Corporation | Strained finFETs and method of manufacture |
US20050186722A1 (en) * | 2004-02-25 | 2005-08-25 | Kuan-Lun Cheng | Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions |
KR100605104B1 (ko) * | 2004-05-04 | 2006-07-26 | 삼성전자주식회사 | 핀-펫 소자 및 그 제조 방법 |
US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
US7452778B2 (en) * | 2004-06-10 | 2008-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-wire devices and methods of fabrication |
JP2006128494A (ja) * | 2004-10-29 | 2006-05-18 | Toshiba Corp | 半導体集積回路装置及びその製造方法 |
US20060118892A1 (en) * | 2004-12-02 | 2006-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Structures to Produce a Strain-Inducing Layer in a Semiconductor Device |
KR100629604B1 (ko) * | 2004-12-31 | 2006-09-27 | 동부일렉트로닉스 주식회사 | 반도체 소자의 게이트 라인 형성 방법 |
TWI295506B (en) | 2005-02-03 | 2008-04-01 | Samsung Electronics Co Ltd | Semiconductor device having transistor with vertical gate electrode and method of fabricating the same |
US7288805B2 (en) | 2005-02-24 | 2007-10-30 | International Business Machines Corporation | Double gate isolation |
US7101763B1 (en) | 2005-05-17 | 2006-09-05 | International Business Machines Corporation | Low capacitance junction-isolation for bulk FinFET technology |
US20070018239A1 (en) | 2005-07-20 | 2007-01-25 | International Business Machines Corporation | Sea-of-fins structure on a semiconductor substrate and method of fabrication |
KR100642384B1 (ko) * | 2005-09-15 | 2006-11-03 | 주식회사 하이닉스반도체 | 반도체 메모리소자의 트랜지스터 및 그 제조방법 |
US7400031B2 (en) * | 2005-09-19 | 2008-07-15 | International Business Machines Corporation | Asymmetrically stressed CMOS FinFET |
FR2895835B1 (fr) * | 2005-12-30 | 2008-05-09 | Commissariat Energie Atomique | Realisation sur une structure de canal a plusieurs branches d'une grille de transistor et de moyens pour isoler cette grille des regions de source et de drain |
US7491995B2 (en) | 2006-04-04 | 2009-02-17 | Micron Technology, Inc. | DRAM with nanofin transistors |
US8734583B2 (en) * | 2006-04-04 | 2014-05-27 | Micron Technology, Inc. | Grown nanofin transistors |
US7425491B2 (en) | 2006-04-04 | 2008-09-16 | Micron Technology, Inc. | Nanowire transistor with surrounding gate |
US8354311B2 (en) | 2006-04-04 | 2013-01-15 | Micron Technology, Inc. | Method for forming nanofin transistors |
US7538391B2 (en) * | 2007-01-09 | 2009-05-26 | International Business Machines Corporation | Curved FINFETs |
US8558278B2 (en) | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
FR2921757B1 (fr) * | 2007-09-28 | 2009-12-18 | Commissariat Energie Atomique | Structure de transistor double-grille dotee d'un canal a plusieurs branches. |
JP5193583B2 (ja) * | 2007-12-17 | 2013-05-08 | 株式会社東芝 | フィン型トランジスタ |
US7943961B2 (en) | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US7808051B2 (en) | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
US8305829B2 (en) * | 2009-02-23 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same |
US8305790B2 (en) * | 2009-03-16 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical anti-fuse and related applications |
US8957482B2 (en) * | 2009-03-31 | 2015-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
US8912602B2 (en) * | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US8461015B2 (en) * | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
US8187928B2 (en) | 2010-09-21 | 2012-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuits |
US8759943B2 (en) | 2010-10-08 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having notched fin structure and method of making the same |
US8298925B2 (en) | 2010-11-08 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US9484462B2 (en) * | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
US8264021B2 (en) * | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
US8980719B2 (en) | 2010-04-28 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
US8472227B2 (en) * | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US8629478B2 (en) * | 2009-07-31 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure for high mobility multiple-gate transistor |
US8440517B2 (en) | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8482073B2 (en) * | 2010-03-25 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including FINFETs and methods for forming the same |
US8623728B2 (en) * | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
US8264032B2 (en) | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
US20110097867A1 (en) * | 2009-10-22 | 2011-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of controlling gate thicknesses in forming fusi gates |
US8021949B2 (en) * | 2009-12-01 | 2011-09-20 | International Business Machines Corporation | Method and structure for forming finFETs with multiple doping regions on a same chip |
US9040393B2 (en) | 2010-01-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
CN102263131B (zh) * | 2010-05-25 | 2013-05-01 | 中国科学院微电子研究所 | 一种半导体器件及其形成方法 |
US8603924B2 (en) | 2010-10-19 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming gate dielectric material |
US9048181B2 (en) | 2010-11-08 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US8769446B2 (en) | 2010-11-12 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and device for increasing fin device density for unaligned fins |
US8592915B2 (en) | 2011-01-25 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doped oxide for shallow trench isolation (STI) |
US8877602B2 (en) | 2011-01-25 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of doping oxide for forming shallow trench isolation |
US8431453B2 (en) | 2011-03-31 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure |
CN102956700B (zh) * | 2011-08-30 | 2015-06-24 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US8872284B2 (en) | 2012-03-20 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with metal gate stressor |
CN103378129B (zh) * | 2012-04-19 | 2016-03-23 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US8987790B2 (en) | 2012-11-26 | 2015-03-24 | International Business Machines Corporation | Fin isolation in multi-gate field effect transistors |
US8877588B2 (en) * | 2013-02-11 | 2014-11-04 | Globalfoundries Inc. | Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device |
US9396931B2 (en) | 2013-08-01 | 2016-07-19 | Qualcomm Incorporated | Method of forming fins from different materials on a substrate |
US9548213B2 (en) | 2014-02-25 | 2017-01-17 | International Business Machines Corporation | Dielectric isolated fin with improved fin profile |
US9224605B2 (en) * | 2014-05-01 | 2015-12-29 | Globalfoundries Inc. | Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process |
US9123627B1 (en) * | 2014-05-01 | 2015-09-01 | Globalfoundries Inc. | Methods of forming alternative material fins with reduced defect density for a FinFET semiconductor device |
CN105097535B (zh) * | 2014-05-12 | 2018-03-13 | 中国科学院微电子研究所 | FinFet器件的制造方法 |
US9847329B2 (en) * | 2014-09-04 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure of fin feature and method of making same |
US9805991B2 (en) * | 2015-08-20 | 2017-10-31 | International Business Machines Corporation | Strained finFET device fabrication |
US9722052B2 (en) * | 2015-10-27 | 2017-08-01 | International Business Machines Corporation | Fin cut without residual fin defects |
US10103246B2 (en) | 2016-06-09 | 2018-10-16 | International Business Machines Corporation | Fabrication of a vertical fin field effect transistor (vertical finFET) with a self-aligned gate and fin edges |
US9773870B1 (en) | 2016-06-28 | 2017-09-26 | International Business Machines Corporation | Strained semiconductor device |
US9680019B1 (en) * | 2016-07-20 | 2017-06-13 | Globalfoundries Inc. | Fin-type field-effect transistors with strained channels |
US10559501B2 (en) * | 2016-09-20 | 2020-02-11 | Qualcomm Incorporated | Self-aligned quadruple patterning process for Fin pitch below 20nm |
FR3089343B1 (fr) * | 2018-11-29 | 2021-10-08 | Commissariat Energie Atomique | Procede de realisation d’un transistor fet |
US11011626B2 (en) | 2019-05-07 | 2021-05-18 | International Business Machines Corporation | Fin field-effect transistor with reduced parasitic capacitance and reduced variability |
US11476356B2 (en) | 2020-05-29 | 2022-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field-effect transistor device with low-dimensional material and method |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0214578A (ja) | 1988-07-01 | 1990-01-18 | Fujitsu Ltd | 半導体装置 |
US5115289A (en) * | 1988-11-21 | 1992-05-19 | Hitachi, Ltd. | Semiconductor device and semiconductor memory device |
JP3202223B2 (ja) * | 1990-11-27 | 2001-08-27 | 日本電気株式会社 | トランジスタの製造方法 |
JPH04250667A (ja) * | 1991-01-28 | 1992-09-07 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2789931B2 (ja) * | 1991-05-27 | 1998-08-27 | 日本電気株式会社 | 半導体装置 |
KR920022546A (ko) * | 1991-05-31 | 1992-12-19 | 김광호 | 모오스 트랜지스터의 구조 및 그 제조방법 |
JPH04354138A (ja) * | 1991-05-31 | 1992-12-08 | Oki Electric Ind Co Ltd | Mis型半導体装置の製造方法 |
JP2572003B2 (ja) | 1992-03-30 | 1997-01-16 | 三星電子株式会社 | 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法 |
JP3203048B2 (ja) * | 1992-04-21 | 2001-08-27 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
DE19548056C1 (de) | 1995-12-21 | 1997-03-06 | Siemens Ag | Verfahren zur Herstellung einer Gateelektrode für eine MOS-Struktur |
US5946566A (en) | 1996-03-01 | 1999-08-31 | Ace Memory, Inc. | Method of making a smaller geometry high capacity stacked DRAM device |
JPH09293793A (ja) * | 1996-04-26 | 1997-11-11 | Mitsubishi Electric Corp | 薄膜トランジスタを有する半導体装置およびその製造方法 |
US5932911A (en) | 1996-12-13 | 1999-08-03 | Advanced Micro Devices, Inc. | Bar field effect transistor |
US6063688A (en) * | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
US6177299B1 (en) * | 1998-01-15 | 2001-01-23 | International Business Machines Corporation | Transistor having substantially isolated body and method of making the same |
JP4436469B2 (ja) * | 1998-09-30 | 2010-03-24 | 三洋電機株式会社 | 半導体装置 |
JP2001185721A (ja) * | 1999-12-22 | 2001-07-06 | Nec Corp | 半導体装置 |
US6483156B1 (en) * | 2000-03-16 | 2002-11-19 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
US20020011612A1 (en) | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
JP4044276B2 (ja) | 2000-09-28 | 2008-02-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6562665B1 (en) | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
US7163864B1 (en) * | 2000-10-18 | 2007-01-16 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6664143B2 (en) * | 2000-11-22 | 2003-12-16 | North Carolina State University | Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls |
US6358827B1 (en) | 2001-01-19 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method of forming a squared-off, vertically oriented polysilicon spacer gate |
US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
US6537880B1 (en) | 2001-09-13 | 2003-03-25 | Vanguard International Semiconductor Corporation | Method of fabricating a high density NAND stacked gate flash memory device having narrow pitch isolation and large capacitance between control and floating gates |
US6492212B1 (en) | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6583469B1 (en) | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
US6635909B2 (en) | 2002-03-19 | 2003-10-21 | International Business Machines Corporation | Strained fin FETs structure and method |
EP1383164A1 (en) * | 2002-07-17 | 2004-01-21 | Interuniversitair Micro-Elektronica Centrum (IMEC) | FinFET device and a method for manufacturing such device |
US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US6770516B2 (en) * | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US6864519B2 (en) | 2002-11-26 | 2005-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS SRAM cell configured using multiple-gate transistors |
US6645797B1 (en) * | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
US6794718B2 (en) * | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
US6716686B1 (en) | 2003-07-08 | 2004-04-06 | Advanced Micro Devices, Inc. | Method for forming channels in a finfet device |
-
2003
- 2003-04-03 US US10/405,343 patent/US6762448B1/en not_active Expired - Lifetime
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2004
- 2004-03-29 WO PCT/US2004/009696 patent/WO2004093197A2/en active Search and Examination
- 2004-03-29 DE DE112004000586T patent/DE112004000586B4/de not_active Expired - Lifetime
- 2004-03-29 KR KR1020057018827A patent/KR101070845B1/ko active IP Right Grant
- 2004-03-29 JP JP2006509472A patent/JP5009611B2/ja not_active Expired - Lifetime
- 2004-03-29 GB GB0521181A patent/GB2417829B/en not_active Expired - Lifetime
- 2004-03-29 CN CNB2004800087527A patent/CN100413038C/zh not_active Expired - Lifetime
- 2004-04-01 TW TW093109021A patent/TWI384614B/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
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US6762448B1 (en) | 2004-07-13 |
KR20050118717A (ko) | 2005-12-19 |
DE112004000586T5 (de) | 2006-02-16 |
GB0521181D0 (en) | 2005-11-23 |
WO2004093197A3 (en) | 2005-02-10 |
GB2417829A (en) | 2006-03-08 |
CN100413038C (zh) | 2008-08-20 |
CN1768419A (zh) | 2006-05-03 |
GB2417829B (en) | 2006-08-30 |
KR101070845B1 (ko) | 2011-10-10 |
TW200501393A (en) | 2005-01-01 |
TWI384614B (zh) | 2013-02-01 |
US20040198031A1 (en) | 2004-10-07 |
US6852576B2 (en) | 2005-02-08 |
WO2004093197A2 (en) | 2004-10-28 |
DE112004000586B4 (de) | 2010-04-08 |
JP2006522488A (ja) | 2006-09-28 |
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