JP3202223B2 - トランジスタの製造方法 - Google Patents

トランジスタの製造方法

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Publication number
JP3202223B2
JP3202223B2 JP32479990A JP32479990A JP3202223B2 JP 3202223 B2 JP3202223 B2 JP 3202223B2 JP 32479990 A JP32479990 A JP 32479990A JP 32479990 A JP32479990 A JP 32479990A JP 3202223 B2 JP3202223 B2 JP 3202223B2
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JP
Japan
Prior art keywords
film
substrate
sio
transistor
silicon layer
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Expired - Fee Related
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JP32479990A
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JPH04192564A (ja
Inventor
俐昭 黄
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NEC Corp
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NEC Corp
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Priority to JP32479990A priority Critical patent/JP3202223B2/ja
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Priority to US08/242,147 priority patent/US5545586A/en
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
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  • Theoretical Computer Science (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】
【０００１】 ［産業上の利用分野］ 本説明は、メモリ、論理回路等の高集積性を要求され
る半導体装置に利用されるトランジスタの製造方法に関
する。
【０００２】 ［従来の技術］ 従来、トランジスタの占有面積を縮小するための試み
として、縦型のMOS型電界効果トランジスタを作製する
試みがなされている。 例えば、須之内らは1989アイ・イー・ディー・エム
テクニカルダイジェスト（1989IEDM Tech.Dig.）23ペー
ジに第４図（ａ），（ｂ）に示した構造を持つエス・ジ
ー・ティー（SGT）と呼ばれるトランジスタ提案してい
る。これは柱状の形状を持つトランジスタで、上部より
ドレイン領域、チャネル領域が存在し、それより下部の
領域には側方（第４図（ａ））あるいは柱状形状の側壁
（（第４図（ｂ））にソース領域が存在する。図中、35
はシリコン基板、36はドレイン拡散層、37はソース拡散
層、38はゲート酸化膜、39はゲート電極、40は第１の拡
散層、41は第２の拡散層、42はパンチスルーキラーであ
る。 また、加賀らは1989アイ・イー・ディ・エム テクニ
カルダイジェスト（1989IEDM Tech.Dig.）833ページに
デルタ（DELTA）と呼ばれるトランジスタを提案してい
る。これは第５図に示すように、基板に対して垂直に立
った平板状の半導体領域を形成し、ソース，チャネル，
ドレインを横方向に形成するものである。図中、45はゲ
ート酸化膜、46はゲート電極、47はソース、48はドレイ
ン、43はシリコン基板、44は第１のSiO2,膜である。
【０００３】 ［発明が解決しようとする課題］ MOSFETにより構成されるLSIにおいて、集積度の向上
を図るには、MOSFETの各寸法の縮小を図ることが必要で
ある。しかし、例えばゲート長に関していえば、現状で
は0.3〜0.4μｍ程度以下にすることは困難である。これ
に対して、通常のトランジスタ動作に必要なシリコン層
の厚さは数十〜数百Åであり、実際厚さ数百ÅのSOI MO
SFETが試作され、数多くの報告がなされている（例えば
アイ・イー・イー・イー・トランザクション・オブ・エ
レクトロニクスデバィスレターズ７巻244ページ［IEEE,
EDL−7,244（1986）］）。そこで集積度を向上させるた
めに、薄膜状のトランジスタを基板に対して垂直に配置
する方法が考えられる。 第５図に示した従来例ではソース，ゲート，ドレイン
の三つの領域がそれぞれ面積を占有してしまう。また第
４図（ａ）の従来例ではソースがトランジスタの側方に
あるため、余分な面積を占有し、設計の自由度が減る。
第４図（ｂ）の従来例ではソースの不純物を側方から導
入するためのプロセスが複雑でかつ不純物プロファイル
の制御に精密さが要求される。 次に、従来例（第４図，第５図）のような縦型トラン
ジスタでは、エッチングにより基板を掘り下げることに
より、平板上あるいは柱状の構造（以下縦型トランジス
タ基板と呼ぶ）を形成する。しかし、一般に垂直にエッ
チングを行うのは困難であり、縦型トランジスタ基板の
膜厚が一定でなくなる。また、エッチングのマスクとな
る幅の狭いレジストパターンを形成することも困難であ
る。基板が薄く、チャネル領域の空乏層が基板付近まで
届くいわゆる完全空乏化SOI MOSFETでは、トランジスタ
特性が膜厚に敏感に依存するため、膜厚の制御は重要な
課題である。 また、従来例（第４図，第５図）のような縦型トラン
ジスタでは、不純物導入に斜めイオン注入を用いるな
ど、イオン注入により形成される不純物プロファイルの
制御に高度な配慮が必要である。 本発明の目的は、前記課題を解決したトランジスタの
製造方法を提供することにある。
【０００４】 ［課題を解決するための手段］ 前記目的を達成するため、本発明に係る第１のトラン
ジスタの製造方法は、半導体基板上に、略垂直な側面を
持ち、前記略垂直な側面に隣接した一部の位置において
前記半導体基板が露出する形状を持つ、第１の絶縁体に
覆われたパターンを設け、続いてスペーサーとなる物質
を前記略垂直な側面に付着するように基板上に堆積さ
せ、続いて第２の絶縁膜を堆積したのち、該第２の絶縁
膜をエッチバックして前記スペーサーの上部を露出さ
せ、スペーサーを第１及び第２の絶縁膜に対して選択的
にエッチングして除去することにより、該絶縁膜中に基
板表面に対してほぼ垂直な方向にスリットを設け、基板
をシードとし、このスリット中に半導体を選択的かつエ
ピタキシャルに成長させることにより、長辺のうち少な
くとも一つが基板表面に対してほぼ垂直となるように配
置された平板状の半導体よりなるトランジスタ基板を製
造することを特徴とする。
【０００５】 ［作用］ 第２図（ａ），（ｂ）に、本発明の参考例となるMOSF
ETの一例を示す。 図において、20はシリコン基板、21は第１のSiO2膜,2
2はスリット、23は第１のシリコン層、24は第２のシリ
コン層、25は第３のシリコン層、26は第２のSiO2膜,27
はポリシリコンである。 従来例（第５図）では、ソース，チャネル，ドレイ
ン，ゲートの４領域が面積を占有するのに対し、本発明
では、ゲート及びトランジスタの断面の２領域だけが面
積を占有し、面積が節減される。従来例（第４図
（ａ））に対しては、下部拡散層の横方向の広がりが少
ない分面積の節減になる。従来例（第４図（ｂ））に対
しては、下部拡散への電極の付加が容易な点で本発明の
参考例は優れる。 低温で不純物をドープしながらエピタキシャル成長を
行うことにより、特に縦型トランジスタを斜めイオン注
入により形成する際問題になるイオン注入後の不純物の
プロファイルの広がり、あるいはイオン注入後の不純物
を活性化する熱処理に伴う不純物の拡散を防ぐことがで
きる。 また、膜が堆積する際、現行のプロセスにおいても、
信頼性が高く、かつ精密な膜厚制御が可能であることを
利用することにより、ゲート電極の位置を決定し、余分
な寄生容量を低減することができる。 ここで本発明では、膜厚制御性の良いスペーサー物質
の堆積プロセスに基づいて、縦型トランジスタ基板の膜
厚が決定できるため、エッチングにより縦型トランジス
タ基板を形成した際発生する膜厚の不均一性を回避する
ことができる。
【０００６】 ［実施例］ 以下、本発明を実施例を図により説明する。
【０００７】 （実施例１） 第１の発明に基づくトランジスタの製造方法を第１図
（ａ）〜（ｆ）に示す。 第１図（ａ）に示すように、Ｐ型シリコン基板１を20
00Å熱酸化し、第１のSiO2膜２を形成し、つづいて3000
Åのポリシリコン膜４をLPCVDにより堆積し、ポリシリ
コン膜４へのリンの拡散を行い、通常のフォトリソグラ
フィ工程及びドライエッチングによりポリシリコン膜４
をパターニングし、ECRプラズマCVDにより、第２のSiO2
膜３をポリシリコン膜４が存在する領域では膜厚が2000
Å、ポリシリコン膜４が存在しない領域では膜厚が5000
Åとなり、第２のSiO2膜３の表面が平坦となるように堆
積し、第１図（ａ）に示した形状を得る。 次に、第１図（ｂ）に示すように、ウェハの上面から
見て、ポリシリコン膜４のある領域５を横断するように
矩形の開口部６をリソグラフィ工程及びドライエッチン
グ工程により設ける。矩形の長辺は例えば1.0μｍ、短
辺は5000Åとする。このとき、開口部６では第１のSiO2
膜2,ポリシリコン膜4,第２のSiO2膜３が除去され、シリ
コン基板１が露出するようにする。そして、等方性のエ
ッチングにより、ポリシリコン膜４を50Åエッチング
し、続いて、熱酸化による100Åの第３のSiO2膜７の形
成、ドライエッチングによる開口部６の酸化膜の除去を
行い、1000ÅのポリシリコンをLPCVDにより堆積したあ
と、ドライエッチングによりポリシリコン膜７を1000Å
エッチングし、開口部６の側壁に第２のポリシリコン膜
８を残し、第１図（ｂ）に示した形状を得る。 次に第１図（ｃ）に示すように、LPCVDにより第４のS
iO2膜９を5000Å堆積し、ドライエッチングにより5000
Åのエッチングを行い、開口部６を第４のSiO2膜９によ
り埋める。そして第２のポリシリコン膜７をエッチング
により除去し、スリット10を形成し、第１図（ｃ）に示
した形状を得る。 次に、第１図（ｄ）に示すように、酸化膜にはシリコ
ンが成長しない選択エピタキシャル成長により、スリッ
ト10の中に、基板と同一導電型の第１導電型の不純物、
例えばボロンを３×1017cm-3ドープした第１のシリコン
層11を1000Å、第２導電型の不純物、例えばヒ素を１×
1017cm-3ドープした第２のシリコン層12を1500Å、ボロ
ンを５×1017cm-3ドープした第３のシリコン層13を2000
Å、ヒ素を１×1017cm-3ドープした第４のシリコン層14
を2500Åだけそれぞれ成長させ、第１図（ｄ）に示した
形状を得る。 次に開口部６の端部に位置する第２の開口15をフォト
リソグラフィ及びドライエッチングに行う。このとき第
２の開口15の領域にある第１のSiO2膜2,第２のSiO2膜3,
ポリシリコン膜４はすべて除去する。第２の開口15の寸
法は、例えば0.3μｍ角とする。そしてLPCVDにより第５
のSiO2膜16を3000Å堆積し、コンタクト開口17におい
て、ポリシリコン膜4,第３のシリコン層13,第４のシリ
コン層14,第２のSiO2膜８のすべてと、第１のシリコン
層11の上部500Åをドライエッチングにより除去する。
このとき、コンタクト開口17の寸法は0.4μｍ角とす
る。そして熱酸化により、コンタクト開口17に露出した
ポリシリコン膜4,第３のシリコン層13,第４のシリコン
層14の側面、第１のシリコン層11の上面に200Åの第６
のSiO2膜18を設け、さらに第７のSiO2膜19をLPCVDによ
り1000Å堆積し、ドライエッチングによりコンタクト開
口17の付近にある第６のSiO2膜18と第７のSiO2膜19を除
去する。そして、第４のシリコン層14及び第１のポリシ
リコン膜４に対して通常のコンタクトホールを開け、通
常の工程で配線を形成すると、第１図（ｆ）に示した縦
型トランジスタを得る。
【０００８】 （参考例２） 第２図（ａ），（ｂ）に、本発明の参考例となるトラ
ンジスタの製造方法を示す。 第２図（ａ）に示すように、第１の導電型のシリコン
基板20の表面に熱酸化により第１のSiO2,膜21を5000Å
形成する。続いて通常のリソグラフィ及びドライエッチ
ングによりスリット22を形成し、第２図（ａ）の形状を
得る。 選択的エピタキシャル成長により、第２の導電型の第
１のシリコン層23,第１の導電型の第２のシリコン層24,
第１の導電型の第３のシリコン層25をこの順にそれぞれ
1500Å,2000Å,1500Åそれぞれ形成し、第１のSiO2,膜
を4000Åドライエッチングにより除去する。 熱酸化により第２のSiO2膜26を100Å形成し、ポリシ
リコン膜27を1000Å堆積し、続いて1000Åポリシリコン
膜27をドライエッチングし、第２（ｂ）の形状を得る。
このとき、ポリシリコン膜27には成長中に不純物のドー
ピングを行う。
【０００９】 （参考例３） 第３図（ａ），（ｂ），（ｃ）に、本発明の別の参考
例となるトランジスタの製造方法を示す。 第３図（ａ）に示すように、シリコン基板28の表面に
熱酸化により第１のSiO2膜29をパターニングし、第１の
ポリシリコン膜30を1000ÅLPCVDにより堆積し、続いて1
000Åのポリシリコンに対するドライエッチングを行
い、第３図（ａ）の構造を得る。ここで、第１のSiO2膜
29のスペースは5000Åとする。 第３図（ｂ）に示すように、続いて3000Åの第２のSi
O2膜31のLPCVDによる堆積、SiO2膜に対する3000Åのド
ライエッチングを行い、レーザーアニールにより第１の
ポリシリコン膜30を単結晶化し、単結晶シリコン膜32を
形成し、第３図（ｂ）の形状を得る。 第３図（ｃ）に示すように、続いてドライエッチング
により単結晶シリコン膜32をパターニングし、第１のSi
O2膜29を4000Åドライエッチングし、斜めイオン注入に
より第１の導電型の不純物を注入し、単結晶シリコン膜
32の表面を200Å熱酸化し、第２のSiO2膜33を形成した
のち、第２のポリシリコン膜34を2000Å堆積し、ドライ
エッチングにより第２のポリシリコン膜34をパターニン
グし、斜めイオン注入により第２の導電型の不純物を注
入し、第３図（ｃ）の形状を得る。 また、この参考例においては、第２のSiO2膜31を省略
することができる。
【００１０】 ［発明の効果］ 以上説明したように、本発明によれば、トランジスタ
の集積度を著しい向上、不純物分布の制御性の向上、ト
ランジスタ製造プロセスの自由度の向上が可能である。 さらに、本発明によれば、縦型トランジスタ基板の膜
厚の高精度に制御することができる。
【図面の簡単な説明】
第１図（ａ），（ｂ），（ｃ），（ｄ），（ｅ），
（ｆ）は、本発明の実施例１に係る製造方法を工程順に
示した断面図、第２図（ａ），（ｂ）は、本発明の参考
例２に係る製造方法を工程順に示した断面図、第３図
（ａ），（ｂ），（ｃ）は、本発明の参考例３に係る構
造方法を工程順に示した断面図、第４図（ａ），
（ｂ），第５図は、従来例を示す断面図でる。 1,20,28……シリコン基板、2,21……第１のSiO2膜 ３……第２のSiO2膜、４……ポリシリコン膜 ５……ポリシリコン膜４のある領域、６……開口部 ７……第３のSiO2膜、８……第２のポリシリコン膜 ９……第４のSiO2膜、10,22……スリット 11,23……第１のシリコン層、12,24……第２のシリコン
層 13,25……第３のシリコン層、14……第４のシリコン層 15……第２の開口、16……第５のSiO2膜 17……コンタクト開口、18……第６のSiO2膜 19……第７のSiO2膜、29……第１のSiO2膜 30……第１のポリシリコン膜、31,33……第２のSiO2膜 32……単結晶シリコン、34……第２のポリシリコン膜

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】半導体基板上に、略垂直な側面を持ち、前
    記略垂直な側面に隣接した一部の位置において前記半導
    体基板が露出する形状を持つ、第１の絶縁体に覆われた
    パターンを設け、続いてスペーサーとなる物質を前記略
    垂直な側面に付着するように基板上に堆積させ、続いて
    第２の絶縁膜を堆積したのち、該第２の絶縁膜をエッチ
    バックして前記スペーサーの上部を露出させ、スペーサ
    ーを第１及び第２の絶縁膜に対して選択的にエッチング
    して除去することにより、該絶縁膜中に基板表面に対し
    てほぼ垂直な方向にスリットを設け、基板をシードと
    し、このスリット中に半導体を選択的かつエピタキシャ
    ルに成長させることにより、長辺のうち少なくとも一つ
    が基板表面に対してほぼ垂直となるように配置された平
    板状の半導体よりなるトランジスタ基板を製造すること
    を特徴とするトランジスタの製造方法。
JP32479990A 1990-11-27 1990-11-27 トランジスタの製造方法 Expired - Fee Related JP3202223B2 (ja)

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US08/242,147 US5545586A (en) 1990-11-27 1994-05-13 Method of making a transistor having easily controllable impurity profile

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