WO2012041035A1 - 一种闪存器件及其形成方法 - Google Patents

一种闪存器件及其形成方法 Download PDF

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Publication number
WO2012041035A1
WO2012041035A1 PCT/CN2011/071248 CN2011071248W WO2012041035A1 WO 2012041035 A1 WO2012041035 A1 WO 2012041035A1 CN 2011071248 W CN2011071248 W CN 2011071248W WO 2012041035 A1 WO2012041035 A1 WO 2012041035A1
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fin
layer
flash memory
memory device
gate
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PCT/CN2011/071248
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English (en)
French (fr)
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朱慧珑
尹海洲
骆志炯
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中国科学院微电子研究所
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Priority to US13/148,265 priority Critical patent/US8878280B2/en
Publication of WO2012041035A1 publication Critical patent/WO2012041035A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Definitions

  • Flash memory device and method of forming same
  • the present invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory device having a FinFET (Fin Field Effect Transistor) structure and a method of forming the same.
  • FinFET Fin Field Effect Transistor
  • a flash memory device is a device for electrically writing and erasing data, which forms two capacitors in series by forming a dielectric layer between a control gate, a floating gate, and a substrate. The charge can be held on the floating gate even when the device is powered down to provide a memory function.
  • An object of the present invention is to at least solve one of the above technical drawbacks, and in particular to provide a FinFET flash memory device compatible with a FinFET device and a manufacturing process thereof, while reducing manufacturing cost.
  • an aspect of the present invention provides a flash memory device, located above an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a layer on sidewalls and tops of the first and second fins; a floating gate on the gate dielectric layer across the first and second fins; source/drain regions, Located in the first fin on both sides of the floating gate.
  • Another aspect of the present invention also provides a method of forming a flash memory device, the method comprising: providing a substrate, the substrate comprising an insulating layer and a semiconductor layer, the semiconductor layer being located in the insulating layer Forming the semiconductor layer to form a first fin and a second fin; forming a gate dielectric layer on sidewalls and tops of the first fin and the second fin; forming on the gate dielectric layer a floating gate spanning the first fin and the second fin; forming source/drain regions in the first fins on both sides of the floating gate.
  • the FinFET flash device process is fully compatible with the FinFET logic device process, and the manufacturing cost can be reduced.
  • FIGS. 2 through 9 are schematic structural views of a device in an intermediate step of a method of fabricating a flash memory device according to an embodiment of the present invention. detailed description
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • 1 is a cross-sectional view showing the structure of a FinFET flash memory device of the present invention.
  • the device is formed on an insulating substrate, which may include an insulating layer 112 and a semiconductor layer 110, the insulating layer 112 being over the semiconductor layer 110.
  • the substrate material may be any semiconductor-on-insulator (SOI) substrate.
  • the embodiment of the present invention uses a silicon-on-insulator substrate as an example, that is, the semiconductor layer 110 is a silicon layer, and the insulating layer 112 is a buried oxide layer (BOX, such as Si0 2 ), the silicon layer on the BOX can directly form fins, ie silicon fins.
  • the semiconductor layer 110 is a silicon layer
  • the insulating layer 112 is a buried oxide layer (BOX, such as Si0 2 )
  • the silicon layer on the BOX can directly form fins, ie silicon fins.
  • the device includes a first fin 114 and a second fin 116 formed on an insulating substrate, wherein the first fin 114 is a flash memory channel, the second fin 116 is a control gate; the first fin 114 and the second a gate dielectric layer 118 on sidewalls and tops of the fins 116; a floating gate 120 formed on the substrate 110 and spanning the first fins 114 and the second fins 116; sources formed on both sides of the first fins 114 / leak zone. Among them, the source/drain regions are not shown in Fig. 1.
  • the device may further include a protective cap layer 160 formed on an upper portion of the silicon layer of the first fin 114 and the second fin 116.
  • the device may further include sidewall spacers 122 formed on both sides of the floating gate. Wherein, the side wall 122 is not shown in FIG.
  • the second fin 116 may be n-type or p-type doped.
  • the second fin 116 is preferably n-type doped, for example, P or As ions may be used as dopant impurities.
  • the n-type doping is more conducive to the conductivity of the control gate.
  • the floating gate 120 can be a polysilicon gate or a metal gate.
  • the first fins 114 and the second fins 116 are arranged in parallel on the insulating layer.
  • FIG. 1 a method of forming a flash memory device as shown in FIG. 1 will be described in detail with reference to the accompanying drawings.
  • the present invention can be formed by using steps and processes different from those described below, without departing from the scope of the present invention.
  • Step 301 Providing a substrate.
  • the substrate includes an insulating layer 112 and a semiconductor layer 113, and the semiconductor layer 113 is located above the insulating layer 112.
  • the substrate may be of any of the insulating materials and semiconductor materials conventionally used, but in practice, an SOI substrate may be directly used.
  • the silicon-on-insulator substrate includes a bottom silicon layer 110, an intermediate buried oxide layer (BOX, such as SiO 2 ) 112, and a top silicon layer 113, thereby forming a layer as shown in FIG. 2 .
  • BOX intermediate buried oxide layer
  • Step 302 Patterning the silicon layer 113 to form a first fin 114 and a second fin 116, wherein the first fin 114 is a channel of the device and the second fin 116 is a control gate of the device.
  • a protective cap layer 160 may also be formed on the first fins 114 and the second fins 116.
  • a protective layer is first formed on the silicon layer 113, wherein the protective layer may include any one or more of insulating materials such as Si 3 N 4 , SiO 2 , SiOF, SiCOH, SiO, SiCO, SiCON, and SiON.
  • the combination is formed by a conventional deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • sputtering a conventional deposition process
  • the above structure is patterned (not shown), for example, by spin-coating photoresist on the protective layer, exposure, development, and etching, such as reactive ion etching (RIE), to provide a protective layer and a silicon layer.
  • 113 is patterned into a shape corresponding to the fin (Fin) to be formed, and etching is stopped on the BOX layer 112, and then the photoresist is removed to obtain a structure as shown in FIG. 3, that is, the silicon layer 113 is formed after etching.
  • the first fin 114 and the second fin 116 are etched to form a protective cap layer 160 on the first fin 114 and the
  • Step 303 forming a gate dielectric layer 118 on sidewalls and tops of the first fins 114 and the second fins 116, as shown in FIG.
  • a gate dielectric layer 118 is deposited over the device shown in FIG.
  • the gate dielectric layer 118 has a thickness of 2-15 nm.
  • the gate dielectric layer 118 may comprise silicon oxide, silicon oxynitride or a high-k material, examples of which include, for example, germanium-based materials such as hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON).
  • the gate dielectric layer 118 can be formed by thermal oxidation, CVD, ALD, or the like. The above process methods are merely examples, and the present invention is not limited thereto.
  • etching is further performed, specifically, the gate dielectric layer 118 is etched, for example, by RIE, and stopped on the BOX layer 112.
  • the second fin 116 is doped with n-type or p-type, wherein n-type doping is preferred, which is more advantageous for activating the conductivity of the control gate.
  • n-type doping is taken as an example.
  • the second fins 116 are ion-implanted, and the ion implantation may be performed by implanting arsenic (As ), a monument (P ), or a combination thereof, as shown in FIG. 4 . Show. Then, the mask layer on the first fin 114 is removed to form a device structure as shown in FIG.
  • Step 304 A floating gate 120 formed on the gate dielectric layer 118 and spanning the first fin 114 and the second fin 116.
  • the floating gate 120 may be a polysilicon gate or a metal gate.
  • the embodiment of the present invention is exemplified by a polysilicon gate. After depositing a polysilicon layer on the device shown in FIG. 5, the device is patterned, such as photolithographically bonded to RIE, to form a floating gate 120 as shown in FIG.
  • the polysilicon layer may be ALD CVD, high density plasma chemical vapor deposition (HDPCVD), sputtering, or other suitable method. The above process is merely an example and is not limited thereto.
  • the first fin is subjected to halo implantation and/or source/drain extension implantation.
  • a tilted ion implantation may be performed using a p-type dopant such as B BF 2 or a combination thereof to form a halo implantation region
  • a tilt ion implantation may be performed using an n-type dopant such as As P or a combination thereof to form a source/drain extension region.
  • sidewalls 122 are formed on both sides of the floating gate 120, as shown in Figure 8 (top view).
  • the sidewall spacers 122 may be composed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials, and combinations thereof, and/or other suitable materials, and the sidewall spacers may have a multilayer structure.
  • the appropriate dielectric material is deposited by ALD, plasma enhanced chemical vapor deposition (PECVD) or other methods, and combined with etching (such as RIE) to form sidewalls, the sidewall thickness can be 20-60
  • Step 305 forming source/drain regions in the first fins 114 on both sides of the floating gate 120.
  • a portion of the first fin 114 that is not covered by the floating gate 120 may be subjected to oblique ion implantation, and then annealed to activate the doped impurities to form source/drain regions.
  • an nMOSFET an n-type dopant such as As P or a combination thereof may be doped; for a pMOSFET, a p-type dopant such as B BF 2 In or a combination thereof may be doped.
  • a metal silicide for example, NiSi
  • a metal silicide for example, NiSi
  • a layer (such as a nitride stress layer), further forming a metal contact on the metal silicide, wherein the source/drain region contact 124 and the gate contact 126 are respectively as shown in FIG. 9 (top view), in the stress layer diagram Not shown.
  • the invention utilizes a FinFET device as a flash memory device, wherein the first fin is used as a flash memory channel, and the second fin is used as a control gate to span the polysilicon layer on the first fin and the second fin. Or the metal layer acts as a floating gate.
  • the FinFET flash device process is fully compatible with the FinFET logic device process while reducing manufacturing costs.

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Description

一种闪存器件及其形成方法
本申请要求于 2010 年 9 月 28 日提交中国专利局、 申请号为 201010296053.4、 发明名称为"一种闪存器件及其形成方法 "的中国专利申请的 优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体制造技术领域， 特别涉及一种具有 FinFET (鳍式场效 应晶体管） 结构的闪存器件及其形成方法。 背景技术
随着集成电路规模的不断扩大， 器件尺寸的不断缩小， 三维器件成为 半导体界发展的方向。 FinFET器件结构由于其良好的截止性能、 可扩展性 以及与常规制造工艺的兼容性而倍受关注。
对于目前的半导体技术发展， 在闪存器件中也开始引入鳍式结构。 闪 存器件是一种电写入和擦除数据的器件，其通过在控制栅极（ Control Gate )、 浮置栅极（ Floating Gate )和衬底之间形成介质层而形成串联的两个电容器， 即使在器件断电时也能在浮置栅极上保持电荷， 以提供存储功能。
然而， 目前的鳍式闪存器件工艺还不能与 FinFET的逻辑器件工艺兼容。 发明内容
本发明的目的旨在至少解决上述技术缺陷之一， 特别是提出一种与 FinFET器件兼容的 FinFET闪存器件及其制造工艺， 同时能够降低制造成本。
为达到上述目的， 本发明一方面提出一种闪存器件， 位于绝缘层之上， 包括： 第一鳍片和第二鳍片， 其中所述第二鳍片为所述器件的控制栅； 栅 介质层， 位于所述第一鳍片和第二鳍片的侧壁和顶部； 浮栅， 位于所述栅 介质层上且横跨所述第一鳍片和第二鳍片； 源 /漏区， 位于所述浮栅两侧的 所述第一鳍片内。
本发明另一方面还提出一种闪存器件的形成方法， 所述方法包括： 提 供衬底， 所述衬底包括绝缘层和半导体层， 所述半导体层位于所述绝缘层 上； 图案化所述半导体层以形成第一鳍片和第二鳍片； 在所述第一鳍片和 第二鳍片的侧壁及顶部形成栅介质层； 在所述栅介质层上形成横跨所述第 一鳍片和所述第二鳍片的浮栅； 在所述浮栅两侧的第一鳍片中形成源 /漏 区。
通过本发明提出的 FinFET闪存器件及其形成方法， 实现了 FinFET闪存 器件工艺与 FinFET逻辑器件工艺的完全兼容， 同时能够降低制造成本。
附图说明 通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1是根据本发明的实施例的 FinFET闪存器件的结构示意图； 图 2至图 9是根据本发明的实施例的闪存器件的制造方法中间步骤的 器件结构示意图。 具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结 构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以 在不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目 的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明 提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可以意 识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一 特征在第二特征之 "上" 的结构可以包括第一和第二特征形成为直接接触 的实施例， 也可以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接触。 图 1示出的是本发明的 FinFET闪存器件结构剖面图。该器件形成于绝 缘衬底上， 该绝缘体衬底可以包括绝缘层 112和半导体层 110 , 绝缘层 112 位于半导体层 110之上。 衬底材料实际运用中可以是任何绝缘体上半导体 ( SOI )衬底， 本发明实施例以绝缘体上硅衬底为例， 即半导体层 110为硅 层， 绝缘层 112为埋氧层 （BOX, 如 Si02 ) , BOX上的硅层可以直接形 成鳍片， 即硅鳍。
该器件包括形成于绝缘衬底上的第一鳍片 114和第二鳍片 116,其中第 一鳍片 114为闪存沟道， 第二鳍片 116为控制栅； 第一鳍片 114和第二鳍 片 116侧壁及顶部上的栅介质层 118; 形成于衬底 110上且横跨第一鳍片 114和第二鳍片 116的浮栅 120; 形成于第一鳍片 114两侧的源 /漏区。 其 中， 源 /漏区在图 1中未示出。
进一步地， 该器件还可以包括形成于第一鳍片 114与第二鳍片 116的 硅层上部的保护帽层 160。 优选地， 该器件还可以包括形成于所述浮栅两 侧的侧墙 122。 其中， 侧墙 122在图 1中未示出。
第二鳍片 116可以为 n型或 p型掺杂。 在本发明的实施例中， 第二鳍 片 116优选为 n型掺杂， 例如 P或 As离子都可以作为掺杂杂质。 n型掺杂 更有利于控制栅的导电性。
浮栅 120可以为多晶硅栅或金属栅。
优选地， 其中第一鳍片 114和第二鳍片 116平行排列于绝缘层上。
以下将结合附图详细介绍如图 1所示的闪存器件的形成方法， 当然本 发明可以采用不同于以下描述的步骤和工艺来形成所述闪存器件， 这些均 不脱离本发明的保护范围。
步骤 301 : 提供衬底， 如图 2所示， 所述衬底包括绝缘层 112和半导体 层 113 , 半导体层 113位于绝缘层 112之上。 该衬底可以是常规使用的任何 绝缘材料和半导体材料的如上构成， 但实际运用中， 可以直接采用 SOI衬底。 在本发明实施例中， 优选地， 以绝缘体上硅衬底为例， 包括底部硅层 110、 中 间埋氧层 （BOX, 如 Si02 ) 112 和顶部硅层 113 , 从而形成如图 2 所示的
Si/Si02/Si叠层。 步骤 302: 图案化硅层 113以形成第一鳍片 114和第二鳍片 116 , 其中 第一鳍片 114为所述器件的沟道， 第二鳍片 116为所述器件的控制栅。 可 选地，还可以在第一鳍片 114和第二鳍片 116上形成保护帽层 160。具体地， 首先在硅层 113上形成保护层， 其中， 所述保护层可以包括 Si3N4、 Si02、 SiOF、 SiCOH、 SiO、 SiCO、 SiCON和 SiON等绝缘材料中的任一种或多 种的组合， 通过常规的淀积工艺形成， 如物理气相淀积 (PVD)、 化学气相淀积 (CVD)、原子层淀积 (ALD)或溅射等工艺形成。然后，对上述结构进行构图（图 中未示出）， 例如， 通过在保护层上旋涂光刻胶、 曝光、 显影和刻蚀， 如反应 离子刻蚀 （RIE ), 使保护层和硅层 113 图案化为与将要形成的鳍片 （Fin )相 对应的形状， 并且刻蚀停止在 BOX层 112上， 然后去除光刻胶， 得到如图 3 所示的结构， 即刻蚀后硅层 113形成第一鳍片 114和第二鳍片 116, 刻蚀后所 述保护层形成位于所述第一鳍片 114和第二鳍片 116上的保护帽层 160。
步骤 303 : 在第一鳍片 114和第二鳍片 116的侧壁及顶部形成栅介质 层 118 , 如图 4所示。 在图 3所示的器件上沉积栅介质层 118。 栅介质层 118的厚度为 2-15nm。 栅介质层 118可包括氧化硅、 氮氧化硅或高 k材料， 高 k材料的例子包括例如铪基材料，如氧化铪（ Hf02 ) ,氧化铪硅（ HfSiO ) , 氮氧化铪硅 ( HfSiON ) , 氧化铪钽 ( HfTaO ) , 氧化铪钛 ( HfTiO ) , 氧 化铪锆 （HfZrO ) 其组合和 /或者其它适当的材料。 栅介质层 118可通过热 氧化、 CVD、 ALD等方法形成。 上述的工艺方法仅是示例， 本发明并不局 限于此。
之后， 进一步进行刻蚀， 具体地， 对栅介质层 118进行刻蚀， 例如可以 通过 RIE实现， 并且停止在 BOX层 112上。
可选地， 对第二鳍片 116进行 n型或 p型掺杂， 其中以 n型掺杂为优选， 更有利于激活控制栅的导电性， 本发明实施例即以 n型掺杂为例。 具体地， 对 第一鳍片 114进行掩模覆盖后， 对第二鳍片 116进行离子注入， 其中的离 子注入可以为砷（As )、 碑（P )或其组合进行注入， 如图 4所示。 然后， 去 除第一鳍片 114上的掩膜层， 形成如图 5所示的器件结构。 其中所述第二 鳍片 116为所述器件的控制栅， 第一鳍片 114为所述器件的沟道。 步骤 304: 形成于栅介质层 118上且横跨第一鳍片 114和第二鳍片 116 的浮栅 120。 浮栅 120可以为多晶硅栅或金属栅， 本发明的实施例以多晶 硅栅为例。 在图 5所示的器件上沉积多晶硅层后， 对上述器件进行图案化， 如光刻结合 RIE, 以形成如图 6所示的浮栅 120。 在本实施例中， 多晶硅层 可使用 ALD CVD、 高密度等离子体化学气相沉积（HDPCVD ) 、 溅射或 其他合适的方法。 上述的工艺方法仅仅是作为示例， 不局限于此。
之后可选地， 如图 7所示， 对第一鳍片进行晕圈注入和 /或源 /漏延伸区 注入。 例如， 可以采用 p型掺杂剂例如 B BF2 或其组合进行倾角离子注入 以形成晕圈注入区， 采用 n型掺杂剂例如 As P或其组合进行倾角离子注入 以形成源 /漏延伸区。
之后可选地， 在浮栅 120两侧形成侧墙 122 , 如图 8 (俯视图 ) 所示。 侧墙 122可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 氟化物掺杂硅玻璃、 低 k电介质材料及其组合，和 /或其他合适的材料，侧墙可以具有多层结构， 通过包括 ALD、 等离子增强化学气相沉积（PECVD )或其他方法沉积合适 的电介质材料， 并结合刻蚀 （例如 RIE ) 以形成侧墙， 侧墙厚度可以为 20-60
步骤 305 : 在浮栅 120两侧的第一鳍片 114中形成源 /漏区。 例如， 可 以向第一鳍片 114中未被浮栅 120覆盖的部分进行倾角离子注入， 然后退火 以激活所掺杂的杂质， 以形成源 /漏区。 对于 nMOSFET, 可以采用 n型掺杂剂 例如 As P或其组合掺杂； 对于 pMOSFET, 可以采用 p型掺杂剂例如 B BF2 In或其组合掺杂。
接着可选地， 采用 CMOS常规工艺在第一鳍片 114的源 /漏区接触部分 和第二鳍片 116的栅极接触部分分别形成金属硅化物 （例如 NiSi ) , 在所 述器件表面形成应力层 （如氮化物应力层） ， 在所述金属硅化物上进一步 形成金属接触， 其中， 源 /漏区接触 124、 栅极接触 126分别如图 9 (俯视 图） 所示， 所述应力层图中未示出。
本发明是利用 FinFET器件作为闪存器件， 其中， 以第一鳍片作为闪存 沟道， 以第二鳍片作为控制栅， 以横跨第一鳍片和第二鳍片上的多晶硅层 或金属层作为浮栅。通过采取该工艺，实现了 FinFET 闪存器件工艺与 FinFET 逻辑器件工艺的完全兼容， 同时能够降低制造成本。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。任何熟 悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭 示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为 等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发 明的技术实质对以上实施例所做的任何筒单修改、等同变化及修饰， 均仍属于 本发明技术方案保护的范围内。
本发明说明书中各个实施例采用递进的方式描述，每个实施例重点说明的 都是与其他实施例的不同之处， 各个实施例之间相同相似部分互相参见即可。 对所公开的实施例的上述说明， 使本领域专业技术人员能够实现或使用本发 明。 对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的， 本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它 实施例中实现。 因此， 本发明将不会被限制于本文所示的这些实施例， 而是要 符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims

权 利 要 求
1. 一种闪存器件， 位于绝缘层之上， 包括：
第一鳍片和第二鳍片， 其中所述第二鳍片为所述器件的控制栅； 栅介质层， 位于所述第一鳍片和第二鳍片的侧壁和顶部；
浮栅， 位于所述栅介质层上且横跨所述第一鳍片和第二鳍片； 源 /漏区， 位于所述浮栅两侧的所述第一鳍片内。
2. 根据权利要求 1所述的闪存器件， 还包括形成于所述浮栅两侧的侧 墙。
3. 根据权利要求 1所述的闪存器件， 其中所述第二鳍片为 n型或 p型 掺杂。
4. 根据权利要求 1所述的闪存器件， 其中所述浮栅为多晶硅栅或金属 栅。
5. 根据权利要求 1 所述的闪存器件， 其中所述第一鳍片和第二鳍片的顶 部有保护帽层。
6. 根据权利要求 1 所述的闪存器件， 其中所述第一鳍片和第二鳍片平行 排列于所述绝缘层上。
7. 根据权利要求 1-6中任一项所述闪存器件， 其中所述绝缘层为绝缘体 上半导体中的绝缘层，所述第一鳍片和第二鳍片由绝缘体上半导体的顶层半导 体形成。
8. 一种闪存器件的形成方法， 所述方法包括：
提供衬底， 所述衬底包括绝缘层和半导体层， 所述半导体层位于所述 绝缘层上；
图案化所述半导体层以形成第一鳍片和第二鳍片；
在所述第一鳍片和第二鳍片的侧壁及顶部形成栅介质层；
在所述栅介质层上形成横跨所述第一鳍片和所述第二鳍片的浮栅； 在所述浮栅两侧的第一鳍片中形成源 /漏区。
9. 根据权利要求 8所述的方法， 在形成所述浮栅后， 还包括在所述浮 栅两侧形成侧墙。
10. 根据权利要求 8所述的方法， 其中， 在所述第一鳍片和第二鳍片 的侧壁及顶部形成栅介质层之前， 所述方法进一步包括：
对所述第二鳍片进行 n型或 p型掺杂。
11. 根据权利要求 8所述的方法， 其中所述图案化所述半导体层以形 成第一鳍片和第二鳍片的步骤包括：
在所述半导体层上形成保护层；
对所述半导体层和保护层构图， 形成与将要形成的鳍片相对应的图案； 对所述半导体层和保护层进行刻蚀，所述半导体层形成第一鳍片和第二鳍 片， 所述保护层形成位于所述第一鳍片和第二鳍片上的保护帽层。
12. 根据权利要求 8-11中任一项所述的方法， 其中在所述栅介质层上 形成横跨所述第一鳍片和所述第二鳍片的浮栅的步骤之后还包括：
对所述第一鳍片进行倾角离子注入以形成晕圈注入区； 和 /或
对所述第一鳍片进行倾角离子注入以形成源 /漏延伸区。
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