CN101322239A - 同一个衬底上具有相同导电类型的低和高性能器件的半导体器件结构 - Google Patents

同一个衬底上具有相同导电类型的低和高性能器件的半导体器件结构 Download PDF

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CN101322239A
CN101322239A CNA200680045213XA CN200680045213A CN101322239A CN 101322239 A CN101322239 A CN 101322239A CN A200680045213X A CNA200680045213X A CN A200680045213XA CN 200680045213 A CN200680045213 A CN 200680045213A CN 101322239 A CN101322239 A CN 101322239A
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grid
effect transistor
field
semiconductor device
distance piece
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J·阿诺德
D·查尔达姆巴劳
李瑛�
拉齐夫·马利克
施里施·纳拉西姆哈
S·潘达
B·特希尔
R·维斯
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Abstract

一种用于制作半导体器件结构的方法，包括：提供衬底(10)；在衬底上形成具有第一间隔件(SP)的第一栅极(G1)、具有第二间隔件(SP)的第二栅极(G2)、分别与第一栅极和第二栅极相邻的相同导电类型的各个源极(S)和漏极(D)区域、设置在第一栅极和第二栅极中间的隔离区域(STI)、以及在第一栅极、第二栅极和各个源极与漏极区域上的硅化物；在第一间隔件上形成附加间隔件(RSPS)，以产生中间结构，然后在整个中间结构上设置应力层。

Description

同一个衬底上具有相同导电类型的低和高性能器件的半导体器件结构
技术领域
本发明涉及用于制作金属氧化物半导体(MOS)器件结构的方法，更具体地，涉及用于使用间隔件和膜来影响MOS场效应晶体管(例如，nFET、pFET)的沟道应力和性能的方法，并且涉及最终得到的器件结构。
背景技术
MOSFET及其各种制造方法是熟知的。典型地，MOSFET包括在适当的衬底中或衬底上形成的表面处的源极和漏极区域、以及设置在它们之间的栅极。在栅极上以及在源极和漏极区域上形成硅化物电层或接触件。通常，典型的已知硅化工艺为如下：进行源极和漏极注入，随后进行金属沉积，然后退火使金属和被注入或掺杂的硅起反应以形成硅化物。衬底包括，尤其是例如，块体半导体(例如，硅)、绝缘体上硅衬底(SOI)。例如，参阅Rausch等人的、在2005年8月16日授权的美国专利No.6,930,030B2，“METHOD OF FORMING ANELECTRONIC DEVICE ON A RECESS IN THE SURFACE OFTHIN FILM OF SILICON ETCHED TO A PRECISETHICKNESS”，通过引用将其全部内容合并于此。`030专利的图2M，在此局部复制为图8，示出了在SOI衬底中形成的nFET器件20的多晶硅栅极44的上表面上设置的硅化物层/接触件54。图中还示出了被设置在栅极的下面的氧化物层42和被设置在栅极的侧壁的间隔件48。
在CMOS技术中，nFET和pFET器件被最优化，以达到所需要的CMOS性能。因此，非常不同的掺杂剂物质被用于nFET器件和pFET器件。这些物质具有非常不同的物理特性，如扩散速率和最大活性浓度。在传统的CMOS技术中，nFET和pFET通常共享相同的间隔件处理和拓扑结构。为了使得CMOS性能最优化，间隔件典型地可以具有一个最大宽度，并被设计成在nFET和pFET之间对性能进行折衷。例如，如果分别用砷和硼作为用于nFET和pFET的源极和漏极掺杂剂，则已知，对于nFET而言间隔件越窄越好，但对于pFET而言间隔件越宽越好，这是因为与硼相比砷扩散慢得多。在这种情形下，pFET是限制因素。因此，将所有间隔件的最大宽度针对pFET而最优化，对nFET的性能进行折衷。
还知道通过提供以下条件来增强n型场效应晶体管器件(nFET)和p型场效应晶体管器件(pFET)的性能：nFET沟道的拉伸应力和pFET沟道的压缩应力，和/或不同的间隔件宽度，以便控制硅化物到例如沟道的距离。
例如，参阅Chidambarrao等人的、在2003年9月22日提交、2005年3月22日授权的美国专利No.6,869,866 B1，“SILICIDEPROXIMITY STRUCTURES FOR CMOS DEVICEPERFORMANCE IMPROVEMENTS”；Chidambarrao等人的、在2003年9月10日提交、2005年5月10日授权的美国专利No.6,890,808B2，“METHOD AND STRUCTURE FOR IMPROVED MOSFETSUSING POLY/SILICIDE GATE HEIGHT CONTROL”；和Fung等人的、在2002年10月21日提交、2004年10月19日授权的美国专利No.6,806,584 B2，“SEMICONDUCTOR DEVICE STRUCTUREINCLUDING MULTIPLE FETS HAVING DIFFERENT SPACERWIDTHS”，通过引用将所有这些专利的全部内容合并于此。
然而，本发明人相信，按照现有技术的方法和最终得到的器件结构还可以进一步改进，以在同一个衬底上提供相同导电类型的低和高性能器件。
发明内容
本发明的第一方面提供了一种用于在一个衬底上制作相同导电类型的低性能半导体器件和高性能半导体器件的方法，该方法容易与传统的用于制作半导体器件结构的工艺兼容。
本发明的第二方面提供了一种包括都由nFET形成的低性能半导体器件和高性能半导体器件的半导体器件结构。
本发明的第三方面提供了一种包括都由pFET形成的低性能半导体器件和高性能半导体器件的半导体器件结构。
根据本发明的一个实施例，一种用于制作半导体器件结构的方法包括：提供衬底，在衬底上形成具有第一间隔件的第一栅极、具有第二间隔件的第二栅极、与第一栅极和第二栅极相邻的相同导电类型的各个源极和漏极区域、被设置在第一栅极和第二栅极中间的隔离区域、在第一栅极、第二栅极和各个源极与漏极区域上的硅化物，仅在第一间隔件上形成附加间隔件，产生中间结构，然后在整个中间结构上设置应力层。
按照另一个实施例，本发明提供了一种包括被设置在同一个衬底上的第一场效应晶体管和第二场效应晶体管的半导体器件结构，该晶体管具有相同导电类型，并包括各自的侧壁间隔件、仅仅被设置在第一场效应晶体管的侧壁间隔件上的附加间隔件、以及被设置在第一场效应晶体管、附加间隔件和第二场效应晶体管上的应力膜，以使得在第一场效应晶体管的沟道中引起的最大应力与在第二场效应晶体管的沟道中引起的最大应力不同。
在本发明的一个优选实施例中，第一场效应晶体管的沟道中引起的最大应力小于第二场效应晶体管的沟道中引起的最大应力。
当结合以下的附图参阅以下的详细说明时，将更容易明白本发明的附加特性和优点。
附图说明
下面参考附图，作为例子，更详细地描述本发明的实施例，图中：
图1至图5是当被用来制作包括具有各自的沟道C的两个nFET的两个器件结构时，根据本发明的一个优选实施例的、从各个相继的步骤得到的相继半导体器件结构的示意性侧视图；侧壁间隔件SP和附加间隔件RSPS具有组合的最大宽度W。
图6是示出对于90nm技术和50nm 1.2GPa应力膜30，在一个器件的沟道中最大的最终得到的应力与附加间隔件RSPS和传统的侧壁间隔件(SP)的组合的最大宽度(2w)之间的关系的、具有说明性图注的图。
图7是根据本发明的、包括两个pFET的半导体器件结构的示意性侧视图。
图8是按照现有技术的nFET的示意性侧视图。
具体实施方式
现在参考图1-7描述本发明的用于制作包括两个nFET的半导体器件结构的优选实施例和最好模式。然而，本领域技术人员考虑到现在的公开内容，将会理解，本申请人的方法可应用于制作包括两个pFET的半导体器件结构。
首先，参考图1，提供衬底10，在其上形成了：具有第一侧壁间隔件SP的第一栅极G1；具有第二侧壁间隔件SP的第二栅极G2；与第一栅极和第二栅极相邻地形成并被适当地注入的各个源极和漏极区域S、D；设置在第一栅极G1和第二栅极G2中间的隔离区域STI；以及设置在第一栅极、第二栅极和各个源极与漏极区域上的硅化物。
半导体衬底10例如是块体硅(Si)衬底或绝缘体上硅(SOI)衬底。可替换地，衬底10是包括多于一个表面取向的混合衬底。可替换地，衬底包括除Si以外的半导体材料，如Ge，或III-V族元素或II-V族元素的任何组合。
在(传统的)初始衬底清洗工艺之后，进行隔离方案。正如在半导体制造中熟知的，隔离方案用来使得所选择的半导体器件彼此电分离。隔离方案是标准的或经修改的浅沟槽隔离(STI)方案。图1中示出了隔离区域STI。可替换地，通过使用LOCOS处理或台面隔离方案而实现隔离，正如在制造半导体器件的技术中所熟知的。对于制造半导体器件的各种已知的或传统的工艺，例如参阅S.M.Sze著，VLSITechnology(VLSI技术)，第2版(McGraw Hill Publishing Co.，1988)。
在形成隔离区域STI后，执行传统的栅极氧化物预清洗处理。通常，在已知的高性能(例如，逻辑)或低性能(例如，存储器或模拟)制造工艺中，可以使用各种传统栅极氧化物工艺来制造具有不同栅极氧化物厚度的器件。例如通过使用传统的热氧化处理来形成栅极氧化物3。可以通过使用N2O、NO、O2或它们的任何组合来形成栅极氧化物3。可以通过使用传统的等离子体处理来形成氧化物3。可替换地，通过使用基础氧化物，随后沉积诸如氧化铝或氧化铪的高k栅极电介质材料或另一种高k栅极电介质，来形成栅极氧化物3。栅极电介质材料例如具有从约(+10％)0.6nm到约7nm的范围内选择的一个近似(+10％)均匀的厚度。
接着，按传统方式形成栅电极或栅极G1、G2。优选地，每个栅极G1、G2由通过使用诸如硅烷(SiH4)的反应性气体进行的低压化学汽相沉积(LPCVD)而沉积的多晶硅层(未示出)形成。该层的厚度在约1000至3000埃之间。然后，该层通过离子注入砷(As75)或磷(P31)而被导电地掺杂为n型。在注入后，层的最终掺杂剂浓度优选地在约1.0×1018至1.0×1021离子/cm3之间。使用传统的光刻技术和各向异性等离子体蚀刻来对多晶硅层形成图案，这包括在器件区域上形成栅电极。通过使用反应离子蚀刻(RIE)或高密度等离子体(HDP)蚀刻和诸如氯(Cl2)的蚀刻气体而对多晶硅层进行等离子体蚀刻。
在例如通过在氧(O2)中的等离子体蚀刻而去除光致抗蚀剂掩模(未示出)之后，通过使用诸如As或P的第二导电类型掺杂剂的离子注入，在与所述栅电极相邻的器件区域中形成轻掺杂的源极和漏极(LDD)或延伸区域(未示出)。多晶硅侧壁再氧化或偏移间隔件可用来偏移LDD注入。典型地，LDD区域被掺杂到在约1.0×1019至5.0×1020原子/cm3之间的浓度。接着，通过使用传统技术沉积保形的绝缘层(未示出)，并对其进行各向异性等离子体回蚀刻，以在栅电极G1、G2的侧壁上形成侧壁间隔件SP。
典型地，绝缘层是氧化硅(SiO2)，它是通过使用四乙氧基硅烷(TEOS)作为反应性气体进行低压CVD(LPCVD)而沉积的，并且被沉积到约200至1000埃的优选的厚度。其它可选项包括氮化物间隔件或具有氮化物和氧化物材料的多个间隔件的组合。
然后，通过使用RIE和诸如四氟化碳(CF4)和氢H2或甲基氟(CHF3)的蚀刻气体而进行传统回蚀刻，这选择性地蚀刻SiO2层到硅衬底和多晶硅栅电极。然后，通过离子注入诸如砷的第二导电类型掺杂剂，在与绝缘侧壁间隔件SP相邻的器件区域中形成重掺杂的源极和漏极接触区域S、D。接触区域被掺杂到1.0×1018至1.0×1021原子/cm3之间的最终浓度。例如通过使用在稀释的氢氟酸溶液中进行的浸渍蚀刻来去除保留在源极和漏极接触区域和多晶硅栅电极的暴露上表面上的任何剩余的本征氧化物。
然后以任何传统的方式将两个nFET硅化，使得在如图1所示的位置处形成硅化物。图1的结构的更多细节例如在图8中示出的现有技术nFET器件结构中示出，并已在先前通过引用合并于此的美国专利6,930,030 B2中描述。
以上对于图1的说明是关于nFET的。当然，本领域技术人员考虑到现在的公开内容，将会理解，当使用pFET时，掺杂杂质的极性类型被颠倒，并且在处理期间需要传统的掩模、图案形成等等。
接着，参考图2，在衬底10上沉积第一保形电介质层或膜20。更具体地，该层20被沉积在具有第一间隔件SP的硅化的第一栅极、具有第二间隔件SP的硅化的第二栅极、硅化的各个源极与漏极区域、和隔离区域STI上。层20优选地是氮化硅，并被沉积成从约20纳米到约70纳米的厚度范围内选择的一个近似(±10％)均匀的厚度。例如，可以通过CVD、HDP、ALD或其它传统的沉积技术来沉积Si3N4。
接着，参考图3，覆盖被设置在具有第一间隔件SP的硅化的第一栅极G1、硅化的各个源极与漏极区域S，D、和STI区域的一部分上的电介质层20。例如借助于沉积传统的光致抗蚀剂掩模(未示出)而完成覆盖。
然后，从未被覆盖的区域(即，具有间隔件的硅化的第二栅极G2、硅化的各个源极与漏极区域、和STI区域的一部分)去除层20。图3示出了所得到的结构。例如借助于传统的RIE完成去除。接着，通过使用诸如剥离或蚀刻的任何传统技术去除光致抗蚀剂掩模(未示出)。
在去除光致抗蚀剂掩模之后，覆盖具有间隔件的硅化的栅极G2、相邻的硅化区域S，D、和STI区域的另一部分。使用传统的光致抗蚀剂掩模(未示出)来覆盖硅化的栅极G2等等。然后，如图4所示，从硅化的栅极G1、硅化的S，D、STI和间隔件SP，除了层20的被设置在间隔件SP上的一部分以外，选择性地去除层20，从而仅仅在具有硅化的栅极G1的nFET的间隔件SP上形成附加间隔件或相反应力相邻间隔件RSPS。优选地，对于一个器件，间隔件RSPS与侧壁间隔件SP的组合最大宽度(2w)不大于50nm(对于90nm工艺技术)，或不大于30nm(对于65nm工艺技术)。借助于诸如RIE的任何传统的蚀刻来实施层20的去除。
在形成附加的间隔件RSPS之后，在整个中间结构上沉积适当的应力膜或层30，以形成图5所示的半导体器件结构。层30例如是氮化硅或碳化硅，并且保形地沉积到从约10nm到约100nm的厚度范围内选择的近似(±10％)均匀的厚度。对于各种应力膜或层的成分和沉积离子技术，例如参阅：F.Ootsuka等，“A Highly Dense，High-Performance 130nm Node CMOS Technology for Large ScaleSystem-on-a-Chip Applications”，IEDM，2000，第23.5.1-23.5.4页。
因此，通常，根据本发明的方法在硅化后在FET上选择性地形成间隔件RSPS，以控制应力衬垫/层的相邻性，从而控制FET器件的迁移率/驱动电流。
层30、侧壁间隔件SP和附加间隔件RSPS有助于在具有硅化的栅极G1的器件的沟道C中创建适当的第一应力。例如，参阅图6。正如从图5和图6理解的，第一应力不同于(优选地小于)在具有硅化的栅极G2的器件的沟道C中创建的应力。
图7是最终得到的包括具有硅化的栅极G11，G12的两个pFET、仅仅被设置在栅极G11的侧壁间隔件上的间隔件RSPS、和被设置在整个结构上的应力层300的半导体器件结构的示意图。
虽然参考本发明的优选实施例具体地示出和描述了本发明，但是本领域技术人员将理解，可以在形式和细节上作出各种改变而不脱离本发明的范围。

Claims (20)

1.一种用于制作半导体器件结构的方法，包括：
提供衬底；
在衬底上形成具有第一间隔件的第一栅极、具有第二间隔件的第二栅极、分别与第一栅极和第二栅极相邻的相同导电类型的各个源极和漏极区域、设置在第一栅极和第二栅极中间的隔离区域、以及硅化物，所述硅化物位于第一栅极、第二栅极以及各个源极和漏极区域上；
仅在第一间隔件上形成附加间隔件，以产生中间结构，然后在整个中间结构上设置应力层。
2.如权利要求1所述的方法，所述形成附加间隔件的步骤还包括：
在具有第一间隔件的硅化的第一栅极、具有第二间隔件的硅化的第二栅极、硅化的各个源极和漏极区域、和隔离区域上设置第一电介质层；以及
覆盖设置在具有第一间隔件的硅化的第一栅极、与第一栅极相邻的硅化的各个源极和漏极区域、和隔离区域的一部分上的第一电介质层，然后从该结构的没有被所述覆盖步骤覆盖的部分去除第一电介质层。
3.如权利要求2所述的方法，所述去除步骤包括：从所述结构的没有被所述覆盖步骤覆盖的部分对第一电介质层进行各向异性蚀刻。
4.如权利要求2所述的方法，还包括：
使设置在具有间隔件的硅化的第一栅极、与第一栅极相邻的硅化的各个源极和漏极区域、和隔离区域的所述部分上的第一电介质层不被覆盖；
覆盖设置在具有第二间隔件的硅化的第二栅极、与第二栅极相邻的硅化的各个源极和漏极区域、和隔离区域的另一部分上的第二电介质层；以及然后
除了设置在第一间隔件上的特定部分之外，去除第一电介质层，以形成附加间隔件。
5.如权利要求3所述的方法，所述各向异性蚀刻的步骤包括对第一电介质层进行反应离子蚀刻。
6.如权利要求1所述的方法，其中所述第一间隔件具有不大于60纳米的最大宽度。
7.如权利要求1所述的方法，其中每个所述附加间隔件具有从包含15nm、30nm和50nm的组中选择的最大宽度。
8.如权利要求1所述的方法，所述设置应力层的步骤还包括沉积从主要包含氮化硅和碳化硅的组中选择的应力层。
9.如权利要求2所述的方法，所述设置第一电介质层的步骤还包括沉积从主要包含氮化硅、碳化硅和二氧化硅的组中选择的第一电介质层。
10.如权利要求2所述的方法，其中第一间隔件和第一电介质层总共具有不大于70纳米的最大宽度。
11.如权利要求1所述的方法，其中所述相同导电类型是n型。
12.如权利要求1所述的方法，其中所述相同导电类型是p型。
13.一种半导体器件结构，包括：
设置在同一个衬底上的第一场效应晶体管和第二场效应晶体管，所述第一场效应晶体管和第二场效应晶体管具有相同导电类型并包括各自的侧壁间隔件；
仅设置在第一场效应晶体管的侧壁间隔件上的附加间隔件和设置在第一场效应晶体管、所述附加间隔件以及第二场效应晶体管上的应力膜，使得第一场效应晶体管的沟道中引起的最大应力与第二场效应晶体管的沟道中引起的最大应力不同。
14.如权利要求13所述的半导体器件结构，其中第一场效应晶体管的沟道中引起的最大应力小于第二场效应晶体管的沟道中引起的最大应力。
15.如权利要求13所述的半导体器件结构，其中第一场效应晶体管是第一nFET，以及第二场效应晶体管是第二nFET。
16.如权利要求13所述的半导体器件结构，其中第一场效应晶体管是第一pFET，以及第二场效应晶体管是第二pFET。
17.如权利要求13所述的半导体器件结构，其中所述附加间隔件和所述应力膜主要包含氮化硅。
18.如权利要求13所述的半导体器件结构，其中所述附加间隔件的化学成分不同于所述应力膜的化学成分。
19.如权利要求13所述的半导体器件结构，其中每个所述附加间隔件包括多个整体部分。
20.如权利要求19所述的半导体器件结构，其中所述多个是两个。
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US20070158753A1 (en) 2007-07-12
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