JPS6476755A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6476755A
JPS6476755A JP62232209A JP23220987A JPS6476755A JP S6476755 A JPS6476755 A JP S6476755A JP 62232209 A JP62232209 A JP 62232209A JP 23220987 A JP23220987 A JP 23220987A JP S6476755 A JPS6476755 A JP S6476755A
Authority
JP
Japan
Prior art keywords
channel
face
current flows
becomes minimum
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62232209A
Other languages
Japanese (ja)
Inventor
Akio Yasukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62232209A priority Critical patent/JPS6476755A/en
Publication of JPS6476755A publication Critical patent/JPS6476755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the characteristics fluctuation due to stress applied from resin, and stabilize characteristics, by using a silicon substrate of face 110, and arranging a P-channel FET element in a manner in which the channel current flows in a specific direction. CONSTITUTION:A silicon substrate 1 of face 110 is used. The source electrode 5, the gate electrode 6, and the drain electrode 7 of a P-channel FET are arranged in the direction <110>, and the P-channel current flows in the direction <110>. The source electrode 10, the gate electrode 11 and the drain electrode 12 of an N-channel FET are arranged in the direction <110>, and the N- channel current flows in the direction <110>. As the result of characteristics fluctuation caused by the stress of a resin-seal type FET element, an important piezoelectric resistance coefficient pi55' becomes minimum in the direction <110> of face 110 in the case of P-channel, and pi55' of N-channel becomes minimum in the direction <110> of face 110. Since characteristics fluctuation due to stress becomes minimum, stable characteristics are obtained.
JP62232209A 1987-09-18 1987-09-18 Semiconductor device Pending JPS6476755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62232209A JPS6476755A (en) 1987-09-18 1987-09-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232209A JPS6476755A (en) 1987-09-18 1987-09-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6476755A true JPS6476755A (en) 1989-03-22

Family

ID=16935695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232209A Pending JPS6476755A (en) 1987-09-18 1987-09-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6476755A (en)

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615668B2 (en) 2000-10-27 2003-09-09 Denso Corporation Semiconductor pressure sensor having signal processor circuit
US7144767B2 (en) 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US7148559B2 (en) * 2003-06-20 2006-12-12 International Business Machines Corporation Substrate engineering for optimum CMOS device performance
US7202513B1 (en) 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7202132B2 (en) 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US7205207B2 (en) 2003-10-16 2007-04-17 International Business Machines Corporation High performance strained CMOS devices
US7224033B2 (en) 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
JP2007141977A (en) * 2005-11-16 2007-06-07 Matsushita Electric Ind Co Ltd Semiconductor device
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7297601B2 (en) 2003-09-09 2007-11-20 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
WO2007142107A1 (en) * 2006-06-07 2007-12-13 Sharp Kabushiki Kaisha Power ic device and method for manufacturing same
US7388259B2 (en) 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US7452761B2 (en) 2004-02-27 2008-11-18 International Business Machines Corporation Hybrid SOI-bulk semiconductor transistors
JP2009521808A (en) * 2005-12-22 2009-06-04 ビシェイ−シリコニクス High mobility power metal oxide semiconductor field effect transistor
US7544577B2 (en) 2005-08-26 2009-06-09 International Business Machines Corporation Mobility enhancement in SiGe heterojunction bipolar transistors
US7615435B2 (en) 2007-07-31 2009-11-10 International Business Machines Corporation Semiconductor device and method of manufacture
US7635620B2 (en) 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US7709317B2 (en) 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US7741185B2 (en) 2005-03-29 2010-06-22 Fujitsu Semiconductor Limited Method of manufacturing semiconductor device
US7776695B2 (en) 2006-01-09 2010-08-17 International Business Machines Corporation Semiconductor device structure having low and high performance devices of same conductive type on same substrate
US7785950B2 (en) 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
WO2010116587A1 (en) * 2009-04-09 2010-10-14 パナソニック株式会社 Semiconductor device and method of producing same
US7964865B2 (en) 2003-09-23 2011-06-21 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
US8183643B2 (en) 2000-09-28 2012-05-22 Oki Semiconductor Co., Ltd. Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane
US8853746B2 (en) 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US9006836B2 (en) 2004-01-16 2015-04-14 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US9053970B2 (en) 2004-07-23 2015-06-09 International Business Machines Corporation Patterned strained semiconductor substrate and device
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
US9887266B2 (en) 2006-03-21 2018-02-06 Vishay-Siliconix Ultra-low drain-source resistance power MOSFET

Cited By (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8183643B2 (en) 2000-09-28 2012-05-22 Oki Semiconductor Co., Ltd. Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane
US6615668B2 (en) 2000-10-27 2003-09-09 Denso Corporation Semiconductor pressure sensor having signal processor circuit
US7388259B2 (en) 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US7148559B2 (en) * 2003-06-20 2006-12-12 International Business Machines Corporation Substrate engineering for optimum CMOS device performance
US7482216B2 (en) 2003-06-20 2009-01-27 International Business Machines Corporation Substrate engineering for optimum CMOS device performance
US7297601B2 (en) 2003-09-09 2007-11-20 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US7410846B2 (en) 2003-09-09 2008-08-12 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US7964865B2 (en) 2003-09-23 2011-06-21 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
US7144767B2 (en) 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US7205207B2 (en) 2003-10-16 2007-04-17 International Business Machines Corporation High performance strained CMOS devices
US7202132B2 (en) 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US9006836B2 (en) 2004-01-16 2015-04-14 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US7767503B2 (en) 2004-02-27 2010-08-03 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7923782B2 (en) 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7452761B2 (en) 2004-02-27 2008-11-18 International Business Machines Corporation Hybrid SOI-bulk semiconductor transistors
US9515140B2 (en) 2004-07-23 2016-12-06 Globalfoundries Inc. Patterned strained semiconductor substrate and device
US9053970B2 (en) 2004-07-23 2015-06-09 International Business Machines Corporation Patterned strained semiconductor substrate and device
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7224033B2 (en) 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
US7741185B2 (en) 2005-03-29 2010-06-22 Fujitsu Semiconductor Limited Method of manufacturing semiconductor device
US7544577B2 (en) 2005-08-26 2009-06-09 International Business Machines Corporation Mobility enhancement in SiGe heterojunction bipolar transistors
US7202513B1 (en) 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7785950B2 (en) 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
US7709317B2 (en) 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US8686544B2 (en) 2005-11-16 2014-04-01 Panasonic Corporation Semiconductor device
JP2007141977A (en) * 2005-11-16 2007-06-07 Matsushita Electric Ind Co Ltd Semiconductor device
JP2009521808A (en) * 2005-12-22 2009-06-04 ビシェイ−シリコニクス High mobility power metal oxide semiconductor field effect transistor
US9425043B2 (en) 2005-12-22 2016-08-23 Vishay-Siliconix High mobility power metal-oxide semiconductor field-effect transistors
US9437424B2 (en) 2005-12-22 2016-09-06 Vishay-Siliconix High mobility power metal-oxide semiconductor field-effect transistors
US7776695B2 (en) 2006-01-09 2010-08-17 International Business Machines Corporation Semiconductor device structure having low and high performance devices of same conductive type on same substrate
US7635620B2 (en) 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US9887266B2 (en) 2006-03-21 2018-02-06 Vishay-Siliconix Ultra-low drain-source resistance power MOSFET
US7902595B2 (en) 2006-06-07 2011-03-08 Sharp Kabushiki Kaisha Power IC device and method of manufacturing same
WO2007142107A1 (en) * 2006-06-07 2007-12-13 Sharp Kabushiki Kaisha Power ic device and method for manufacturing same
US8853746B2 (en) 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US7615435B2 (en) 2007-07-31 2009-11-10 International Business Machines Corporation Semiconductor device and method of manufacture
WO2010116587A1 (en) * 2009-04-09 2010-10-14 パナソニック株式会社 Semiconductor device and method of producing same

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