CN106206577A - 用于FinFET器件的方法和结构 - Google Patents
用于FinFET器件的方法和结构 Download PDFInfo
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- CN106206577A CN106206577A CN201510216889.1A CN201510216889A CN106206577A CN 106206577 A CN106206577 A CN 106206577A CN 201510216889 A CN201510216889 A CN 201510216889A CN 106206577 A CN106206577 A CN 106206577A
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了半导体器件及其形成方法。该器件包括半导体衬底,半导体衬底包括第一半导体材料并且具有多个隔离部件,从而限定第一有源区和第二有源区;第一鳍式半导体部件,包括第二半导体材料并且形成在第一有源区中;以及第二鳍式半导体部件,包括第二半导体材料并且形成在第二有源区中。第一鳍式半导体部件是拉伸应变的并且第二鳍式半导体部件是压缩应变的。本发明涉及用于FinFET器件的方法和结构。
Description
技术领域
本发明涉及用于FinFET器件的方法和结构。
背景技术
半导体集成电路(IC)产业经历了指数式发展。IC材料和设计中的技术进步已经产生了数代的IC,其中每代IC都具有比上一代IC更小和更复杂的电路。在IC发展过程中,功能密度(即,每一芯片面积上互连器件的数量)通常已经增加而几何尺寸(即,使用制造工艺可以制造的最小的部件(或线))却已减小。通常这种按比例缩小工艺通过提高生产效率和降低相关成本而带来益处。这种按比例缩小工艺也增加了处理和制造IC的复杂度。
由于包括促进按比例缩小工艺的多种原因,诸如鳍式场效应晶体管(FinFET)的三维器件由于它们相比于传统的平面器件的高驱动电流和小覆盖区已被开发。诸如这样的器件具有与其相关联的独特的考虑,并且期望这一领域的改进。
发明内容
为了解决现有技术中存在的问题,根据本发明的一个方面,提供了一种半导体结构,包括:衬底,包括第一半导体材料并且具有第一有源区和第二有源区;第一鳍式半导体部件,包括第二半导体材料并且形成在所述第一有源区中;以及第二鳍式半导体部件,包括所述第二半导体材料并且形成在所述第二有源区中,其中,所述第一鳍式半导体部件是拉伸应变的并且所述第二鳍式半导体部件是压缩应变的。
在上述半导体结构中,所述第一半导体材料与所述第二半导体材料不同。
在上述半导体结构中,所述第二半导体材料是具有比Si更高的迁移率的任何半导体材料。
在上述半导体结构中,所述第二半导体材料选自由SiGe、Ge、GeSn、InGaP、InAs、InP、InGaAs、GaAs、InSb、GaSb、和AlGaAs组成的组。
在上述半导体结构中,还包括:第一应变松弛缓冲部件和第二应变松弛缓冲部件,所述第一应变松弛缓冲部件和所述第二应变松弛缓冲部件分别形成在所述第一有源区和所述第二有源区内,从而使得所述第一应变松弛缓冲部件位于所述第一鳍式半导体部件和所述衬底之间,并且所述第二应变松弛缓冲部件位于所述第二鳍式半导体部件和所述衬底之间,其中,所述第一应变松弛缓冲部件和所述第二应变松弛缓冲部件均包括第三半导体材料。
在上述半导体结构中,所述第一半导体材料、所述第二半导体材料和所述第三半导体材料均彼此不同。
在上述半导体结构中,所述第三半导体材料是Si1-xGex并且所述第二半导体材料是Si1-yGey,其中,x<1并且x<y。
在上述半导体结构中,n型finFET形成在所述第一鳍式半导体部件上,并且p型finFET形成在所述第二鳍式半导体部件上。
在上述半导体结构中,所述n型finFET的源极和漏极包括对所述第一鳍式半导体部件施加额外的拉伸应变的第四半导体材料;以及所述p型finFET的源极和漏极包括对所述第二鳍式半导体部件施加额外的压缩应变的第五半导体材料。
在上述半导体结构中,所述第四半导体材料与所述第五半导体材料彼此不同。
根据本发明的另一方面,还提供了一种形成半导体器件的方法,包括以下步骤:接收半导体衬底,所述半导体衬底包括第一半导体材料并且具有多个隔离部件,从而限定第一有源区和第二有源区;同时形成位于所述第一有源区中的包括第二半导体材料的第一鳍式部件和位于所述第二有源区中的包括所述第二半导体材料的第二鳍式部件;在所述半导体衬底的表面上形成图案化的热掩模,从而使得所述第一鳍式部件暴露;以及对所述第一鳍式部件实施退火工艺以反转所述第一鳍式部件中的应变。
在上述方法中,同时形成所述第一鳍式部件和所述第二鳍式部件的步骤还包括以下步骤:在所述隔离部件中蚀刻第一沟槽和第二沟槽;利用第三半导体材料实施第一外延生长以分别在所述第一沟槽和所述第二沟槽的底部中形成第一应变松弛缓冲件和第二应变松弛缓冲件;利用第二半导体材料实施第二外延生长以分别在所述第一沟槽和所述第二沟槽中的所述第一应变松弛缓冲件和所述第二应变松弛缓冲件的顶部上形成第一鳍式部件和第二鳍式部件;以及使围绕所述第一鳍式部件的所述隔离结构的第一区域凹进,从而暴露所述第一鳍式部件的侧壁。
在上述方法中,所述第一半导体材料、所述第二半导体材料和所述第三半导体材料均彼此不同。
在上述方法中,所述图案化的热掩模包括能够反射所述退火工艺的能量的材料。
在上述方法中,所述图案化的热掩模是接触蚀刻停止层。
在上述方法中,所述图案化的热掩模是分布式布拉格反射器。
在上述方法中,所述分布式布拉格反射器被校准为用于反射具有约532nm的波长的光,并且包括交替的10个Si3N4层和10个SiO2层,其中,每层的厚度为75nm。
在上述方法中,所述退火工艺是激光退火工艺或快速退火工艺中的一个。
在上述方法中,所述退火工艺选择性地将所述第一鳍式部件从压缩应力改变成拉伸应力,而所述第二鳍式部件具有在整个所述退火工艺中保持不变的拉伸应力。
根据本发明的又一方面,还提供了一种形成半导体器件的方法,包括:在半导体衬底上形成第一鳍式部件和第二鳍式部件,其中,所述第一鳍式部件和所述第二鳍式部件具有第一类型的应变;在所述半导体衬底上形成图案化的热掩模,从而使得所述第一鳍式部件暴露;以及使用所述图案化的热掩模实施退火工艺,从而使得所述第一鳍式部件从所述第一类型的应变被反转成与所述第一类型的应变相反的第二类型的应变,而所述第二鳍式部件在整个所述退火工艺中保持所述第一类型的应变。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上,为了清楚讨论起见,各种部件的尺寸可以被任意增大或缩小。
图1A至图1B是根据本发明的各个方面的半导体器件的截面图。
图2示出了根据本发明的各个方面的制造半导体器件的方法的流程图。
图3A至图3J是根据一些实施例的根据图2的方法形成半导体器件的截面图。
图4是根据本发明的各个方面的可以被用作热掩模的分布式布拉格反射器的截面图。
图5是根据本发明的各个方面的图4的分布式布拉格反射器的反射率的图。
具体实施方式
应当理解,以下公开内容提供了许多用于实现本发明的不同特征的许多不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在第二部件上方或者之上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和字符。这种重复是为了简化和清楚的目的,并且其本身并不表示所论述的实施例和/或结构之间的关系。
另外,为便于描述,本文中可以使用诸如“在…之下”、“在…下方”、“下”、“在…之上”、“上”等的空间相对位置术语,以描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的方位外,空间相对位置术语旨在包括器件在使用或操作中的不同方位。例如,如果翻转附图中的器件,则描述为位于其他元件“下方”或“之下”的元件可以定向为在其他元件或部件“之上”。因此,示例性术语“在…下方”可以包括“在…之上”和“在…下方”的方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且因此可以对本文中使用的空间相对位置描述符同样作相应的解释。
本发明通常涉及半导体器件,更具体地,涉及具有多栅极FET的半导体器件,诸如双栅极FET、三栅极FET和FinFET。本发明的目的在于提供用于半导体器件的方法和结构,其中,n-型和p-型器件由相同的材料构成,并且n型和p型性质来自于诱导器件的沟道区中的拉伸(对于n型)和压缩(对于P型)应力。
图1A示出了根据本发明的各个方面构建的半导体器件100的截面图。图1B示出了沿着线A-A截取的图1A的结构的截面图。如图所示,器件100示出了位于衬底的一个区中的P型FinFET和N型FinFET。提供这仅用于简化和便于理解的目的,并且不必将实施例限制于任何数量的器件、任何数量的区或任何配置的区。此外,FinFET器件100可以是在处理集成电路(IC)或其部分期间制造的中间器件,其可以包括静态随机存取存储器(SRAM)和/或其他逻辑电路、诸如电阻器、电容器和电感器的无源部件和诸如p型FET、n型FET、双栅极FET、三栅极FET、FinFET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他存储器单元和它们的组合的有源部件。
参考图1A和图1B,器件100包括衬底102和位于衬底102上方的隔离结构104。该器件100包括形成在衬底102上方的p型FinFET 108和n型FinFET 106。FinFET106和108具有类似的结构并且将在下文中共同描述。以下论述将参考FinFET106以及与其相关的参考标号。与FinFET 108相关的参考标号将出现在括号中。
FinFET 106(108)包括从衬底102穿过隔离结构104向上(沿“Z”方向)突出作为第一(第二)鳍的沟道区110b(112b)。FinFET 106(108)还包括位于隔离结构104上方并且在它的三侧(顶面和侧壁)上与沟道区110b(112b)接合的栅极结构114(116)。在一些实施例中,栅极结构114(116)可以在两侧上(例如,鳍的侧壁)与相应的鳍接合。FinFET 106(108)还包括形成在源极/漏极区126中的隔离结构104上方的源极/漏极结构118(120)和122(124),每个源极/漏极结构118(120)在它的一侧上与沟道区110b(112b)接合并且彼此间隔(displaced),从而使得栅极结构114(116)和沟道区110b(112b)本身将源极/漏极结构118(120)与源极/漏极结构122(124)分离。将在下面的部分中进一步描述器件100的各个元件。
现在参照图2,根据本发明的各个方面示出了在形成诸如图1A和图1B的半导体器件100的半导体器件中的方法200的流程图。方法200仅仅是实例,并不是旨在将本发明限制于超出权利要求中明确阐述的。可以在方法200之前、期间和之后提供额外的操作,并且对于该方法的附加实施例,可以取代、消除或重排一些操作。下文中结合图3A至图3H来描述方法200,其中,图3A至图3H示出了处于制造的各个阶段的半导体器件的截面图。
在操作202中开始该工艺并且参照图3A,接收块状鳍晶圆300,块状鳍晶圆300包括衬底102,衬底102具有通过隔离结构104分隔开的一个或多个凸起区(例如,区302和304)。
在示例性实施例中,衬底102是硅衬底。可选地,衬底102可以包括诸如锗的其他元素半导体;包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP或它们的组合的合金半导体。
在示例性实施例中,隔离结构104是由诸如氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料的介电材料形成的。在一些实施例中,隔离结构104包括浅沟槽隔离(STI)部件。在进一步的实施例中,STI部件通过诸如以下步骤的工序形成:将硬掩模层用作蚀刻掩模,在衬底区302和304之间的间隙内蚀刻衬底102。在本实施例中,蚀刻工艺蚀刻穿过衬底102。蚀刻工艺可以包括任何合适的蚀刻技术,诸如干蚀刻、湿蚀刻和/或其他蚀刻方法(例如,RIE)。在一些实施例中,蚀刻工艺包括利用不同的蚀刻化学物质的多个蚀刻步骤,每个蚀刻步骤针对特定的材料。通过蚀刻工艺在衬底102中形成隔离部件沟槽。随后在隔离部件沟槽内沉积介电材料以形成隔离部件104。合适的填充材料包括半导体氧化物、半导体氮化物、半导体氮氧化物、FSG、低k介电材料和/或它们的组合。在各个示例性实施例中,使用HDP-CVD工艺、次大气压CVD(SACVD)工艺、高纵横比工艺(HARP)和/或自旋工艺沉积介电材料。在一个这样的实施例中,CVD工艺用于沉积可流动的介电材料,可流动的介电材料包括介电材料和液体或半液体状态的溶剂。固化工艺用来除去溶剂,留下固体状态的介电材料。
参照图3B和移动至操作204,蚀刻掉衬底区302和304以形成鳍沟槽306和308。在示例性实施例中,可以通过光刻实现这种蚀刻。在这样的实施例中,可以在隔离结构104和衬底区302和304上方形成光刻胶层(或光致抗蚀剂)。示例性的光刻胶层包括光敏材料,当该光敏材料暴露于光时引起层经历性质变化。通过显影工艺,这种性质变化可以用于选择性地去除光刻胶层的曝光或未曝光部分。因此,用于形成图案化的光刻胶层的这种类型的工艺可以称为光刻图案化。
在一个实施例中,通过光刻工艺图案化光刻胶层以留下设置在隔离结构104上方的光刻胶材料的部分。在图案化光刻胶之后,实施蚀刻工艺以去除区302和区304的部分并且从而限定鳍沟槽306和308。在蚀刻鳍沟槽306和308之后,可以去除剩余的光刻胶层。示例性光刻工艺包括旋涂光刻胶层、光刻胶层的软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶层、冲洗和干燥(例如,硬烘烤)。可选地,光刻工艺可以由诸如无掩模光刻、电子束写入和离子束写入的其他方法实现、补充或代替。
现在参照图3C和移动至操作206,分别在鳍沟槽306和308的底部中外延生长应变松弛缓冲(SRB)层110a和112a。合适的生长工艺包括原子层沉积(ALD)、化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、物理汽相沉积(PVD)和/或其他合适的沉积工艺。SRB层110a和112a在组成上可以与衬底102不同以在与衬底102的界面处产生晶格应变。在示例性实施例中,SRB层110a和112a包括Si1-xGex,其中x<1。
移动到操作208,分别在鳍沟槽306和308内,在SRB层110a和112a的顶部上外延生长沟道区110b和112b。在示例性实施例中,每个沟道区110b和112b均由相同的材料组成,但是在组成上与SRB层110a和112a不同。在示例性实施例中,沟道区110b和112b的材料是Si1-yGey,其中,y>x。可选地,沟道区110b和112b可以由诸如Ge、GeSn、InGaP、InAs、InP、InGaAs、GaSa、InSb、GaSb或AlGaAs的III-V族材料形成。可以基于它们的迁移率(例如,大于Si的迁移率)、它们无缺陷地外延生长的能力和/或其他合适的因素来选择用于沟道区110b和112b的材料。随着生长,由于SRB层110a和112a与沟道区110b和112b之间的晶格尺寸的差异,沟道区110b和112b发生压缩应变。
现在参照图3D和移动至操作210,使隔离层104的区向下凹进至大约SRB 110a的水平处以暴露沟道区110b的侧部,从而暴露作为第一鳍的沟道区110b。在示例性实施例中,通过可以是光刻蚀刻的蚀刻实现这种凹进。可选地,可以使用其他合适的蚀刻技术。在蚀刻工艺期间,通过合适的掩模覆盖沟道区112b和SRB 112a以及隔离层104的围绕它们的区以便不被蚀刻。
现在参照图3E和移动至操作212,将图案化的热掩模310应用于晶圆300的表面以保护沟道区112b同时暴露沟道区110b。在示例性实施例中,图案化的热掩模310是分布式布拉格反射器(DBR)。
现在参照图4,示出了由10层Si3N4/SiO2对组成的DBR 400,其用作热掩模310。DBR 400设计为反射来自退火工艺312(使用532nm的波长)的能量,并且结果Si3N4层402和SiO2层404各自为75nm厚。DBR 400可以设计为具有不同厚度的Si3N4层和SiO2层以反射使用不同波长的退火工艺312的能量。在另一个示例性实施例中,图案化的热掩模310是金属掩模或接触蚀刻停止层(CESL)。
参照图5,示出了如图4所示的示例性DBR 400的反射率的曲线图。在这个实施例中,将DBR 400校准为用于波长532nm的源。因此,DBR 400基本上反射约532nm波段中的所有光。
再次参照图3E和移动至操作214,对晶圆300实施退火工艺312。由于图案化的热掩模310,对沟道区110b进行选择性地退火。来自退火工艺312的一些能量也到达SRB层110a。
退火工艺312用于反转沟道区(对其应用退火工艺312)上的应变。在示例性实施例中,退火工艺312将沟道区110b上的压缩应变反转为拉伸应变。在这个实施例中,随着通过退火工艺312加热沟道区110b,存在的压缩应变被松弛,导致未应变的沟道区110b。额外地,随着退火工艺312加热沟道区110b,降低了沟道区110b中的缺陷量。在这个实施例中,沟道区110b具有比SRB层110a更高的热电系数(TEC)。因此,在完成退火工艺312之后,沟道区110b和SRB层110a冷却下来,SRB层110a的收缩小于沟道区110b的收缩,从而导致沟道区110b变为拉伸应变的。
在示例性实施例中,退火工艺312是使用具有100nm和700nm之间的波长的激光的激光退火工艺。在另一示例性实施例中,退火工艺312是使用具有400nm和700nm之间的波长的闪光灯的快速退火工艺。在示例性实施例中,退火工艺312达到在从500℃到1000℃范围内的最大温度。在一些实施例中,更高的退火温度导致在沟道区110b内的更显著的应变以及伴随着缺陷的减少。可以使用包括激光退火、快速退火和/或其他适合的技术的任何合适的退火技术。
现在参照图3F和移动至操作216,从晶圆300的表面去除图案化的热掩模310。移动至操作224,蚀刻掉隔离层104的区以达到SRB 112a的水平处以暴露沟道区112b,从而暴露作为第二鳍的沟道区112b。在示例性实施例中,可以通过光刻实现这种蚀刻。可选地,可以使用其他合适的蚀刻技术。在蚀刻工艺期间,通过合适的掩模覆盖沟道区110b和SRB 110a以及隔离层104的围绕它们的区以便不被蚀刻。
移动至操作218,使隔离层104的区向下凹进至大约SRB 112a的水平处以暴露沟道区112b的侧部,从而生成第二鳍。在示例性实施例中,通过可以是光刻蚀刻的蚀刻实现这种凹进。可选地,可以使用其他合适的蚀刻技术。在蚀刻工艺期间,通过合适的掩模覆盖沟道区110b和SRB 110a以及隔离层104的围绕它们的区以便不被蚀刻。
现在参照图3G和图3H(其是沿着线A-A的图3G的截面图),在一些实施例中,在沟道区110b和112b上方形成诸如伪栅极314或316的保护结构,以为形成源极/漏极结构118、120、122和124作准备。形成伪栅极314或316可以包括沉积含有多晶硅或其他合适的材料的伪栅极层和以光刻工艺图案化该层。可以在伪栅极层上形成栅极硬掩模层。栅极硬掩模层可以包括任何适合的材料,诸如氧化硅、氮化硅、碳化硅、氮氧化硅、其他合适的材料和/或它们的组合。伪栅极314或316的形成包括沉积栅极材料层和图案化栅极材料层。在一些实施例中,图案化工艺包括形成图案化的光刻胶层;使用图案化的光刻胶层作为蚀刻掩模来蚀刻硬掩模层;以及使用图案化的硬掩模层作为蚀刻掩模来蚀刻栅极材料层。
在一些实施例中,在伪栅极314或316的侧壁上形成栅极间隔件或侧壁间隔件318。栅极间隔件318可以用于偏移随后形成的源极/漏极结构118、120、122和124,并且可以用于设计或修改源极/漏极结构(结)轮廓。栅极间隔件318可以包括任何合适的介电材料,诸如半导体氧化物、半导体氮化物、半导体碳化物、半导体氮氧化物、其他合适的材料和/或它们的组合。栅极间隔件的形成包括沉积和各向异性蚀刻,诸如干蚀刻。
在一些实施例中,在源极/漏极区126中的沟道区110b和112b上方形成硬掩模以用作导向部件以在后续操作中与外延生长的源极/漏极结构118、120、122和124对准。硬掩模形成在沟道区110b和112b的表面上,包括沟道区110b和112b的上表面和侧壁表面。硬掩模可以包括任何合适的介电材料,包括半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、它们的组合和/或其他合适的材料。示例性硬掩模包括氮化硅。在各个实施例中,使用包括热生长、ALD、CVD、HDP-CVD、PVD和/或其他合适的沉积工艺的一个或多个合适的工艺形成硬掩模层。
在随后的操作中,进一步为源极/漏极结构118、120、122和124的外延生长作准备,蚀刻源极/漏极区126内的硬掩模。该蚀刻基本上去除源极/漏极区126内的沟道区110b和112b中的所有的半导体材料。该技术可以留下延伸在半导体层120的顶面之上的硬掩模的一部分以控制和对准源极/漏极结构118、120、122和124的外延生长。可以使用各种蚀刻剂和技术将该蚀刻实施为单蚀刻工艺或多蚀刻工艺。在示例性实施例中,使用诸如各向异性干蚀刻技术的各向异性(定向)蚀刻技术蚀刻硬掩模的水平表面。在另一个示例性实施例中,蚀刻包括多个蚀刻步骤,多个蚀刻步骤进一步包括各向异性蚀刻步骤以去除位于沟道区110b和112b上方的硬掩模的顶部,和选择性蚀刻步骤(诸如湿蚀刻)以选择性地去除沟道区110b和112b的半导体材料。
移动至操作220和参照图3G和图3H,在源极/漏极区126上形成源极/漏极结构118、120、122和124。在一些实施例中,伪栅极314或316和/或栅极间隔件318将源极/漏极结构118、120、122和124限制于源极/漏极区126,并且硬掩模将源极/漏极结构水平地限制在源极/漏极区126内。在许多实施例中,由一个或多个外延或外延(epi)的工艺形成源极/漏极结构118、120、122和124,由此,在沟道区110b和112b上以晶体状态生长Si部件、SiGe部件、SiC部件和/或其他合适的部件。合适的外延工艺包括CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延和/或其他合适的工艺。外延工艺可使用气体和/或液体前体,其与沟道区110b和112b的组分相互作用。
通过引入掺杂物质可以在外延工艺期间原位掺杂源极/漏极结构118、120、122和124,掺杂物质包括:p型掺杂剂,诸如硼或BF2;n型掺杂剂,诸如磷或砷;和/或包括它们的组合的其他合适的掺杂剂。如果源极/漏极结构118、120、122和124没有被原位掺杂,则实施注入工艺(即,结注入工艺)以掺杂源极/漏极结构118、120、122和124。在示例性实施例中,NMOS中的源极/漏极结构118、120、122和124包括SiCP或SiP,而那些位于PMOS中的源极/漏极结构118、120、122和124包括GeSnB(锡可以用于调整晶格常数)和/或SiGeSnB。可以实施一个或多个退火工艺以活化源极/漏极结构118、120、122和124。合适的退火工艺包括快速热退火(RTA)和/或激光退火工艺。在另一实施例中,源极/漏极结构118、120、122和124对它们的邻接的沟道区110b和112b施加额外的应变。具体地,源极/漏极结构118和122对沟道区110b施加额外的拉伸应变并且源极/漏极结构120和124对沟道区112b施加额外的压缩应变。
移动至操作222并且参照图3I和图3J(图3J是沿着线A-A的图3I的截面),栅极结构114和116分别形成在沟道区110b和112b的顶部上。在一些实施例中,在源极/漏极区126中的源极/漏极结构118、120、122和124上形成层间电介质(ILD)。ILD可以围绕伪栅极314或316和/或栅极间隔件318,从而允许去除这些部件并且在产生的腔体中形成替代栅极114和116。因此,在这样的实施例中,在沉积ILD之后,去除伪栅极314或316。ILD也可以是电互连与半导体器件100位于相同衬底上的其他器件的电互连结构的部分。在这样的实施例中,ILD用作支撑和隔离导电迹线的绝缘体。ILD可包括任何合适的介电材料,诸如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物、其他合适的材料和/或它们的组合。在一些实施例中,ILD的形成包括沉积和CMP。
去除伪栅极314或316,从而生成栅极沟槽。在一些实施例中,通过诸如湿蚀刻的工艺以选择性地蚀刻伪栅极314或316来去除伪栅极314或316。蚀刻可以包括针对相应的伪栅极层的多个蚀刻步骤。栅极结构114和116形成为包裹围绕沟道区110b和112b。通过工序(诸如包括沉积和CMP的工序)在栅极沟槽中形成栅极结构114和116。但是应当理解,栅极结构114和116可以是任何合适的栅极结构,在一些实施例中,栅极结构114和116是包括栅极介电层和栅电极层的高-k金属栅极,栅极介电层和栅电极层各自可以包括多个子层。
在一个这样的实施例中,栅极介电层包括通过诸如ALD、CVD、臭氧氧化等合适的方法沉积的界面层。界面层可以包括氧化硅、HfSiO、氮化硅、氮氧化硅、和/或其他合适的材料。在一些实施例中,栅极介电层包括通过合适的技术沉积在界面层上的高k介电层,合适的技术诸如ALD、CVD、金属有机CVD(MOCVD)、PVD、热氧化、其组合和/或其他适合的技术。高k介电层可以包括LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba、Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其他合适的材料。
然后,可以通过ALD、PVD、CVD或其他合适的工艺形成栅电极层,栅电极层可以包括单层或多层,诸如金属层、衬垫层、润湿层、和/或粘附层。栅电极层可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W或任何适合的材料。在一些实施例中,对于nMOS和pMOS器件使用不同的金属栅极材料。可以实施CMP工艺以产生栅极结构114和116的基本上平坦的顶面。在形成栅极结构114和116之后,可以将半导体器件100提供为用于进一步的制造,诸如接触件形成和进一步制造互连结构。
由方法200产生的结构分别是成对的n型和p型FinFET 106和108。沟道区112b由于被压缩应变是p型沟道,而沟道区110b由于被拉伸应变是n型沟道。因此,方法200使用用于n型和p型FinFET的仅一轮外延生长或沉积同时产生n型和p型FinFET,并且由退火工艺312实现沟道区110b中的n型性质。退火工艺312相比于外延生长或沉积非常快,因此,相比于需要n型和p型材料的分别地外延生长或沉积的方法,方法200更节约时间。
虽然不旨在限制,本发明的一个或多个实施例对半导体器件及其形成提供了许多益处。例如,本发明的实施例提供了用于块状FinFET的结构和方法,块状FinFET具有由相同的材料堆叠件组成的n型和p型沟道鳍。由于仅需要使用一次外延生长工艺阶段来获得n型和p型finFET,这允许在更短的时间段内制造器件。可以以低复杂度和低制造成本实现本发明的各个实施例。
在一个示例性方面中,本发明涉及一种形成半导体器件的方法。该方法包括接收衬底,衬底具有穿过隔离结构在衬底上方突出的第一鳍和第二鳍。该方法还包括蚀刻第一和第二鳍的部分,从而生成第一和第二沟槽;以及在第一沟槽和第二沟槽中同时生长第一和第二外延层。该方法还包括使隔离结构凹进,从而生成在隔离结构上方突出的第一鳍的第一外延层的第一部分和由隔离结构围绕的第一鳍的第一外延层的第二部分。该方法还包括应用图案化的热掩模,图案化的热掩模使得第一鳍的第一外延层暴露。该方法还包括实施退火工艺,从而使第一鳍的第一外延层上的应变反转。
在另一个示例性方面中,本发明涉及一种半导体器件。该半导体器件包括衬底;位于衬底上方的隔离结构;以及从衬底突出在隔离部件之上的第一和第二鳍结构。第一和第二鳍结构由位于衬底上方的两个外延层组成,其中,第一外延层的第一部分在隔离结构之上突出,第一外延层的第二部分由隔离结构围绕,并且第二外延层由隔离结构围绕。第一外延层的在隔离结构之上突出的部分在第一鳍结构中具有拉伸应力并且在第二鳍结构中具有压缩应力。该半导体器件还包括位于隔离结构上方并且与在隔离结构之上突出的每个鳍的第一外延层的部分在顶面和两个侧部上接合的栅极结构。该半导体器件还包括位于隔离结构上方并且与在隔离结构之上突出的每个鳍的第一外延层的部分在侧部(没有与栅极结构接合)上接合的源极/漏极结构。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体结构,包括:
衬底,包括第一半导体材料并且具有第一有源区和第二有源区;
第一鳍式半导体部件,包括第二半导体材料并且形成在所述第一有源区中;以及
第二鳍式半导体部件,包括所述第二半导体材料并且形成在所述第二有源区中,
其中,所述第一鳍式半导体部件是拉伸应变的并且所述第二鳍式半导体部件是压缩应变的。
2.根据权利要求1所述的半导体结构,其中,所述第一半导体材料与所述第二半导体材料不同。
3.根据权利要求2所述的半导体结构,其中,所述第二半导体材料是具有比Si更高的迁移率的任何半导体材料。
4.根据权利要求2所述的半导体结构,其中,所述第二半导体材料选自由SiGe、Ge、GeSn、InGaP、InAs、InP、InGaAs、GaAs、InSb、GaSb、和AlGaAs组成的组。
5.根据权利要求1所述的半导体结构,还包括:
第一应变松弛缓冲部件和第二应变松弛缓冲部件,所述第一应变松弛缓冲部件和所述第二应变松弛缓冲部件分别形成在所述第一有源区和所述第二有源区内,从而使得所述第一应变松弛缓冲部件位于所述第一鳍式半导体部件和所述衬底之间,并且所述第二应变松弛缓冲部件位于所述第二鳍式半导体部件和所述衬底之间,其中,所述第一应变松弛缓冲部件和所述第二应变松弛缓冲部件均包括第三半导体材料。
6.根据权利要求5所述的半导体结构,其中,所述第一半导体材料、所述第二半导体材料和所述第三半导体材料均彼此不同。
7.根据权利要求5所述的半导体结构,其中,所述第三半导体材料是Si1-xGex并且所述第二半导体材料是Si1-yGey,其中,x<1并且x<y。
8.根据权利要求1所述的半导体结构,其中,n型finFET形成在所述第一鳍式半导体部件上,并且p型finFET形成在所述第二鳍式半导体部件上。
9.一种形成半导体器件的方法,包括以下步骤:
接收半导体衬底,所述半导体衬底包括第一半导体材料并且具有多个隔离部件,从而限定第一有源区和第二有源区;
同时形成位于所述第一有源区中的包括第二半导体材料的第一鳍式部件和位于所述第二有源区中的包括所述第二半导体材料的第二鳍式部件;
在所述半导体衬底的表面上形成图案化的热掩模,从而使得所述第一鳍式部件暴露;以及
对所述第一鳍式部件实施退火工艺以反转所述第一鳍式部件中的应变。
10.一种形成半导体器件的方法,包括:
在半导体衬底上形成第一鳍式部件和第二鳍式部件,其中,所述第一鳍式部件和所述第二鳍式部件具有第一类型的应变;
在所述半导体衬底上形成图案化的热掩模,从而使得所述第一鳍式部件暴露;以及
使用所述图案化的热掩模实施退火工艺,从而使得所述第一鳍式部件从所述第一类型的应变被反转成与所述第一类型的应变相反的第二类型的应变,而所述第二鳍式部件在整个所述退火工艺中保持所述第一类型的应变。
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