JP5271372B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5271372B2 JP5271372B2 JP2011060630A JP2011060630A JP5271372B2 JP 5271372 B2 JP5271372 B2 JP 5271372B2 JP 2011060630 A JP2011060630 A JP 2011060630A JP 2011060630 A JP2011060630 A JP 2011060630A JP 5271372 B2 JP5271372 B2 JP 5271372B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor layer
- regions
- mask
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 238000004519 manufacturing process Methods 0.000 title claims description 53
- 239000013078 crystal Substances 0.000 claims description 44
- 238000005468 ion implantation Methods 0.000 claims description 39
- 150000002500 ions Chemical class 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 29
- 238000010438 heat treatment Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 10
- 238000002425 crystallisation Methods 0.000 claims description 8
- 230000008025 crystallization Effects 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 abstract description 41
- 239000011810 insulating material Substances 0.000 abstract 1
- 239000002070 nanowire Substances 0.000 description 187
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 57
- 229910021417 amorphous silicon Inorganic materials 0.000 description 41
- 229910052710 silicon Inorganic materials 0.000 description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 32
- 239000010703 silicon Substances 0.000 description 32
- 238000005280 amorphization Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000003949 trap density measurement Methods 0.000 description 3
- 238000010306 acid treatment Methods 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Description
第1実施形態による半導体装置について図1乃至図3を参照して説明する。この実施形態の半導体装置は、多結晶シリコンのナノワイヤトランジスタ(以下、ナノワイヤトランジスタともいう)を備えている。このナノワイヤトランジスタの平面図を図1に示し、図1に示す切断面A−Aで切断した場合の断面図を図2に示し、図1に示す切断面B−Bで切断した場合の断面図を図3に示す。なお、断面A−Aはゲート長方向の断面を示し、断面B−Bはゲート幅方向の断面を示す。
第2実施形態による半導体装置を図12乃至図15に示す。この第2実施形態の半導体装置は、多結晶シリコンのナノワイヤトランジスタを備えている。このナノワイヤトランジスタの平面図を図12に示し、図12に示す切断面A−Aで切断した場合の断面図を図13に示し、図12に示す切断面B−Bで切断した場合の断面図を図14に示し、図12に示す切断面C−Cで切断した場合の断面図を図15に示す。なお、断面A−Aはゲート長方向の断面を示し、断面B−Bはゲート幅方向の断面を示す。
第3実施形態の半導体装置について、図20乃至図23および図1を参照して説明する。
2 酸化膜
3 ナノワイヤ領域
3a ナノワイヤ領域
3b ナノワイヤ領域
4 多結晶シリコン層
4a 多結晶シリコン層
4b 多結晶シリコン層
5 ゲート絶縁膜
6 ゲート電極
7 ゲート側壁
8 ソース領域
8a ソース領域
8b ソース領域
9 ドレイン領域
9a ドレイン領域
9b ドレイン領域
12 非晶質シリコン層
12a 非晶質シリコン層
13 ハードマスク層
13a ハードマスク
16 酸化膜
18 エピタキシャル成長で形成されたシリコン層
19 非晶質シリコン層
19a 非晶質シリコン層
Claims (15)
- 半導体基板上に第1絶縁膜を形成する工程と、
前記第1絶縁膜上に設けられ、第1領域と前記第1領域よりも幅の広い第2および第3領域とを有しこれらの第2および第3領域の少なくとも一方が前記第1領域に接続するように構成された第1半導体層と、前記第1乃至第3領域の上面に設けられるマスクと、を形成する工程と、
前記マスクを用いて、前記第1領域を非晶質化するために前記第1半導体層の前記第1領域の側面にイオン注入を行う第1イオン注入を行う工程と、
前記第1イオン注入を行った後に第1熱処理を行い、前記第1領域に接続する前記第2および第3領域の少なくとも一方の結晶を種として前記第1半導体層の前記第1領域を結晶化する工程と、
前記マスクを除去した後、前記第1半導体層の前記第1領域の少なくとも側面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極の、前記第2および第3領域側の側面に絶縁体のゲート側壁を形成する工程と、
少なくとも前記第1半導体層の前記第2および第3領域に第2イオン注入を行う工程と、
を備えていることを特徴とする半導体装置の製造方法。 - 前記第1イオン注入を行う前の前記第1半導体層は多結晶半導体である請求項1記載の半導体装置の製造方法。
- 前記第1イオン注入を行う工程は、前記第2領域から前記第3領域に向かう方向に対して傾くとともに前記第1領域の上面の法線に対して0度より大きく90度未満の角度でイオン注入を行うことを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記マスクを形成する前の前記第1半導体層は非晶質半導体であり、
前記マスクを形成した後でかつ前記第1イオン注入を行う前に、第2熱処理を行って前記第1半導体層を多結晶化する工程を更に備えていることを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。 - 前記マスクを形成する前の前記第1半導体層は非晶質半導体であり、
前記第1半導体層と前記第1半導体層の上面に設けられるマスクとを形成する工程は、
前記第1絶縁膜上に非晶質半導体層を形成する工程と、
前記非晶質半導体層上にマスク層を形成する工程と、
前記マスク層をパターニングしてマスクを形成する工程と、
前記マスクを用いて前記第1半導体層をパターニングする工程と、
を備え、
前記マスクを形成した後でかつ前記第1イオン注入を行う前に、第2熱処理を行って前記第1半導体層を多結晶化する工程を更に備えていることを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。 - 前記第1半導体層の第1領域は、前記第2および第3領域に接続していることを特徴とする請求項1乃至5のいずれかに記載の半導体装置の製造方法。
- 前記第1半導体層の第1領域は、前記第2および第3領域の一方に接続するが他方には接続せず、
前記第1領域と、前記第2および第3領域の他方とを電気的に接続する工程を更に備えていることを特徴とする請求項1乃至5のいずれかに記載の半導体装置の製造方法。 - 半導体基板上に第1絶縁膜を形成する工程と、
前記第1絶縁膜上に設けられ、第1領域と前記第1領域よりも幅の広い第2および第3領域とを有しこれらの第2および第3領域の少なくとも一方が前記第1領域に接続するように構成された第1半導体層と、前記第1半導体層の上面に設けられる第2絶縁膜と、前記第2絶縁膜上に設けられ、第4領域と前記第4領域よりも幅の広い第5および第6領域とを有しこれらの第5および第6領域の少なくとも一方が前記第4領域に接続するように構成された第2半導体層と、前記第4乃至第6領域の上面に設けられるマスクとを形成する工程と、
前記マスクを用いて、前記第1および第4領域を非晶質化するために前記第1半導体層の前記第1領域の側面および第2半導体層の前記第4領域の側面にイオン注入を行う第1イオン注入を行う工程と、
前記第1イオン注入を行った後に第1熱処理を行い、前記第1領域に接続する前記第2および第3領域の少なくとも一方の結晶を種として前記第1半導体層の前記第1領域を結晶化するとともに前記第4領域に接続する前記第5および第6領域の少なくとも一方の結晶を種として前記第2半導体層の前記第4領域を結晶化する工程と、
前記マスクを除去した後、前記第1半導体層の前記第1領域の少なくとも側面および第2半導体層の前記第4領域の少なくとも側面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極の、前記第2および第3領域側の側面に絶縁体のゲート側壁を形成する工程と、
少なくとも前記第1半導体層の前記第2および第3領域と前記第2半導体層の前記第5および第6領域に第2イオン注入を行う工程と、
を備えていることを特徴とする半導体装置の製造方法。 - 前記第1イオン注入を行う前の前記第1および第2半導体層は多結晶半導体である請求項8記載の半導体装置の製造方法。
- 前記第1イオン注入を行う工程は、前記第5領域から前記第6領域に向かう方向に対して傾くとともに前記第4領域の上面の法線に対して0度より大きく90度未満の角度でイオン注入を行うことを特徴とする請求項8または9記載の半導体装置の製造方法。
- 前記マスクを形成する前の前記第1および第2半導体層は非晶質半導体であり、
前記マスクを形成した後でかつ前記第1イオン注入を行う前に、第2熱処理を行って前記第1および第2半導体層を多結晶化する工程を更に備えていることを特徴とする請求項8乃至10のいずれかに記載の半導体装置の製造方法。 - 前記マスクを形成する前の前記第1および第2半導体層は非晶質半導体であり、
前記第1半導体層と、第2絶縁膜と、前記第2半導体層と、前記マスクとを形成する工程は、
前記第1絶縁膜上に第1非晶質半導体層を形成する工程と、
前記第1非晶質半導体層上に前記第2絶縁膜を形成する工程と、
前記第2絶縁膜上に第2非晶質半導体層を形成する工程と、
前記第2非晶質半導体層上にマスク層を形成する工程と、
前記マスク層をパターニングしてマスクを形成する工程と、
前記マスクを用いて前記第2非晶質半導体層、前記第2絶縁膜、および前記第1非晶質半導体層をパターニングする工程と、
を備え、
前記マスクを形成した後でかつ前記第1イオン注入を行う前に、第2熱処理を行って前記第1および第2非晶質半導体層を多結晶化する工程を更に備えていることを特徴とする請求項8乃至10のいずれかに記載の半導体装置の製造方法。 - 前記第1半導体層の第1領域は、前記第2および第3領域に接続し、
前記第2半導体層の第4領域は、前記第5および第6領域に接続していることを特徴とする請求項8乃至12のいずれかに記載の半導体装置の製造方法。 - 前記第1半導体層の第1領域は、前記第2および第3領域の一方に接続するが他方には接続せず、
前記第2半導体層の第4領域は、前記第5および第6領域の一方に接続するが他方には接続せず、
前記第1領域と、前記第2および第3領域の他方とを電気的に接続する工程と、前記第4領域と、前記第5および第6領域の他方とを電気的に接続する工程を更に備えていることを特徴とする請求項8乃至12のいずれかに記載の半導体装置の製造方法。 - 前記第1イオン注入を行う工程のイオン種として、Ge、F、N、C、B、P、As、Ar、Siのいずれかを用いることを特徴とする請求項1乃至14のいずれかに記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011060630A JP5271372B2 (ja) | 2011-03-18 | 2011-03-18 | 半導体装置の製造方法 |
US13/236,199 US8999801B2 (en) | 2011-03-18 | 2011-09-19 | Nanowire channel field effect device and method for manufacturing the same |
TW100133819A TWI520214B (zh) | 2011-03-18 | 2011-09-20 | 半導體裝置及其製造方法 |
TW103135301A TWI520184B (zh) | 2011-03-18 | 2011-09-20 | 半導體裝置及其製造方法 |
KR1020110120940A KR101324439B1 (ko) | 2011-03-18 | 2011-11-18 | 반도체 장치 및 그 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011060630A JP5271372B2 (ja) | 2011-03-18 | 2011-03-18 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012199274A JP2012199274A (ja) | 2012-10-18 |
JP5271372B2 true JP5271372B2 (ja) | 2013-08-21 |
Family
ID=46827769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011060630A Active JP5271372B2 (ja) | 2011-03-18 | 2011-03-18 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8999801B2 (ja) |
JP (1) | JP5271372B2 (ja) |
KR (1) | KR101324439B1 (ja) |
TW (2) | TWI520184B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5456090B2 (ja) | 2012-03-13 | 2014-03-26 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN103236400B (zh) * | 2013-03-29 | 2015-07-08 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜制作方法、薄膜晶体管制作方法 |
US9871104B2 (en) * | 2015-06-30 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nanowire semiconductor device structure and method of manufacturing |
CN108352400B (zh) * | 2015-10-30 | 2021-09-10 | 佛罗里达大学研究基金会有限公司 | 包封的纳米结构及其制造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0691109B2 (ja) * | 1985-09-30 | 1994-11-14 | ソニー株式会社 | 電界効果型トランジスタの製造方法 |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
KR100528486B1 (ko) * | 2004-04-12 | 2005-11-15 | 삼성전자주식회사 | 불휘발성 메모리 소자 및 그 형성 방법 |
TWI283066B (en) * | 2004-09-07 | 2007-06-21 | Samsung Electronics Co Ltd | Field effect transistor (FET) having wire channels and method of fabricating the same |
KR100593369B1 (ko) | 2004-09-23 | 2006-06-28 | 한국과학기술원 | 둥근 실리콘 나노와이어를 이용한 다중 게이트 전계효과트랜지스터 제조 방법 및 그 구조 |
KR100594327B1 (ko) | 2005-03-24 | 2006-06-30 | 삼성전자주식회사 | 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법 |
KR101127132B1 (ko) * | 2005-05-13 | 2012-03-21 | 삼성전자주식회사 | 실리콘 나노와이어 기판 및 그 제조방법, 그리고 이를이용한 박막 트랜지스터의 제조방법 |
KR101155176B1 (ko) * | 2005-07-12 | 2012-06-11 | 삼성전자주식회사 | 방향성이 조절된 단결정 와이어 및 이를 적용한트랜지스터의 제조방법 |
US7341902B2 (en) * | 2006-04-21 | 2008-03-11 | International Business Machines Corporation | Finfet/trigate stress-memorization method |
US20080111185A1 (en) * | 2006-11-13 | 2008-05-15 | International Business Machines Corporation | Asymmetric multi-gated transistor and method for forming |
JP2009054705A (ja) * | 2007-08-24 | 2009-03-12 | Toshiba Corp | 半導体基板、半導体装置およびその製造方法 |
JP2008085357A (ja) * | 2007-11-06 | 2008-04-10 | Nec Corp | 電界効果型トランジスタの製造方法 |
US7829401B2 (en) * | 2008-05-15 | 2010-11-09 | Advanced Micro Devices, Inc. | MOSFET with asymmetrical extension implant |
US8722492B2 (en) * | 2010-01-08 | 2014-05-13 | International Business Machines Corporation | Nanowire pin tunnel field effect devices |
US8283217B2 (en) * | 2010-03-04 | 2012-10-09 | International Business Machines Corporation | Prevention of oxygen absorption into high-K gate dielectric of silicon-on-insulator based finFET devices |
US8395942B2 (en) * | 2010-05-17 | 2013-03-12 | Sandisk Technologies Inc. | Junctionless TFT NAND flash memory |
US8263446B2 (en) * | 2010-09-13 | 2012-09-11 | International Business Machines Corporation | Asymmetric FinFET devices |
-
2011
- 2011-03-18 JP JP2011060630A patent/JP5271372B2/ja active Active
- 2011-09-19 US US13/236,199 patent/US8999801B2/en active Active
- 2011-09-20 TW TW103135301A patent/TWI520184B/zh not_active IP Right Cessation
- 2011-09-20 TW TW100133819A patent/TWI520214B/zh not_active IP Right Cessation
- 2011-11-18 KR KR1020110120940A patent/KR101324439B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI520184B (zh) | 2016-02-01 |
US20120235152A1 (en) | 2012-09-20 |
KR101324439B1 (ko) | 2013-10-31 |
US8999801B2 (en) | 2015-04-07 |
TWI520214B (zh) | 2016-02-01 |
KR20120106538A (ko) | 2012-09-26 |
TW201507001A (zh) | 2015-02-16 |
TW201239985A (en) | 2012-10-01 |
JP2012199274A (ja) | 2012-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5073014B2 (ja) | 半導体装置およびその製造方法 | |
US9576960B2 (en) | Structure for finFET CMOS | |
JP5279807B2 (ja) | 半導体装置およびその製造方法 | |
US10037924B2 (en) | Fin-FET device and fabrication method thereof | |
US8796093B1 (en) | Doping of FinFET structures | |
CN106030818B (zh) | 用于基于鳍状物的nmos晶体管的高移动性应变沟道 | |
JP5404812B2 (ja) | 半導体装置の製造方法 | |
US10192888B2 (en) | Metallized junction FinFET structures | |
JP5454984B2 (ja) | 半導体装置の製造方法 | |
US20110291188A1 (en) | Strained finfet | |
JP5184831B2 (ja) | フィン型トランジスタの形成方法 | |
JP5271372B2 (ja) | 半導体装置の製造方法 | |
US9570588B2 (en) | Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material | |
US9660086B2 (en) | Fin-shaped field effect transistor | |
US9831254B1 (en) | Multiple breakdown point low resistance anti-fuse structure | |
TWI790476B (zh) | 積體電路晶粒及其製造方法 | |
US9159632B2 (en) | Fabrication method of semiconductor apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130312 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130314 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130402 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130419 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130510 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5271372 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |