JP5073014B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5073014B2 JP5073014B2 JP2010134460A JP2010134460A JP5073014B2 JP 5073014 B2 JP5073014 B2 JP 5073014B2 JP 2010134460 A JP2010134460 A JP 2010134460A JP 2010134460 A JP2010134460 A JP 2010134460A JP 5073014 B2 JP5073014 B2 JP 5073014B2
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Description
本実施形態の半導体装置の製造方法は、半導体基板上に絶縁体層を形成する工程と、絶縁体層上に狭窄部を有する非晶質または多結晶質の半導体層を形成する工程と、半導体層上に半導体層よりも熱膨張係数の大きい絶縁体層を形成する工程と、熱処理を行う工程と、絶縁体層を除去する工程と、狭窄部の側面にゲート絶縁膜を形成する工程と、ゲート絶縁膜上にゲート電極を形成する工程と、半導体層中にソース・ドレイン領域を形成する工程と、を備えている。
本実施形態の半導体装置の製造方法は、第1の実施形態の製造方法において、n型トランジスタ作製領域にのみ非晶質シリコンナノワイヤを取り囲むシリコン窒化膜の歪み誘起用絶縁膜を形成し、p型トランジスタ作製領域では非晶質シリコンナノワイヤを取り囲む歪み誘起用絶縁膜を除去した状態で、非晶質シリコン層の結晶化用熱処理を行うものである。第1の実施形態と重複する内容については記載を省略する。
本実施形態の半導体装置の製造方法は、多結晶シリコンナノワイヤトランジスタの下層に、プレーナ型の電界効果トランジスタが形成されること以外は、第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については記載を省略する。
本実施形態の半導体装置の製造方法は、半導体基板上に第1の絶縁体層を形成する工程と、第1の絶縁体層上に非晶質または多結晶質の第1の半導体層を形成する工程と、第1の半導体層上に第2の絶縁体層を形成する工程と、第2の絶縁体層上に非晶質または多結晶質の第2の半導体層を形成する工程と、第2の半導体層、第2の絶縁体層および第1の半導体層をパターニングし、第1および第2の半導体層に狭窄部を形成する工程と、第1および第2の半導体層上に第1および第2の半導体層よりも第3の絶縁体層を形成する工程と、熱処理を行う工程と、第3の絶縁体層を除去する工程と、狭窄部の側面にゲート絶縁膜を形成する工程と、ゲート絶縁膜上にゲート電極を形成する工程と、第1および第2の半導体層中にソース・ドレイン領域を形成する工程と、を有する。
本実施形態の半導体装置の製造方法は、第4の実施形態の製造方法において、ゲート絶縁膜を形成する工程と、ゲート電極を形成する工程との間に、ゲート絶縁膜上に電荷を蓄積する電荷蓄積絶縁膜を形成する工程と、電荷蓄積絶縁膜上に、電荷をブロックするブロック絶縁膜を形成する工程とを、さらに有する。
本実施形態の半導体装置の製造方法は、半導体基板の上に第1の絶縁体層を形成する工程と、第1の絶縁体層上にゲート電極層を形成する工程と、ゲート電極層上に第2の絶縁体層を形成する工程と、第2の絶縁体層、ゲート電極層および第1の絶縁体層を貫通する溝を形成する工程と、溝の内側面にゲート絶縁膜を形成する工程と、ゲート絶縁膜の内側面に非晶質または多結晶質の半導体層を形成する工程と、半導体層の内側面に半導体層よりも熱膨張係数の大きい第3の絶縁体層を形成する工程と、半導体層に熱処理を行う工程と、第3の絶縁体層を除去する工程と、を有する。
本実施形態の半導体装置の製造方法は、第6の実施形態の製造方法において、溝を形成する工程と、ゲート絶縁膜を形成する工程との間に、溝の内側面にブロック絶縁膜を形成する工程と、ブロック絶縁膜の内側面に電荷を蓄積する電荷蓄積絶縁膜を形成する工程とを、さらに有する
12 酸化膜
14 狭窄部(シリコンナノワイヤ)
16 幅広部
18 多結晶シリコン層
20 ゲート絶縁膜(トンネル絶縁膜)
22 ゲート電極、ゲート電極層
24 ゲート側壁
26 チャネル領域
28 ソース領域
28a 不純物拡散層
28b 金属シリサイド膜
30 ドレイン領域
30a 不純物拡散層
30b 金属シリサイド膜
32 非晶質シリコン層
36 保護絶縁膜
38 歪み誘起用絶縁膜
74 電荷蓄積絶縁膜
76 ブロック絶縁膜
Claims (9)
- 半導体基板上に第1の絶縁体層を形成する工程と、
前記第1の絶縁体層上に非晶質または多結晶質の第1の半導体層を形成する工程と、
前記第1の半導体層上に第2の絶縁体層を形成する工程と、
前記第2の絶縁体層上に非晶質または多結晶質の第2の半導体層を形成する工程と、
前記第2の半導体層、前記第2の絶縁体層および前記第1の半導体層をパターニングし、前記第1および第2の半導体層に狭窄部を形成する工程と、
前記第1および第2の半導体層上に前記第1および第2の半導体層よりも熱膨張係数の大きい第3の絶縁体層を形成する工程と、
熱処理を行う工程と、
前記第3の絶縁体層を除去する工程と、
前記狭窄部の側面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記第1および第2の半導体層中にソース・ドレイン領域を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第1および第2の半導体層中に形成される複数のソース領域のうちの少なくともいずれか2つ、または、複数のドレイン領域のうちの少なくともいずれか2つが、電気的に独立していることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第1および第2の半導体層中に形成される複数のソース領域のすべて、および、複数のドレイン領域のすべてが、電気的に共通化されていることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記ゲート絶縁膜を形成する工程と、前記ゲート電極を形成する工程との間に、
前記ゲート絶縁膜上に、電荷蓄積絶縁膜を形成する工程と、前記電荷蓄積絶縁膜上に、ブロック絶縁膜を形成する工程とを、さらに有することを特徴とする請求項1記載の半導体装置の製造方法。 - 半導体基板上に第1の絶縁体層を形成する工程と、
前記第1の絶縁体層上にゲート電極層を形成する工程と、
前記ゲート電極層上に第2の絶縁体層を形成する工程と、
前記第2の絶縁体層、前記ゲート電極層および前記第1の絶縁体層を貫通する溝を形成する工程と、
前記溝の内側面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の内側面に非晶質または多結晶質の半導体層を形成する工程と、
前記半導体層の内側面に前記半導体層よりも熱膨張係数の大きい第3の絶縁体層を形成する工程と、
熱処理を行う工程と、
前記第3の絶縁体層を除去する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記溝を形成する工程と、前記ゲート絶縁膜を形成する工程との間に、
前記溝の内側面にブロック絶縁膜を形成する工程と、前記ブロック絶縁膜の内側面に電荷蓄積絶縁膜を形成する工程とを、さらに有することを特徴とする請求項5記載の半導体装置の製造方法。 - 前記第1および第2の半導体層がシリコンであることを特徴とする請求項1ないし請求項4いずれか一項記載の半導体装置の製造方法。
- 前記半導体層がシリコンであることを特徴とする請求項5または請求項6記載の半導体装置の製造方法。
- 前記第3の絶縁体層がシリコン窒化膜であることを特徴とする請求項1ないし請求項8いずれか一項記載の半導体装置の製造方法。
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