CN103199016A - Process method for preventing occurrence of defects of photoresist in wet etching - Google Patents
Process method for preventing occurrence of defects of photoresist in wet etching Download PDFInfo
- Publication number
- CN103199016A CN103199016A CN2013100851979A CN201310085197A CN103199016A CN 103199016 A CN103199016 A CN 103199016A CN 2013100851979 A CN2013100851979 A CN 2013100851979A CN 201310085197 A CN201310085197 A CN 201310085197A CN 103199016 A CN103199016 A CN 103199016A
- Authority
- CN
- China
- Prior art keywords
- photoresist
- silicon oxide
- wet etching
- film
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention provides a process method for preventing occurrence of defects of photoresist in wet etching. The method comprises the steps: coating the photoresist on a silicon wafer, wherein a shallow insulation groove is formed in the silicon wafer, and a silicon oxide thin film is deposited on the silicon wafer; finishing exposure and development on the photoresist to expose a first silicon oxide area to be wet etched of the silicon oxide thin film and a second silicon oxide area protected by the photoresist; after the exposure and the development, coating a miniature aid film on a photoresist graph in the same developer carrying out the development, heating the miniature aid film and enabling the miniature aid film to react with the surface of the photoresist to form a high molecular and cross-linked protection film, thereby solidifying the photoresist graph, and then removing redundant miniature aid films; carrying out the wet etching to partially remove the silicon oxide thin film on the first silicon oxide area; and after removing redundant photoresist, depositing the silicon oxide thin film again, and thereby forming silicon oxide thin film dual gate oxide with different thickness on the first silicon oxide area and the second silicon oxide area.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of photoresist that prevents and in wet etching, produce the process of defective.
Background technology
Advanced integrated circuit (IC) chip usually can integrated multiple function element.Multiple function element generally needs corresponding different field-effect transistors (FETs).Multiple-grid oxygen (multiple gate oxide) technology is the common method of making different field-effect transistors in same chip.There is several different methods can realize multiple-grid oxygen.
For example, Fig. 1-Fig. 5 has showed the manufacture craft flow process of Dual Gate Oxide (dual gate oxide).Form shallow isolated raceway groove 2 and depositing the silicon chip 1 coating photoresist 4 (Fig. 1) of silicon oxide film 3.Exposure and develop after expose zone 5 that will wet etching and be subjected to the zone 6 (Fig. 2) of photoresist 4 protections.The silicon oxide film 3 of wet etching attenuate or removal regional 5 fully (Fig. 3-Fig. 4).Remove behind the residue photoresist 4 cvd silicon oxide film 3 again, form the silicon oxide film 3 of different-thickness-be so-called Dual Gate Oxide (Fig. 5) in zone 5 and zone 6.On regional 5 and regional 6, can produce different field-effect transistors.
Wet etching silicon oxide film 3 is that the silicon chip 1 that will deposit silicon oxide film 3 places acid solution.Acid solution commonly used is such as hydrofluoric acid (HF).Acid solution also can form defective to photoresist 4 generation effects when etching oxidation silicon thin film 3.Main defective comprises residual and carborundum (SiC) deposition of photoresist.The mechanism that forms the photoresist residual defects is acid solution etch photoresist film, and the part macromolecular compound in the photoresist film is peeled off out from photoresist film, forms defective at silicon chip surface.The formation mechanism of carborundum deposition defective is that hydrofluoric acid and silica reaction generate six silicon fluorides (SiF6), and the macromolecular compound in six silicon fluorides and the photoresist film further reacts the generation silicon-carbide particles, forms deposition at silicon chip then.
The existing method that produces the photoresist defective in the wet etching process that prevents comprises: 1) at photolithographic exposure and the back of developing photoresist film is is further baked and banked up with earth, form finer and close photoresist film, make the acid solution of wet etching be difficult to immerse from the slit between the photoresist macromolecular compound, generate defective with the effect of photoresist macromolecular compound; 2) at photolithographic exposure and the back of developing photoresist film is carried out ultraviolet light (UV) or plasma cured processing, form the crosslinked of macromolecular compound on the photoresist surface.Crosslinked macromolecule surface can improve the acid-resisting solution etch ability of photoresist effectively.US Patent No. 6498106B1 has reported that adopting low-energy plasma to solidify handles the case that prevents from producing in the wet etching process photoresist defective.
The problem that the existing method that prevents from the wet etching process producing the photoresist defective still exists some to solve.In method 1) in, baking and banking up with earth temperature should not be too high, and the time of baking and banking up with earth is unsuitable oversize.Otherwise can cause the photoresist figure deformation, and can have a negative impact to production throughput (throughput).Because the restriction that is subjected to baking and banking up with earth temperature and bakes and banks up with earth the time, the compactness of baking and banking up with earth the back photoresist film may can't satisfy the requirement of acid-resisting solution etch.Method 2) need after photoetching process, add ultraviolet light (UV) or plasma cured technology.Ultraviolet light (UV) or plasma cured arts demand are realized at other board, have not only increased equipment cost, and have prolonged the production time, have reduced the production throughput.
Summary of the invention
Technical problem to be solved by this invention is at having above-mentioned defective in the prior art, a kind of requirement that can satisfy the etch of acid-resisting solution is provided, can guaranteeing that also the photoresist that prevents of production throughput produces the process of defective in wet etching.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, provide a kind of photoresist that prevents to produce the process of defective in wet etching, it comprises: be coated with photoresist at the silicon chip that forms shallow isolated raceway groove and deposited silicon oxide film; Finish exposure and development to photoresist, with expose silicon oxide film will wet etching first region of silicon oxide and be subjected to second region of silicon oxide of photoresist protection; After exposure and developing, in carrying out the same developing machine platform that develops, in photoresist figure coating micro auxiliary film, and heating makes micro auxiliary film and photoresist surface reaction form the crosslinked diaphragm of macromolecule, thereby solidify the photoresist figure, remove unnecessary micro auxiliary film subsequently; Carry out wet etching partly to remove the silicon oxide film on first region of silicon oxide; Remove behind the residue photoresist cvd silicon oxide film again, thereby form the silicon oxide film Dual Gate Oxide of different-thickness in first region of silicon oxide and second region of silicon oxide.
According to a second aspect of the invention, provide a kind of photoresist that prevents to produce the process of defective in wet etching, it comprises: be coated with photoresist at the silicon chip that forms shallow isolated raceway groove and deposited silicon oxide film; Finish exposure and development to photoresist, with expose silicon oxide film will wet etching first region of silicon oxide and be subjected to second region of silicon oxide of photoresist protection; In same developing machine platform, in photoresist figure coating micro auxiliary film, heating makes micro auxiliary film and photoresist surface reaction form the crosslinked diaphragm of macromolecule, thereby solidifies the photoresist figure, removes unnecessary micro auxiliary film subsequently; Carry out wet etching to remove the silicon oxide film on first region of silicon oxide fully; Remove behind the residue photoresist cvd silicon oxide film again, thereby form the silicon oxide film Dual Gate Oxide of different-thickness in first region of silicon oxide and second region of silicon oxide.
Preferably, remove unnecessary micro auxiliary film with deionized water or the deionized water solution that contains surfactant.
Preferably, the vitrification point of photoresist main body macromolecular material+/-30 ℃.
Preferably, solidifying the scope of heating time is 15 seconds to 300 seconds; Preferably, 30 seconds to 120 seconds.
Preferably, select photoresist for I linear light carving technology, 248 nano-photoetching technologies, 193 nano-photoetching technologies, EUV photoetching process for use.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed, will more easily more complete understanding be arranged and more easily understand its attendant advantages and feature the present invention, wherein:
Fig. 1 to Fig. 5 schematically shows the manufacture craft flow process according to the Dual Gate Oxide of prior art.
Fig. 2 to Fig. 8 schematically shows the photoresist that prevents according to the present invention and produce the part steps of the process of defective in wet etching.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear and understandable more, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
＜the first embodiment 〉
Photoresist produces defective in wet etching the process that prevents according to first embodiment of the invention comprises:
Forming shallow isolated raceway groove 2 and depositing silicon chip 1 coating photoresist 4(Fig. 1 of silicon oxide film 3).For example, can select the photoresist that is fit to I linear light carving technology, 248 nano-photoetching technologies, 193 nano-photoetching technologies, EUV photoetching process for use.
Finish exposure and development to photoresist 4, with expose silicon oxide film 3 will wet etching first region of silicon oxide 5 and be subjected to second region of silicon oxide 6(Fig. 2 of photoresist 4 protections).
After exposure and developing; in carrying out the same developing machine platform that develops; at photoresist 4 figures coating micro auxiliary film (SAFIER; Shrink Assist Film for Enhanced Resolution); and heating makes micro auxiliary film SAFIER material and photoresist 4 surface reactions form the crosslinked diaphragm 7 of macromolecule; thereby solidify photoresist 4 figures, remove unnecessary micro auxiliary film SAFIER subsequently.For example, unnecessary micro auxiliary film SAFIER can remove (Fig. 6) with deionized water or the deionized water solution that contains surfactant.Preferably, micro auxiliary film SAFIER adopts the micro auxiliary film (SAFIER, Shrink Assist Film for Enhanced Resolution) that Tokyo Applied Chemistry Industrial Co., Ltd. (TOK, Tokyo Ohka Kogyo) produces.
And, preferably, the vitrification point of photoresist main body macromolecular material+/-30 ℃.。And preferably, the scope of solidifying heating time is 15 seconds to 300 seconds.Preferably, solidifying the scope of heating time is 30 seconds to 120 seconds.
Carry out wet etching partly to remove the silicon oxide film 3(Fig. 7 on first region of silicon oxide 5).
Remove behind the residue photoresist 4 cvd silicon oxide film 3 again, thereby form silicon oxide film 3 Dual Gate Oxide (Fig. 5) of different-thickness in first region of silicon oxide 5 and second region of silicon oxide 6.
Can finish subsequent technique subsequently, produce different field-effect transistors in first region of silicon oxide 5 with second region of silicon oxide 6.
＜the second embodiment 〉
Photoresist produces defective in wet etching the process that prevents according to second embodiment of the invention comprises:
Forming shallow isolated raceway groove 2 and depositing silicon chip 1 coating photoresist 4(Fig. 1 of silicon oxide film 3).For example, can select the photoresist that is fit to I linear light carving technology, 248 nano-photoetching technologies, 193 nano-photoetching technologies, EUV photoetching process for use.
Finish exposure and development to photoresist 4, with expose silicon oxide film 3 will wet etching first region of silicon oxide 5 and be subjected to second region of silicon oxide 6(Fig. 2 of photoresist 4 protections).
In same developing machine platform; at photoresist 4 figures coating micro auxiliary film (SAFIER; Resolution Enhancement Lithography Assisted by Chemical Shrink); heating makes micro auxiliary film SAFIER material and photoresist 4 surface reactions form the crosslinked diaphragm 7 of macromolecule; thereby solidify photoresist 4 figures, remove unnecessary micro auxiliary film SAFIER subsequently.For example, unnecessary micro auxiliary film SAFIER material can be removed (Fig. 6) with deionized water or the deionized water solution that contains surfactant.Preferably, micro auxiliary film SAFIER adopts the micro auxiliary film (SAFIER, Shrink Assist Film for Enhanced Resolution) that Tokyo Applied Chemistry Industrial Co., Ltd. (TOK, Tokyo Ohka Kogyo) produces.
And, preferably, the vitrification point of photoresist 4 main body macromolecular materials+/-30 ℃.And preferably, the scope of solidifying heating time is 15 seconds to 300 seconds.Preferably, 30 seconds to 120 seconds.
Carry out wet etching to remove the silicon oxide film 3(Fig. 8 on first region of silicon oxide 5 fully).
Remove behind the residue photoresist 4 cvd silicon oxide film 3 again, thereby form silicon oxide film 3 Dual Gate Oxide (Fig. 5) of different-thickness in first region of silicon oxide 5 and second region of silicon oxide 6.
Can finish subsequent technique subsequently, produce different field-effect transistors in first region of silicon oxide 5 with second region of silicon oxide 6.
According to above-described embodiment, can improve the compactness on photoresist 4 top layers effectively, improve photoresist 4 acid-resisting solution etch abilities, reduce photoresist 4 produces defective in the wet etching process probability, and do not need extra board, reduced processing step and cost of manufacture, improved production capacity.
Thus; the present invention is directed to the problems of the prior art; proposed to adopt micro auxiliary film SAFIER in developing machine platform, post-develop to be carved the method for glue pattern chemosetting processing at the crosslinked diaphragms 7 of photoresist 4 surface formation macromolecules; the requirement of acid-resisting solution etch can be satisfied, also the production throughput can be guaranteed.For example, micro auxiliary film (SAFIER) can adopt the micro auxiliary film (SAFIER, Shrink Assist Film for Enhanced Resolution) that Tokyo Applied Chemistry Industrial Co., Ltd. (TOK, Tokyo Ohka Kogyo) produces.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that though the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. one kind prevents that photoresist from producing the process of defective in wet etching, is characterized in that comprising:
Be coated with photoresist at the silicon chip that forms shallow isolated raceway groove and deposited silicon oxide film;
Finish exposure and development to photoresist, with expose silicon oxide film will wet etching first region of silicon oxide and be subjected to second region of silicon oxide of photoresist protection;
After exposure and developing, in carrying out the same developing machine platform that develops, in photoresist figure coating micro auxiliary film, and heating makes micro auxiliary film and photoresist surface reaction form the crosslinked diaphragm of macromolecule, thereby solidify the photoresist figure, remove unnecessary micro auxiliary film subsequently;
Carry out wet etching partly to remove the silicon oxide film on first region of silicon oxide;
Remove behind the residue photoresist cvd silicon oxide film again, thereby form the silicon oxide film Dual Gate Oxide of different-thickness in first region of silicon oxide and second region of silicon oxide.
2. one kind prevents that photoresist from producing the process of defective in wet etching, is characterized in that comprising:
Be coated with photoresist at the silicon chip that forms shallow isolated raceway groove and deposited silicon oxide film;
Finish exposure and development to photoresist, with expose silicon oxide film will wet etching first region of silicon oxide and be subjected to second region of silicon oxide of photoresist protection;
In same developing machine platform, in photoresist figure coating micro auxiliary film, heating makes micro auxiliary film and photoresist surface reaction form the crosslinked diaphragm of macromolecule, thereby solidifies the photoresist figure, removes unnecessary micro auxiliary film subsequently;
Carry out wet etching to remove the silicon oxide film on first region of silicon oxide fully;
Remove behind the residue photoresist cvd silicon oxide film again, thereby form the silicon oxide film Dual Gate Oxide of different-thickness in first region of silicon oxide and second region of silicon oxide.
3. the photoresist that prevents according to claim 1 and 2 produces the process of defective in wet etching, it is characterized in that, removes unnecessary micro auxiliary film with deionized water or the deionized water solution that contains surfactant.
4. the photoresist that prevents according to claim 1 and 2 produces the process of defective in wet etching, the vitrification point of photoresist main body macromolecular material+/-30 ℃.
5. the photoresist that prevents according to claim 1 and 2 produces the process of defective in wet etching, it is characterized in that, the scope of solidifying heating time is 15 seconds to 300 seconds.
6. the photoresist that prevents according to claim 1 and 2 produces the process of defective in wet etching, it is characterized in that, the scope of solidifying heating time is 30 seconds to 120 seconds.
7. the photoresist that prevents according to claim 1 and 2 produces the process of defective in wet etching, it is characterized in that, selects the photoresist for I linear light carving technology, 248 nano-photoetching technologies, 193 nano-photoetching technologies, EUV photoetching process for use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100851979A CN103199016A (en) | 2013-03-15 | 2013-03-15 | Process method for preventing occurrence of defects of photoresist in wet etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100851979A CN103199016A (en) | 2013-03-15 | 2013-03-15 | Process method for preventing occurrence of defects of photoresist in wet etching |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103199016A true CN103199016A (en) | 2013-07-10 |
Family
ID=48721475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100851979A Pending CN103199016A (en) | 2013-03-15 | 2013-03-15 | Process method for preventing occurrence of defects of photoresist in wet etching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103199016A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110989292A (en) * | 2019-12-10 | 2020-04-10 | 东莞市友辉光电科技有限公司 | Method for preparing fine texture on substrate |
| CN112516804A (en) * | 2019-09-18 | 2021-03-19 | 无锡华润微电子有限公司 | PM2.5 protective equipment, PM2.5 filtering membrane and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080199814A1 (en) * | 2006-12-06 | 2008-08-21 | Fujifilm Electronic Materials, U.S.A., Inc. | Device manufacturing process utilizing a double patterning process |
| CN101796631A (en) * | 2007-09-07 | 2010-08-04 | 飞思卡尔半导体公司 | Dual gate oxide device is integrated |
| US20100311244A1 (en) * | 2009-06-09 | 2010-12-09 | Shanghai Ic R&D Center Co., Ltd. | Double-exposure method |
| CN102760696A (en) * | 2012-07-27 | 2012-10-31 | 上海华力微电子有限公司 | Through hole priority copper interconnection manufacturing method |
-
2013
- 2013-03-15 CN CN2013100851979A patent/CN103199016A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080199814A1 (en) * | 2006-12-06 | 2008-08-21 | Fujifilm Electronic Materials, U.S.A., Inc. | Device manufacturing process utilizing a double patterning process |
| CN101796631A (en) * | 2007-09-07 | 2010-08-04 | 飞思卡尔半导体公司 | Dual gate oxide device is integrated |
| US20100311244A1 (en) * | 2009-06-09 | 2010-12-09 | Shanghai Ic R&D Center Co., Ltd. | Double-exposure method |
| CN102760696A (en) * | 2012-07-27 | 2012-10-31 | 上海华力微电子有限公司 | Through hole priority copper interconnection manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112516804A (en) * | 2019-09-18 | 2021-03-19 | 无锡华润微电子有限公司 | PM2.5 protective equipment, PM2.5 filtering membrane and preparation method thereof |
| CN110989292A (en) * | 2019-12-10 | 2020-04-10 | 东莞市友辉光电科技有限公司 | Method for preparing fine texture on substrate |
| CN110989292B (en) * | 2019-12-10 | 2023-03-17 | 东莞市友辉光电科技有限公司 | Method for preparing fine texture on substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI380350B (en) | Double patterning strategy for contact hole and trench in photolithography | |
| US20060292497A1 (en) | Method of forming minute pattern of semiconductor device | |
| US9087875B2 (en) | Pattern formation method for manufacturing semiconductor device using phase-separating self-assembling material | |
| US9069249B2 (en) | Self aligned patterning with multiple resist layers | |
| US9640410B2 (en) | Pattern formation method | |
| CN107168010B (en) | Method for manufacturing photoetching mask | |
| US20120129316A1 (en) | Method for forming fine pattern of semiconductor device | |
| US9543160B2 (en) | Reducing defects in patterning processes | |
| CN103258795A (en) | Technological method capable of preventing shortcomings on photoresist during wet etching | |
| JP2009239030A (en) | Method of manufacturing semiconductor device | |
| CN103199016A (en) | Process method for preventing occurrence of defects of photoresist in wet etching | |
| US20120276745A1 (en) | Method for fabricating hole pattern in semiconductor device | |
| US20090061635A1 (en) | Method for forming micro-patterns | |
| CN103165533A (en) | Process method for preventing defects of photoresist during wet etching | |
| US20070298333A1 (en) | Manufacturing process of an organic mask for microelectronic industry | |
| US8758984B2 (en) | Method of forming gate conductor structures | |
| CN103258733A (en) | Technological method capable of preventing shortcomings on photoresist during wet etching | |
| CN103197513A (en) | Technical method for preventing photoresist from generating defects during wet etching | |
| US11500293B2 (en) | Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer | |
| CN101320712B (en) | Method for fabricating semiconductor device | |
| US8835101B1 (en) | Method for fabricating a circuit | |
| CN102879996A (en) | Method for manufacturing phase shift photomask | |
| CN105573045B (en) | Photomask, manufacturing method of semiconductor device and semiconductor device | |
| TWI229905B (en) | Method for controlling critical dimension by utilizing resist sidewall protection | |
| CN103258794A (en) | Technological method capable of preventing shortcomings on photoresist during wet etching |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130710 |