CN101556934A

CN101556934A - Manufacturing method of shallow ridge in semiconductor

Info

Publication number: CN101556934A
Application number: CNA2009100515454A
Authority: CN
Inventors: 张�雄; 张博; 孔蔚然
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-05-19
Filing date: 2009-05-19
Publication date: 2009-10-14

Abstract

The invention provides a manufacturing method of shallow ridge which is applicable to forming shallow ridges in a substrate layer. The invention is characterized in that the manufacturing method comprises the steps as follows: a grid oxide layer, a polysilicon grid layer and a silicon nitride hard mask layer are formed on the substrate layer in sequence; optical resist is coated on the silicon nitride hard mask layer and is then moulded into a patterned optical resist layer; the patterned optical resist layer is used as a mask to carry out etching, thereby penetrating the silicon nitride hard mask layer and halting on the polysilicon grid layer; the patterned optical resist layer is removed; and the silicon nitride hard mask layer is used as a mask to carry out shallow ridged etching, thus obtaining a shallow ridge in the substrate layer. The process provided in the invention carries out small-scale etchings twice and uses the silicon nitride hard mask layer to conduct the second etching to form a shallow ridge, thereby brining in less etching load, possessing better line width control and facilitating further reduction of device dimension.

Description

The manufacture method of shallow slot in the semiconductor

Technical field

The present invention relates to a kind of semiconductor fabrication process flow process, more relate to the manufacture method of shallow slot in a kind of semiconductor.

Background technology

Subsist today closely in that element is integrated, it is very important that the isolation between the element becomes, and for anti-adjacent transistors here is short-circuited, can add an isolation structure betwixt usually.

The technology that element separation is general is a silicon selective oxidation technology (LOCOS).Yet Locos still has multinomial shortcoming, comprises the formation etc. of beak district (bird ' sbeak) on every side of relevant issues that known stress produces and LOCOS field isolation structure.And the problem that caused of beak district particularly makes that the LOCOS field isolation structure on miniaturized component can not be isolated effectively.

In view of this, there to be other element separation method to continue to be developed, wherein (Shallow Trench Isolation STI) is widely used most, to strengthen isolating MOS transistor with shallow-trench isolation in technology.

Shown in Fig. 1 a～Fig. 1 c, existing shallow trench isolation from manufacturing process on basalis 101, forming pad oxide 102 and silicon nitride mask 104 in regular turn.On silicon nitride mask layer 104, cover one deck photoresist then, and to photoresist expose, developing process, to form the photoresist layer 106 of patterning.Then, be mask with the photoresist layer 106 of patterning, carry out etch process, in substrate 101, form shallow slot 107.

This technology has bigger etching load, is not easy to carry out live width control, therefore is unfavorable for the reduction of device size.

Summary of the invention

The present invention proposes shallow slot manufacture craft in a kind of semiconductor, can address the above problem.

In order to achieve the above object, the present invention proposes a kind of shallow slot manufacture method, is used for forming shallow slot at basalis, it is characterized in that, may further comprise the steps:

On basalis, form gate oxide, polycrystalline silicon grid layer and silicon nitride hard mask layer successively;

On the silicon nitride hard mask layer, apply photoresist, and photoresist is formed the photoresist layer of patterning;

With the patterning photoresist layer is mask, carries out etching, passes the silicon nitride hard mask layer and is parked on the polycrystalline silicon grid layer;

Remove the patterning photoresist layer; And

With the silicon nitride hard mask layer is mask, carries out the shallow slot etching, forms shallow slot in basalis.

Optionally, the material of gate oxide is a silica, and the formation method is a thermal oxidation method.

Optionally, the formation method of silicon nitride hard mask layer is a chemical vapour deposition technique.

Optionally, the photoresist layer of formation patterning is to have utilized the method that photoresist is exposed, develops.

The technology that the present invention proposes, because carried out twice small-scale etching, and utilized the silicon nitride hard mask layer to carry out the etching second time and formed shallow slot, introducing etching load has still less been arranged, better live width control is arranged, help the further reduction of device size.

Description of drawings

Fig. 1 a～1c is depicted as the process flow diagram that forms shallow slot at present in basalis;

Fig. 2 a～Fig. 2 f is depicted as the process flow diagram that forms shallow slot in basalis that the present invention proposes.

Embodiment

In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.

Fig. 2 a～Fig. 2 f is depicted as the manufacturing process steps of shallow slot in the preferred embodiment of the present invention:

At first, on basalis 201, form gate oxide 202, polysilicon (Polycrystalline silicon) grid layer 203, silicon nitride hard mask layer 204 (shown in Fig. 2 a).Wherein, the material of gate oxide 202 for example is a silica, and the formation method comprises thermal oxidation method (Thermal Oxidation).The formation method of silicon nitride hard mask layer 204 comprise chemical vapour deposition technique (Chemical Vapor Deposition, CVD).

Then, apply one deck photoresist 205 (shown in Fig. 2 b) on silicon nitride hard mask layer 204, the mode that applies photoresist 205 can be that elder generation drips to photoresist 205 on the silicon nitride hard mask layer 204, rotates wafer again, makes photoresist 205 coatings evenly.

Then, photoresist 205 is carried out patterned process, form the photoresist layer 206 (shown in Fig. 2 c) of patterning.Wherein, patterning photoresist 205 comprises steps such as exposure, development.

Next the photoresist layer 206 with patterning is a mask, carries out etching, is parked in (shown in Fig. 2 d) on the polycrystalline silicon grid layer 203.In this step, in silicon nitride hard mask layer 204, formed groove 207.

Remove patterning photoresist layer 206 (shown in Fig. 2 e).

With silicon nitride hard mask layer 204 is mask, carries out the shallow slot etching, is forming shallow slot 208 (shown in Fig. 2 f) in the basalis 201.

Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims

1. a shallow slot manufacture method is used for forming shallow slot at basalis, it is characterized in that, may further comprise the steps:

On above-mentioned silicon nitride hard mask layer, apply photoresist, and above-mentioned photoresist is formed the photoresist layer of patterning;

With above-mentioned patterning photoresist layer is mask, carries out etching, passes above-mentioned silicon nitride hard mask layer and is parked on the above-mentioned polycrystalline silicon grid layer;

Remove above-mentioned patterning photoresist layer; And

With above-mentioned silicon nitride hard mask layer is mask, carries out the shallow slot etching, forms shallow slot in basalis.

2. temperature-controlled process according to claim 1 is characterized in that the material of above-mentioned gate oxide is a silica, and the formation method is a thermal oxidation method.

3. temperature-controlled process according to claim 1 is characterized in that, the formation method of above-mentioned silicon nitride hard mask layer is a chemical vapour deposition technique.

4. temperature-controlled process according to claim 1 is characterized in that, the photoresist layer that forms above-mentioned patterning is to have utilized the method that photoresist is exposed, develops.