CN117174659A - Method for manufacturing transistor - Google Patents
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- CN117174659A CN117174659A CN202311228948.8A CN202311228948A CN117174659A CN 117174659 A CN117174659 A CN 117174659A CN 202311228948 A CN202311228948 A CN 202311228948A CN 117174659 A CN117174659 A CN 117174659A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000000059 patterning Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 230000000903 blocking effect Effects 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 150000002894 organic compounds Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application provides a method for manufacturing a transistor. The method comprises the following steps: providing a substrate; sequentially forming a dielectric layer, a conductive layer and a barrier layer on the surface of the substrate; patterning the conductive layer and the barrier layer to expose a portion of the dielectric layer, and forming a doped region in the substrate using the patterned conductive layer and the patterned barrier layer as a hard mask. According to the technical scheme, the dielectric layer, the conductive layer and the barrier layer are sequentially formed on the surface of the substrate, the conductive layer and the barrier layer are subjected to patterning treatment, and then the patterned conductive layer and the patterned barrier layer are used as hard masks, so that a doped region is formed in the substrate. And on the basis, the subsequent grid forming process is performed, so that the overlapping width of the grid and the doped region can be accurately controlled, and the stability of the transistor is improved.
Description
Technical Field
The application relates to the technical field of semiconductor processing, in particular to a manufacturing method of a transistor.
Background
Generally, an integrated circuit includes at least one of an N-type transistor (NMOS), a P-type transistor (PMOS), and a Complementary-Metal-Oxide-Semiconductor (CMOS). Wherein the performance of an integrated circuit is directly related to the performance of the transistors it contains.
Please refer to fig. 1A to 1E, which are schematic views of a device structure corresponding to main steps of a transistor forming process in the prior art. As shown in fig. 1A, a substrate 10 is provided. As shown in fig. 1B, a patterned hard mask 11 is formed on the surface of the substrate 10. As shown in fig. 1C, the hard mask 11 is used as a shielding material to perform ion implantation on the substrate 10 to form a first doped region 12 and a second doped region 13, wherein the first doped region 12 is a source or a drain, and the second doped region 13 is a drain or a source. As shown in fig. 1D, the hard mask 11 is removed and a polysilicon layer 14 is deposited on the surface of the substrate 10. As shown in fig. 1E, the polysilicon layer 14 is etched to form a gate electrode 15.
In the conventional transistor manufacturing process, the doped regions (the first doped region 12 and the second doped region 13 as shown in fig. 1E) in the transistor overlap with the gate 15 in a partial region, and a mask is generally used to control the overlapping region in the manufacturing process, where the width of the overlapping region has a greater influence on the electrical parameters of the device; meanwhile, the width of the overlapped area is difficult to control accurately due to the fact that the line width of the device is smaller and the process of the mask is limited, and the drift of the overlapped area cannot meet the stability of the transistor.
Disclosure of Invention
The application aims to provide a manufacturing method of a transistor, which can accurately control the width of an overlapping area and improve the stability of the transistor.
In order to solve the above problems, the present application provides a method for manufacturing a transistor, comprising the steps of: providing a substrate; sequentially forming a dielectric layer, a conductive layer and a barrier layer on the surface of the substrate; patterning the conductive layer and the barrier layer to expose a portion of the dielectric layer, and forming a doped region in the substrate using the patterned conductive layer and the patterned barrier layer as a hard mask.
In some embodiments, the substrate includes a first region and a second region, the patterning the conductive layer and the barrier layer, using the patterned conductive layer and barrier layer as a hard mask, and the step of forming a doped region in the substrate further includes: patterning the conductive layer and the barrier layer of the first region to expose a portion of the dielectric layer in the first region; forming a first conductive type doped region in the first region by using the conductive layer and the blocking layer after the first region is patterned as a hard mask; forming a filling layer covering the exposed dielectric layer, the patterned conductive layer and the barrier layer; patterning the conductive layer and the barrier layer of the second region to expose a portion of the dielectric layer in the second region; and forming a second conductive type doped region in the second region by using the filling layer and the conductive layer and the blocking layer after the second region is patterned as a hard mask.
In some embodiments, the first region is an NMOS region and the first conductivity type is N-type; the second region is a PMOS region, and the second conductivity type is P-type.
In some embodiments, the first conductivity type doped region and the second conductivity type doped region are formed using an ion implantation process.
In some embodiments, the method further comprises the steps of: removing the patterned barrier layer; forming a gate conductive layer covering the patterned conductive layer on the surface of the substrate; and patterning the grid conductive layer to form a grid.
In some embodiments, the substrate includes a first region and a second region, the step of forming the gate further comprising: and forming a first grid electrode in the first region and forming a second grid electrode in the second region.
In some embodiments, the gate is formed by etching the gate conductive layer using dry etching.
In some embodiments, the material of the dielectric layer is silicon oxide.
In some embodiments, the material of the conductive layer is polysilicon.
In some embodiments, the material of the barrier layer is photoresist.
According to the technical scheme, the dielectric layer, the conductive layer and the barrier layer are sequentially formed on the surface of the substrate, the conductive layer and the barrier layer are subjected to patterning treatment, and then the patterned conductive layer and the patterned barrier layer are used as hard masks, so that a doped region is formed in the substrate. And on the basis, the subsequent grid forming process is performed, so that the overlapping width of the grid and the doped region can be accurately controlled, and the stability of the transistor is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1A to 1E are schematic views of a device structure corresponding to main steps of a transistor forming process in the prior art;
FIG. 2 is a schematic diagram showing the implementation steps of a method for manufacturing a transistor according to an embodiment of the present application;
fig. 3A to 3F are schematic device structures corresponding to main steps of a method for manufacturing a transistor according to an embodiment of the present application;
fig. 4A to fig. 4F are schematic device structures corresponding to main steps of another embodiment of a method for manufacturing a transistor according to the present application;
FIG. 5 is a schematic diagram showing the steps performed to pattern the conductive layer and the barrier layer and form doped regions in accordance with one embodiment of the present application;
fig. 6A to 6E are schematic device structures corresponding to main steps of patterning the conductive layer and the barrier layer and forming doped regions according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art without the exercise of inventive faculty, are intended to be within the scope of the present application, based on the embodiments herein.
An embodiment of the application provides a method for manufacturing a transistor.
Please refer to fig. 2, which is a schematic diagram illustrating steps performed in an embodiment of a method for manufacturing a transistor according to the present application. As shown in fig. 2, the method for manufacturing a transistor according to this embodiment includes: step S201, providing a substrate; step S202, sequentially forming a dielectric layer, a conductive layer and a barrier layer on the surface of the substrate; and step 203, patterning the conductive layer and the barrier layer to expose part of the dielectric layer, and forming a doped region in the substrate by using the patterned conductive layer and the patterned barrier layer as a hard mask. The method further comprises the steps of: step S204, removing the patterned barrier layer; step S205, forming a grid conductive layer covering the patterned conductive layer on the surface of the substrate; step S206, patterning the gate conductive layer to form a gate.
According to the technical scheme, the dielectric layer, the conductive layer and the blocking layer are sequentially formed on the surface of the substrate, patterning is conducted on the conductive layer and the blocking layer to expose part of the dielectric layer, and then the patterned conductive layer and the patterned blocking layer are used as a hard mask, so that a doped region is formed in the substrate. And on the basis, the subsequent grid forming process is performed, so that the overlapping width of the grid and the doped region can be accurately controlled, and the stability of the transistor is improved.
Fig. 3A to 3F are schematic device structures corresponding to main steps of a method for manufacturing a transistor according to an embodiment of the present application.
Referring to fig. 3A, referring to step S201, a substrate 30 is provided. In this embodiment substrate 30 is a monocrystalline silicon wafer. In other embodiments, the substrate 30 may be made of any one of the common substrate materials used to form semiconductor devices, such as single crystal silicon, silicon germanium, silicon on insulator, silicon carbide, gallium nitride, gallium arsenide, and sapphire.
Referring to fig. 3B, referring to step S202, a dielectric layer 31, a conductive layer 32, and a barrier layer 33 are sequentially formed on the surface of the substrate 30.
In this embodiment, the material of the dielectric layer 31 is silicon oxide. The dielectric layer 31 serves as a device isolation. Specifically, the dielectric layer 31 is formed on the surface of the substrate 30 by a plasma chemical vapor deposition method. In other embodiments, the dielectric layer 31 may be formed on the surface of the substrate 30 by a thermal oxidation method.
In this embodiment, the material of the conductive layer 32 is polysilicon. The conductive layer 32 may be part of a subsequently formed gate. Specifically, the conductive layer 32 is formed on the surface of the dielectric layer 31 by chemical vapor deposition.
In this embodiment, the material of the blocking layer 33 is photoresist. Further, a photoresist is coated on the surface of the conductive layer 32 to form the barrier layer 33. Photoresists (PR) are also known as photoresists, which are organic compounds that are sensitive to light and change in solubility in a developer after exposure to ultraviolet light. The pattern on the mask can be transferred to the photoresist layer on the top layer of the wafer surface through the photoresist.
Referring to fig. 3C, referring to step S203, the conductive layer 32 and the barrier layer 33 are patterned to expose a portion of the dielectric layer 31, and a doped region 34 is formed in the substrate 30 by using the patterned conductive layer 32 and the patterned barrier layer 33 as a hard mask.
In this embodiment, the barrier layer 33 is subjected to photolithography and development to achieve patterning. Further, the patterned barrier layer 33 is used as a mask, and the conductive layer 32 is etched, so that the conductive layer 32 is patterned as well.
In this embodiment, the patterned conductive layer 32 and the patterned barrier layer 33 are used as a hard mask, and an ion implantation process is used to form the doped region 34 on the substrate 30. Further, the doped region 34 serves as a source and drain of the transistor.
Referring to fig. 3D, referring to step S204, the patterned barrier layer 33 is removed.
In this embodiment, the material of the barrier layer 33 is photoresist, and wet photoresist stripping is used to remove the barrier layer 33. In other embodiments, other methods may be used to remove the barrier layer 33.
Referring to fig. 3E, referring to step S205, a gate conductive layer 35 is formed on the surface of the substrate 30 to cover the patterned conductive layer 32.
In this embodiment, the material of the gate conductive layer 35 is polysilicon. That is, the gate conductive layer 35 and the conductive layer 32 may be made of the same material. The gate conductive layer 35 may be part of a subsequently formed gate. Specifically, the gate conductive layer 35 is formed on the surface of the conductive layer 32 by chemical vapor deposition.
Referring to fig. 3F, referring to step S206, the gate conductive layer 35 is patterned to form a gate 36.
In this embodiment, the gate electrode 36 is formed by etching the gate conductive layer 35 by dry etching. By forming the doped region 34 and then forming the gate 36, the width of the overlapping region of the gate 36 and the doped region 34 can be precisely controlled, thereby improving the stability of the transistor formed.
Fig. 4A to fig. 4F are schematic device structures corresponding to main steps of another embodiment of a method for manufacturing a transistor according to the present application.
Referring to fig. 4A, referring to step S201, a substrate 40 is provided. In this embodiment, the substrate 40 includes a first region 401 and a second region 402, where the first region 401 and the second region 402 are regions where transistors are to be formed. Further, the first region 401 is an NMOS region, and the first region 402 is a PMOS region. In other embodiments, the substrate 40 may have multiple regions where transistors are to be formed.
Referring to fig. 4B, referring to step S202, a dielectric layer 41, a conductive layer 42, and a barrier layer 43 are sequentially formed on the surface of the substrate 40.
In this embodiment, the material of the dielectric layer 41 is silicon oxide. The dielectric layer 41 serves as a device isolation. Specifically, the dielectric layer 41 is formed on the surface of the substrate 40 by a plasma chemical vapor deposition method. In other embodiments, the dielectric layer 41 may be formed on the surface of the substrate 40 by a thermal oxidation method.
In this embodiment, the material of the conductive layer 42 is polysilicon. The conductive layer 42 may be part of a subsequently formed gate. Specifically, the conductive layer 42 is formed on the surface of the dielectric layer 41 by chemical vapor deposition.
In this embodiment, the material of the blocking layer 43 is photoresist. Further, a photoresist is coated on the surface of the conductive layer 42 to form the barrier layer 43. Photoresists (PR) are also known as photoresists, which are organic compounds that are sensitive to light and change in solubility in a developer after exposure to ultraviolet light. The pattern on the mask can be transferred to the photoresist layer on the top layer of the wafer surface through the photoresist.
Referring to fig. 4C, referring to step S203, the conductive layer 42 and the blocking layer 43 are patterned to expose a portion of the dielectric layer 41, and a doped region 44 is formed in the substrate 40 by using the patterned conductive layer 42 and blocking layer 43 as a hard mask.
In this embodiment, the specific steps of patterning the conductive layer 42 and the barrier layer 43 and forming the doped region 44 are shown in fig. 5, and include the following steps: step S501 of patterning the conductive layer 42 and the barrier layer 43 of the first region 401 to expose a portion of the dielectric layer 41 in the first region 401; step S502, forming a first conductivity type doped region 441 in the first region 401 by using the patterned conductive layer 42 and the patterned barrier layer 43 of the first region 401 as a hard mask; step S503, forming a filling layer 61 covering the exposed dielectric layer 41, the patterned conductive layer 42 and the barrier layer 43; step S504, patterning the conductive layer 42 and the barrier layer 43 of the second region 402 to expose a portion of the dielectric layer 41 in the second region 402; in step S505, a second conductivity type doped region 442 is formed in the second region 402 by using the filling layer 61 and the patterned conductive layer 42 and the patterned barrier layer 43 of the second region 402 as hard masks.
Fig. 6A to 6E are schematic device structures corresponding to main steps of patterning the conductive layer and the barrier layer and forming a doped region in another embodiment of the method for manufacturing a transistor according to the present application.
Referring to fig. 6A, referring to step S501, the conductive layer 42 and the barrier layer 43 of the first region 401 are patterned to expose a portion of the dielectric layer 41 in the first region 401. In this embodiment, since the material of the barrier layer 43 is photoresist, the barrier layer 43 of the first region 401 is patterned by photolithography and development. Further, the patterned barrier layer 43 is used as a mask to etch the conductive layer 42 of the first region 401, so as to realize patterning of the conductive layer 42 of the first region 401.
Referring to fig. 6B, referring to step S502, a first conductivity type doped region 441 is formed in the first region 401 by using the patterned conductive layer 42 and the patterned barrier layer 43 of the first region 401 as a hard mask. In this embodiment, the first region 401 is an NMOS region, and the first conductivity type doped region formed in the first region 401 is an N-type. Further, ion implantation is performed to the first region 401 of the substrate 40 to form the first conductive type doped region 441.
Referring to fig. 6C, referring to step S503, a filling layer 61 is formed to cover the exposed dielectric layer 41, the patterned conductive layer 42 and the barrier layer 43. In this embodiment, the filling layer 61 is used to prevent contamination of the first conductive type doped region 441 when the second region 402 is ion-implanted. Further, the material of the filling layer 61 is the same as the material of the blocking layer 43.
Referring to fig. 6D, referring to step S504, the conductive layer 42 and the barrier layer 43 of the second region 402 are patterned to expose a portion of the dielectric layer 41 in the second region 402. In this embodiment, the blocking layer 43 of the second region 402 of the substrate 40 is patterned by photolithography and development. Further, the patterned barrier layer 43 is used as a mask to etch the conductive layer 42 of the second region 402, so as to realize patterning of the conductive layer 42 of the second region 402.
Referring to fig. 6E, referring to step S505, a second conductivity type doped region 442 is formed in the second region 402 by using the filling layer 61 and the patterned conductive layer 42 and the patterned barrier layer 43 of the second region 402 as hard masks. In this embodiment, the second region 402 is a PMOS region, and the second conductivity type doped region formed in the second region 402 is P-type. Further, ion implantation is performed into the second region 402 of the substrate 40 to form the second conductivity-type doped region 442.
Referring to fig. 4D, referring to step S204, the patterned barrier layer 43 is removed.
In this embodiment, the patterned barrier layer 43 is removed by dry photoresist removal. In other embodiments, a wet or other method may be used to remove the barrier layer 43. When the filling layer 61 is further formed on the substrate 40, the step of removing the patterned barrier layer 43 simultaneously removes the filling layer 61.
Referring to fig. 4E, referring to step S205, a gate conductive layer 45 covering the patterned conductive layer 42 is formed on the surface of the substrate 40.
In this embodiment, the material of the gate conductive layer 45 is polysilicon. That is, the gate conductive layer 45 and the conductive layer 42 may be made of the same material. The gate conductive layer 45 may be part of a subsequently formed gate. Specifically, the gate conductive layer 45 is formed on the surface of the conductive layer 42 by chemical vapor deposition.
Referring to fig. 4F, referring to step S206, the gate conductive layer 45 is patterned to form a gate 46.
In this embodiment, the step of forming the gate 46 further includes forming a first gate 461 in the first region 401 and forming a second gate 462 in the second region 402. The gate conductive layer 45 is etched by dry etching to form a gate 46.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the statement "comprises" and "comprising" does not exclude the presence of other elements than those listed in any process, method, article, or apparatus that comprises the element. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present application.
The embodiments of the present application are described in a related manner, and identical and similar parts of the embodiments are all referred to each other, and each embodiment is mainly different from other embodiments.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the scope of the present application. It should be noted that modifications and adaptations to the present application may occur to one skilled in the art without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.
Claims (10)
1. A method of manufacturing a transistor, comprising the steps of:
providing a substrate;
sequentially forming a dielectric layer, a conductive layer and a barrier layer on the surface of the substrate;
patterning the conductive layer and the barrier layer to expose a portion of the dielectric layer, and forming a doped region in the substrate using the patterned conductive layer and the patterned barrier layer as a hard mask.
2. The method of claim 1, wherein the substrate comprises a first region and a second region, the patterning the conductive layer and the barrier layer using the patterned conductive layer and barrier layer as a hard mask, and the step of forming a doped region in the substrate further comprises: patterning the conductive layer and the barrier layer of the first region to expose a portion of the dielectric layer in the first region;
forming a first conductive type doped region in the first region by using the conductive layer and the blocking layer after the first region is patterned as a hard mask;
forming a filling layer covering the exposed dielectric layer, the patterned conductive layer and the barrier layer;
patterning the conductive layer and the barrier layer of the second region to expose a portion of the dielectric layer in the second region;
and forming a second conductive type doped region in the second region by using the filling layer and the conductive layer and the blocking layer after the second region is patterned as a hard mask.
3. The method of claim 2, wherein the first region is an NMOS region and the first conductivity type is N-type; the second region is a PMOS region, and the second conductivity type is P-type.
4. The method of claim 2, wherein the first conductivity type doped region and the second conductivity type doped region are formed using an ion implantation process.
5. The method of claim 1, further comprising the step of:
removing the patterned barrier layer;
forming a gate conductive layer covering the patterned conductive layer on the surface of the substrate;
and patterning the grid conductive layer to form a grid.
6. The method of claim 5, wherein the substrate comprises a first region and a second region, the step of forming the gate further comprising:
and forming a first grid electrode in the first region and forming a second grid electrode in the second region.
7. The method of claim 5, wherein the gate electrode is formed by etching the gate conductive layer using dry etching.
8. The method of claim 1, wherein the material of the dielectric layer is silicon oxide.
9. The method of claim 1, wherein the conductive layer is polysilicon.
10. The method of claim 1, wherein the material of the barrier layer is photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311228948.8A CN117174659A (en) | 2023-09-21 | 2023-09-21 | Method for manufacturing transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311228948.8A CN117174659A (en) | 2023-09-21 | 2023-09-21 | Method for manufacturing transistor |
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| Publication Number | Publication Date |
|---|---|
| CN117174659A true CN117174659A (en) | 2023-12-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311228948.8A Pending CN117174659A (en) | 2023-09-21 | 2023-09-21 | Method for manufacturing transistor |
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| CN (1) | CN117174659A (en) |
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- 2023-09-21 CN CN202311228948.8A patent/CN117174659A/en active Pending
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