CN102339782A - Production method of shallow channel isolation region - Google Patents
Production method of shallow channel isolation region Download PDFInfo
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- CN102339782A CN102339782A CN2010102292345A CN201010229234A CN102339782A CN 102339782 A CN102339782 A CN 102339782A CN 2010102292345 A CN2010102292345 A CN 2010102292345A CN 201010229234 A CN201010229234 A CN 201010229234A CN 102339782 A CN102339782 A CN 102339782A
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- mask layer
- shallow trench
- trench isolation
- isolation regions
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Abstract
The invention relates to a production method of a shallow channel isolation region, which comprises the following steps that: a semiconductor underlay is provided, a mask layer is formed on the semiconductor underlay, the semiconductor underlay is etched to form a channel, an oxidized isolation layer is formed to fill the channel, etching-back processing on the mask layer is undertaken after the oxidized isolation layer is smoothened, a gap is formed between the oxidized isolation layer and the mask layer, and an oxidized layer is formed to fill the gap. By forming the gap between the mask layer and the oxidized isolation layer and by filling the gap with the oxidized layer, not only can the hollow formation problem inside the oxidized isolation layer be avoided, but also the corrosion is difficult to happen in the subsequent wet-method washing process, and the broken corner formation problem on the top edge of the shallow channel isolation region can be effectively reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of manufacture method of shallow trench isolation regions.
Background technology
In recent years, along with the development of semiconductor integrated circuit manufacturing technology, the quantity of contained element constantly increases in the chip, and size of component is also constantly dwindled because of the lifting of integrated level, and the line width that uses on the production line has got into the tiny scope of inferior micron.Yet no matter how downsizing of component size still must have suitably insulation or isolates between each element in chip, just can obtain good component properties.The technology of this respect generally becomes element separation technology (Device Isolation Technology); Its main purpose is between each element, to form spacer; And under the situation of guaranteeing the good effect; Dwindle the zone of spacer as far as possible, hold more element to vacate more chip area.
In various element separation technology; Localized oxidation of silicon method (LOCOOS) and shallow trench isolation regions (Shallow Trench Isolation; STI) manufacture process is the most normal adopted two kinds of technology; Especially the latter have area of isolation little with accomplish after still keep advantage such as substantially flat property, quite valued in recent years especially semiconductor fabrication.Shallow trench isolation regions is the general partition method that the following semiconductor technology of 0.25um adopts, and the advantage of this partition method is that isolation effect is good, and area occupied is little.But STI also has a lot of technical problems on technology, like the morphology control of STI, the corners of STI drift angle, the silicon dioxide of STI inside and the unfilled corner problem (STI Divot) of adaptive stress between the outside silicon and shallow trench isolation regions top etc.Wherein, Fig. 1 is the sketch map of the unfilled corner problem of shallow trench isolation regions top in the prior art; With reference to figure 1, in removing mask layer 102 ' step, said mask layer 102 ' is carried out wet-cleaned, can corrode the top of said oxidation separator 103 ' in the said wet-cleaned process; Cause the unfilled corner problem 10 of more even bigger shallow trench isolation regions top; The problem that the unfilled corner 10 of shallow trench isolation regions top causes can be directly connected to the electric leakage problem at STI edge, can influence Devices Characteristics, causes parasitic current path owing to the formation of the unfilled corner 10 of shallow trench isolation regions top causes forming inversion layer in the side of active area when the grid of filling; And then influence Devices Characteristics; And the unfilled corner 10 of crossing dark shallow trench isolation regions top can strengthen the difficulty of polysilicon gate and silicon nitride side wall etching, and possibly cause etching residual, and the size and the depth of therefore controlling the unfilled corner 10 of shallow trench isolation regions top have more and more caused people's attention.
Fig. 2 is for doing back the structural representation of carving after handling to mask layer in the prior art after forming raceway groove, Fig. 3 is the sketch map of oxidation separator interior void in the prior art, below please combine Fig. 2 and Fig. 3.In the prior art, in comparatively advanced manufacturing process, for preventing unfilled corner 10 problems of relatively poor shallow trench isolation regions top.The step and the deposition that form raceway groove in etching form between the oxidation separator 103 ' step; Also need return to carve and handle mask layer 102 '; Promptly between said mask layer 102 ' and said raceway groove, form the gap; The step 20 that exposes said raceway groove two edges, deposition forms oxidation separator 103 ' again.But this method also has problems, that is, to said mask layer 102 ' return carve to handle after; The angle at raceway groove step place is generally about 270 °, and when the said oxide-isolation layer of deposition 103 ', the step place is because angle is bigger; Deposition velocity is local faster than other; Raceway groove is sealed in advance, cause raceway groove inside hole 30 (void) to occur and fill not exclusively and influence isolation effect, also can cause the back process polycrystalline silicon growth the time can in empty 30, the residual of polysilicon be arranged; Thereby influence the electric leakage of components and parts, serious meeting forms short circuit.
Summary of the invention
The technical problem that the present invention will solve is; Provide a kind of can reduce to avoid making the oxidation separator in the shallow trench isolation regions time; The inner problem that the cavity occurs of said oxidation separator, and can reduce to form the manufacture method of shallow trench isolation regions of the unfilled corner problem of shallow trench isolation regions top simultaneously.
For addressing the above problem, the present invention provides a kind of manufacture method of shallow trench isolation regions, may further comprise the steps:
Semiconductor substrate is provided;
On said Semiconductor substrate, form mask layer;
Forming the raceway groove step, define the type appearance of said mask layer, exposing the part that said Semiconductor substrate desire forms said shallow trench isolation regions, is hard mask with the type appearance of said mask layer, and the said Semiconductor substrate of etching is to form raceway groove;
Deposition oxidation separator on said Semiconductor substrate, said oxidation separator fills up said raceway groove;
Planarisation step is implemented planarization process to said oxidation separator, removes the said oxidation separator beyond the said raceway groove, exposes said mask layer;
Return and carve treatment step, said mask layer is implemented back to carve handle, between said oxidation separator and said mask layer, form the gap;
The oxide layer of on said mask layer, growing, said oxide layer is filled the gap between said oxidation separator and the said mask layer;
The said oxide layer of etching is until exposing said mask layer;
Etching is removed said mask layer and said oxide layer successively, finally forms shallow trench isolation regions.
Further, said mask layer is one of them or a combination in any of silica, silicon nitride, silicon oxynitride.
Further, said mask layer adopts thermal oxidation method or chemical vapour deposition technique deposition to form.
Further, in forming the raceway groove step, the type appearance that defines said mask layer is: on said mask layer, form photoresist, the said photoresist of patterning is a mask with said photoresist, and the said mask layer of etching is until exposing said Semiconductor substrate.
Preferable, the degree of depth of said raceway groove is
to
Further, said oxidation separator adopts the high density plasma enhanced chemical vapor deposition method to form.
Preferable, be silica at said oxidation separator.
Further, in said planarisation step, said planarization process adopts chemical mechanical milling method.
Further, carve in the treatment step, adopt phosphoric acid solution that said mask layer is returned to carve and handle at said time.
Preferable; The mass percent of phosphoric acid is 80%～90% in the said phosphoric acid solution, and the rate of etch of said phosphoric acid solution is 45～
Preferably, the gap width between said oxidation separator and the said mask layer is
Preferably, being filled in said oxidation separator equates with the width in said gap with said thickness of oxide layer between the said mask layer.
Further, remove in the said oxide layer step, adopt the said oxide layer of hydrofluoric acid solution etching in etching.
Further; The mass percent 45%～55% of hydrofluoric acid in the said hydrofluoric acid solution, the rate of etch of said hydrofluoric acid solution are 50～
In sum, the present invention is employed in and deposits the said oxidation separator of formation before said mask layer returns the processing at quarter, has avoided the problem of said oxidation separator deposition rate inequality, and then has avoided forming empty problem in said oxidation separator inside; Simultaneously; The gap of the present invention between said mask layer and said oxidation separator forms oxide layer; Said oxide layer can protect the top of said oxidation separator not to be corroded in the process of follow-up wet-cleaned, has effectively reduced the formation of the unfilled corner of shallow trench isolation regions top.
Description of drawings
Fig. 1 is the sketch map of the unfilled corner of shallow trench isolation regions top in the prior art.
Fig. 2 is for returning the structural representation of carving after the processing in the prior art to mask layer after forming raceway groove.
Fig. 3 is the sketch map of oxidation separator interior void in the prior art.
Fig. 4～Figure 11 is the structural representation of the manufacturing process of shallow trench isolation regions in one embodiment of the invention.
Figure 12 is the manufacturing process flow chart of shallow trench isolation regions in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable,, content of the present invention is described further below in conjunction with Figure of description.Is certainly the present invention not limited to this specific embodiment, the technology in this area? The general replacement that personnel knew also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes sketch map to carry out detailed statement, and when instance of the present invention was detailed, for the ease of explanation, sketch map did not amplify according to general ratio is local, should be with this as to qualification of the present invention.
Core concept of the present invention is: through after forming oxidation separator step; Mask layer is returned quarter to be handled; And protect the oxidation separator between said oxidation separator and said mask layer, forming oxide layer; Thereby not only avoided in oxidation separator interior void problem, and in follow-up wet-cleaned process, be not corroded, reduced the formation of the unfilled corner of shallow trench isolation regions top.
Figure 12 is the manufacturing process flow chart of shallow trench isolation regions in one embodiment of the invention; Fig. 4～Figure 11 is the structural representation of the manufacturing process of shallow trench isolation regions in one embodiment of the invention; Please refer to shown in Figure 12; And combine Fig. 4～Figure 11, the present invention proposes a kind of manufacture method of shallow trench isolation regions, may further comprise the steps:
S01: Semiconductor substrate 100 is provided.
S02: on said Semiconductor substrate 100, form mask layer 102, form structure as shown in Figure 4; Said mask layer 102 is silica, silicon nitride, silicon oxynitride one of them or combination in any; Said in the present embodiment mask layer 102 comprises silicon oxide layer 102a and silicon nitride layer 102b; Said silicon oxide layer 102a adopts thermal oxidation method to form or aumospheric pressure cvd method (Atmospheric) or Low Pressure Chemical Vapor Deposition (10w Pressure Chemical Vapor Deposition; LPCVD) deposition forms, and the thickness of said silicon oxide layer 102a does
Arrive
Said silicon nitride layer 102b adopts Low Pressure Chemical Vapor Deposition to form, with dichlorosilane (SiCl
2H
2) and ammonia (NH
3) for the reaction raw materials deposition forms, the thickness of said silicon nitride layer 102b does
Arrive
S03: in said Semiconductor substrate 100, form raceway groove; Form said raceway groove step; Define the type appearance of said mask layer 102; To expose the part that said Semiconductor substrate 100 desires form said shallow trench isolation regions; Type appearance with said mask layer 102 is hard mask; The said Semiconductor substrate 100 of etching is to form raceway groove (among the figure not label); The degree of depth of said raceway groove wherein defines the type appearance of said mask layer 102 to
for
; Be specially on said mask layer 102 and form photoresist; The said photoresist of patterning is a mask with the photoresist, and the said mask layer 102 of etching is until exposing said Semiconductor substrate 100; Further again, the said photoresist of patterning is specially photoresist is made public, and develops, and exposes the part that desire forms shallow trench isolation regions.
S04: in said raceway groove, form oxidation separator 103; Deposition oxidation separator 103 on said Semiconductor substrate 100; Said oxidation separator 103 fills up said raceway groove; Said oxidation separator 103 adopts the high density plasma enhanced chemical vapor deposition method to form; For example use O2 and SiH4 as reactant, impose Ar electricity slurry simultaneously and splash and deposit an oxide layer, fill up said raceway groove to form oxidation separator 103; Preferable, said oxidation separator is a silica.
S05: said oxidation separator 103 is implemented planarization; Planarisation step is implemented planarization to said oxidation separator 103, removes the said oxidation separator 103 beyond the said raceway groove, and said planarisation step adopts chemical mechanical milling method, exposes said mask layer 102, forms the structure like Fig. 5.
S06: said mask layer 102 is returned quarter handle; Return and carve treatment step; Between said oxidation separator 103 and said mask layer 102, form the gap, further, in the present embodiment; Specifically the silicon nitride layer 102b to said mask layer 102 returns the processing at quarter; Between said oxidation separator 103 and said silicon nitride layer 102b, form the gap, and expose said silicon oxide layer 102a, form structure as shown in Figure 6; Further; With phosphoric acid solution said mask layer 102 being returned quarter handles; The mass percent of phosphoric acid is 80%～90% in the wherein said phosphoric acid solution; The rate of etch of said phosphoric acid solution is 45～
preferable; The mass percent of phosphoric acid is 85% in the said phosphoric acid solution; The rate of etch of said phosphoric acid solution is crossed conference for the mass percent of phosphoric acid in
said phosphoric acid solution makes etching rate too fast; Wayward, and the too small meeting of the mass percent of phosphoric acid makes etching rate slower in the said phosphoric acid solution, reduces make efficiency.
S07: form oxide layer 104 and fill said gap; In the said oxide layer 104 of said mask layer 102 superficial growths, the gap that said oxide layer 104 is filled between said oxidation separator 103 and the said mask layer forms the structure like Fig. 7.
S08: the said oxide layer 104 of etching; The said oxide layer 104 of etching forms the structure like Fig. 8 until exposing said mask layer 102 surfaces;
S09: remove said mask layer 102 and said oxide layer 104; Remove said mask layer 102 and said oxide layer 104 successively, finally form shallow trench isolation regions, form structure shown in figure 11; Further, in the present embodiment, remove said silicon nitride layer 102b, said silicon oxide layer 102a and said oxide layer 104 successively; Further; Remove said silicon nitride layer 102b with phosphoric acid solution; Form structure as shown in Figure 9; Remove said silicon oxide layer 102a with hydrofluoric acid solution; Form structure shown in figure 10; Remove said oxide layer 104 with hydrofluoric acid solution; Form structure shown in figure 11; It is identical with the hydrofluoric acid solution concentration that oxide layer 104 adopts to remove said silicon oxide layer 102a; But said silicon oxide layer 102a is different with said oxide layer 104 thickness; So etch period is different; The mass percent of phosphoric acid is 80%～90% in the wherein said phosphoric acid solution, and the rate of etch of said phosphoric acid solution is the mass percent 45%～55% of hydrofluoric acid in 45～
the said hydrofluoric acid solutions, and the rate of etch of said hydrofluoric acid solution is 50～
preferred; The mass percent of phosphoric acid is 85% in the said phosphoric acid solution; The rate of etch of said phosphoric acid solution is the mass percent 49% of hydrofluoric acid in
said hydrofluoric acid solution, and the rate of etch of said hydrofluoric acid solution is crossed conference for the concentration of
said phosphoric acid solution or hydrofluoric acid solution makes etching rate too fast, wayward; The too small etching rate that then can make is slower, reduces make efficiency.
Preferable; Gap width between said oxidation separator 103 and the said mask layer 102 is that
is preferable, and the width that is filled in the said oxide layer 104 between said oxidation separator 103 and the said mask layer 102 equates with the width in said gap.Gap between said oxidation separator 103 of said oxide layer complete filling and the said mask layer 102, top that can the said oxidation separator 104 of better protection are by follow-up wet-cleaned process corrosion.
In sum; The present invention is employed in and deposits the said oxidation separator 103 of formation before said mask layer 102 returns the processing at quarter; Avoided the uneven problem of said oxidation separator 103 deposition rates, and then avoided in the said oxidation separator 103 inner problems that form the cavity; Simultaneously; The gap of the present invention between said mask layer 102 and said oxidation separator 103 forms oxide layer 104; Said oxide layer 104 can protect the top of said oxidation separator 103 not to be corroded in the process of follow-up wet-cleaned, and then has effectively reduced the formation of the unfilled corner of shallow trench isolation regions top.
In the present embodiment, phosphoric acid of using in oxide layer, mask layer thickness, channel depth and the wet etching and hydrofluoric acid concentration are preferable selection, are the preferable selection that those skilled in the art knew.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (14)
1. the manufacture method of a shallow trench isolation regions is characterized in that, may further comprise the steps:
Semi-conductive substrate is provided;
On said Semiconductor substrate, form mask layer;
Forming the raceway groove step, define the type appearance of said mask layer, exposing the part that said Semiconductor substrate desire forms said shallow trench isolation regions, is hard mask with the type appearance of said mask layer, and the said Semiconductor substrate of etching is to form raceway groove;
Deposition oxidation separator on said Semiconductor substrate, said oxidation separator fills up said raceway groove;
Planarisation step is implemented planarization process to said oxidation separator, removes the said oxidation separator beyond the said raceway groove, exposes said mask layer;
Return and carve treatment step, said mask layer is implemented back to carve handle, between said oxidation separator and said mask layer, form the gap;
The oxide layer of on said mask layer, growing, said oxide layer is filled the gap between said oxidation separator and the said mask layer;
The said oxide layer of etching is until exposing said mask layer;
Etching is removed said mask layer and said oxide layer successively, finally forms shallow trench isolation regions.
2. the manufacture method of shallow trench isolation regions as claimed in claim 1 is characterized in that, said mask layer is one of them or a combination in any of silica, silicon nitride, silicon oxynitride.
3. the manufacture method of shallow trench isolation regions as claimed in claim 2 is characterized in that, said mask layer adopts thermal oxidation method or chemical vapour deposition technique deposition to form.
4. the manufacture method of shallow trench isolation regions as claimed in claim 1; It is characterized in that; In forming the raceway groove step, the type appearance that defines said mask layer is: on said mask layer, form photoresist, the said photoresist of patterning; With said photoresist is mask, and the said mask layer of etching is until exposing said Semiconductor substrate.
5. the manufacture method of shallow trench isolation regions as claimed in claim 1; It is characterized in that, the degree of depth of said raceway groove is
to
6. the manufacture method of shallow trench isolation regions as claimed in claim 1 is characterized in that, said oxidation separator adopts the high density plasma enhanced chemical vapor deposition method to form.
7. the manufacture method of shallow trench isolation regions as claimed in claim 1 is characterized in that, is silica at said oxidation separator.
8. the manufacture method of shallow trench isolation regions as claimed in claim 1 is characterized in that, in said planarisation step, said planarization process adopts chemical mechanical milling method.
9. the manufacture method of shallow trench isolation regions as claimed in claim 1 is characterized in that, carves in the treatment step at said time, adopts phosphoric acid solution that said mask layer is returned to carve and handles.
10. the manufacture method of shallow trench isolation regions as claimed in claim 9; It is characterized in that; The mass percent of phosphoric acid is 80%～90% in the said phosphoric acid solution, and the rate of etch of said phosphoric acid solution is 45～
11. the manufacture method of shallow trench isolation regions as claimed in claim 1; It is characterized in that the gap width between said oxidation separator and the said mask layer is
12. the manufacture method of shallow trench isolation regions as claimed in claim 11 is characterized in that, is filled in said oxidation separator and equates with the width in said gap with said thickness of oxide layer between the said mask layer.
13. the manufacture method of shallow trench isolation regions as claimed in claim 1 is characterized in that, removes in the said oxide layer step in etching, adopts the said oxide layer of hydrofluoric acid solution etching.
14. the manufacture method of shallow trench isolation regions as claimed in claim 13; It is characterized in that; The mass percent 45%～55% of hydrofluoric acid in the said hydrofluoric acid solution, the rate of etch of said hydrofluoric acid solution are 50～
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078411A (en) * | 2014-07-25 | 2014-10-01 | 上海华力微电子有限公司 | Manufacturing method for shallow groove isolation structure |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN104078409B (en) * | 2014-07-25 | 2017-08-22 | 上海华力微电子有限公司 | The process of shallow trench isolation |
| CN110867444A (en) * | 2018-08-28 | 2020-03-06 | 华邦电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN112086352A (en) * | 2020-08-06 | 2020-12-15 | 北京烁科精微电子装备有限公司 | Process for growing oxidation isolation layer by using Locos and preparing IGBT chip |
| CN115938937A (en) * | 2023-03-09 | 2023-04-07 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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| US6232203B1 (en) * | 1999-07-23 | 2001-05-15 | Taiwan Semiconductor Manufacturing Company | Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches |
| JP2004356484A (en) * | 2003-05-30 | 2004-12-16 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| CN101154617A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing isolation structure of shallow plough groove |
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2010
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| US6232203B1 (en) * | 1999-07-23 | 2001-05-15 | Taiwan Semiconductor Manufacturing Company | Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches |
| JP2004356484A (en) * | 2003-05-30 | 2004-12-16 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN104078411A (en) * | 2014-07-25 | 2014-10-01 | 上海华力微电子有限公司 | Manufacturing method for shallow groove isolation structure |
| CN104078409B (en) * | 2014-07-25 | 2017-08-22 | 上海华力微电子有限公司 | The process of shallow trench isolation |
| CN110867444A (en) * | 2018-08-28 | 2020-03-06 | 华邦电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN110867444B (en) * | 2018-08-28 | 2022-03-04 | 华邦电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN112086352A (en) * | 2020-08-06 | 2020-12-15 | 北京烁科精微电子装备有限公司 | Process for growing oxidation isolation layer by using Locos and preparing IGBT chip |
| CN112086352B (en) * | 2020-08-06 | 2024-02-20 | 北京晶亦精微科技股份有限公司 | Technology for growing oxidation isolation layer and preparing IGBT chip by using Locos |
| CN115938937A (en) * | 2023-03-09 | 2023-04-07 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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