CN103187258A - Method for removing silicon nitride layer in floating gate manufacturing process - Google Patents
Method for removing silicon nitride layer in floating gate manufacturing process Download PDFInfo
- Publication number
- CN103187258A CN103187258A CN2011104562733A CN201110456273A CN103187258A CN 103187258 A CN103187258 A CN 103187258A CN 2011104562733 A CN2011104562733 A CN 2011104562733A CN 201110456273 A CN201110456273 A CN 201110456273A CN 103187258 A CN103187258 A CN 103187258A
- Authority
- CN
- China
- Prior art keywords
- silicon nitride
- nitride layer
- substrate
- floating boom
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a method for removing a silicon nitride layer in a floating gate manufacturing process. The method includes the steps that a substrate is provided and comprises a substrate body, a silicon oxide layer, the silicon nitride layer and a shallow trench isolating structure, wherein the silicon oxide layer and the silicon nitride layer are sequentially deposited on the substrate body, and the shallow trench isolating structure separates the silicon nitride layer into at least one independent portion; a part of the silicon nitride layer is removed; and the following step is carried out repeatedly until all the silicon nitride layer is removed: groove side walls formed after the part of the silicon nitride layer is removed are partially removed, and then another part of the silicon nitride layer is removed again. According to a groove structure formed through the method for removing the silicon nitride layer in the floating gate manufacturing process, a cross section of the groove structure is in the inverted trapezoidal shape, namely an opening of the groove structure is wider than the bottom of the groove structure, in the following floating gate manufacturing process, when polycrystalline silicon is deposited in the groove structure, the effect that the whole groove structure is completely filled with the polycrystalline silicon can be guaranteed, the defect that a gap is left in the groove structure does not exist, the quality of a manufactured floating gate and the quality of a manufactured storage unit are guaranteed, and reliability of the storage unit is guaranteed.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly the removal method of silicon nitride layer in a kind of floating boom manufacture process.
Background technology
Autoregistration floating boom (self align floating gate) is widely used in the manufacture process of flash memory (flash memory) as the memory cell of NOR flash memory.
Comprise following process among the preparation method of a kind of floating boom of prior art:
As shown in Figure 1, wafer substrate 1 as silicon substrate on silicon oxide layer deposited 2 and silicon nitride layer 3 successively, form shallow trench 4 by photoetching at substrate 1, this shallow trench 4 runs through silicon nitride layer 3 and silicon oxide layer 2, as shown in Figure 2.Continue cvd silicon oxide, form shallow trench isolation from (STI) 5, as shown in Figure 3.Shallow trench isolation is carried out cmp (CMP) until exposing silicon nitride layer 3 on the surface from 5, and this moment, silicon nitride layer 3 was divided into some absolute construction separated from one another by shallow trench isolation from 5, as shown in Figure 4.As shown in Figure 5, remove silicon nitride layer 3, form several grooves 6.Deposit spathic silicon also carries out cmp and forms as shown in Figure 6 polysilicon separated from one another 7.Form after the polysilicon, proceed to prepare each existing technical process subsequently of floating boom, to form floating gate structure.
In the manufacture process of above-mentioned prior art, please refer to Fig. 4 to Fig. 6, silicon nitride layer 3 removes by the method for dry method or wet etching is disposable, and after removing described silicon nitride layer 3 formation grooves 6, the A/F of groove 6 is less than the bottom land width, when deposit spathic silicon 7 in groove 6, polysilicon 7 also is not easy to fill up fully whole groove 6, and easily occurs the space in groove 6, produces defective 8 (as shown in Figure 6), influence the preparation of floating boom, and then make the memory cell performance descend even inefficacy.
Summary of the invention
In view of this, the invention provides the removal method of silicon nitride layer in a kind of floating boom manufacture process, when guaranteeing after removing described silicon nitride layer, to carry out follow-up floating boom manufacture process craft, the polysilicon that is deposited in the groove of removing silicon nitride layer formation can fill up whole groove fully, avoids generation of defects.
Technical scheme of the present invention is achieved in that
The removal method of silicon nitride layer in a kind of floating boom manufacture process comprises:
Substrate is provided, and described substrate comprises silicon oxide layer and the silicon nitride layer that deposits successively on substrate and the substrate, and fleet plough groove isolation structure, and described fleet plough groove isolation structure is separated at least one separate part with described silicon nitride layer;
Remove the part silicon nitride layer;
Carry out following step repeatedly, all be removed up to silicon nitride layer:
Carry out the part removal to removing the recess sidewall that forms behind the part silicon nitride layer, and remove the part silicon nitride layer again.
Further, described silicon nitride layer all is removed the formed slot opening width in back greater than the bottom portion of groove width.
Further, described groove cross section is trapezoidal.
Further, remove the part silicon nitride layer and adopt wet etch process, etching liquid is 160 ℃ of hot phosphoric acid, to the rate of etch of silicon nitride is
Etching period is 5min.
Further, recess sidewall is carried out part remove the employing wet etch process, etching liquid adopts HF: H
2O is 1: 200 hydrofluoric acid solution, to the rate of etch of silica is
Etching period is 5～10min.
From such scheme as can be seen, the new method that the removal method of silicon nitride layer proposes in the floating boom manufacture process of the present invention, replace the existing disposable step that removes silicon nitride layer in the Floating-gate Technology of making, the mode that it adopts multistep to carry out the removal process of silicon nitride layer, all remove the silicon nitride layer of part in each step, and in each step, after removing the part silicon nitride layer, the sidewall of the groove that forms is also carried out part to be removed, therefore in the process of carrying out each step, width between the sidewall of groove is just widened, increase along with step, every silicon nitride layer of removing a part is all widened recess sidewall accordingly, formed like this groove structure, the width of its opening just is wider than the width of bottom portion of groove, treats after whole silicon nitride layers removals, and whole groove has just formed cross section and has been opening greater than the trapezoidal shape that falls of bottom width.The groove structure of this shape is in floating boom manufacturing process subsequently, when to deposit spathic silicon wherein, can guarantee that polysilicon fills up whole groove fully, in groove, do not stay void defects, guarantee prepared floating boom and the quality of memory cell, ensured the reliability of memory cell.
Description of drawings
Fig. 1 to Fig. 4 for prior art and the embodiment of the invention prepare in the floating boom method from provide substrate to shallow trench isolation from carrying out device architecture evolution schematic diagram the chemical mechanical planarization process;
Fig. 5 and Fig. 6 are the device architecture evolution schematic diagram of removing silicon nitride layer and deposit spathic silicon process in the prior art for preparing floating boom method;
Fig. 7 is the flow chart of the removal method of silicon nitride layer in the floating boom manufacture process of the present invention;
Fig. 8 to Figure 12 removes device architecture evolution schematic diagram in the silicon nitride layer process for adopting the inventive method.
In the accompanying drawing, the corresponding title of each label is as follows:
1, substrate, 2, silicon oxide layer, 3, silicon nitride layer, 4, shallow trench, 5, shallow trench isolation from, 6, groove, 7, polysilicon, 8, defective
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The removal method of silicon nitride layer in the floating boom manufacture process of the present invention as shown in Figure 7, comprising:
Substrate is provided, and described substrate comprises silicon oxide layer and the silicon nitride layer that deposits successively on substrate and the substrate, and fleet plough groove isolation structure, and described fleet plough groove isolation structure is separated at least one separate part with described silicon nitride layer;
Remove the part silicon nitride layer;
Carry out following step repeatedly, all be removed up to silicon nitride layer:
Carry out the part removal to removing the recess sidewall that forms behind the part silicon nitride layer, and remove the part silicon nitride layer again.
Now in conjunction with the floating boom manufacture process, method of the present invention is further set forth.
Referring to figs. 1 through Fig. 4, wafer substrate 1 as silicon substrate on silicon oxide layer deposited 2 and silicon nitride layer 3 successively.Wherein, substrate 1 can comprise any can be as the basic material that makes up semiconductor device thereon, such as silicon substrate.
Form shallow trench 4 by photoetching at substrate 1, this shallow trench 4 runs through silicon nitride layer 3 and silicon oxide layer 2.For example form the method for shallow trench 4: apply photoresist at crystal column surface, photoresist is exposed and develops, with predefined graph transfer printing to photoresist, be that mask carries out etching with remaining photoresist then, the part that is not covered by photoresist on the wafer is etched away silicon nitride layer 3, silicon oxide layer 2 and part substrate 1 successively, forms shallow trench 4.The bottom of this shallow trench 4 is arranged in substrate 1.
In the substrate after forming shallow trench 4, continue cvd silicon oxide, this is silica-filled to advance in the shallow trench 4 to form shallow trench isolation from (STI) 5, and covering is by above-mentioned photoetching process silicon nitride layer 3 separated from one another.Afterwards, device surface is carried out cmp (CMP), be covered in silica on the described silicon nitride layer 3 with removal, up to silicon nitride layer 3 exposing surfaces.
Said process is prior art, adopts existing conventional method can realize that specific embodiment repeats no more herein.
With reference to Fig. 8 to Figure 12, a specific embodiment removing described silicon nitride layer 3 is as follows.
As shown in Figure 8, remove part silicon nitride layer 3, make shallow trench isolation that the height of described silicon nitride layer 3 is lower than silica from 5, form groove 6.Remove part silicon nitride layer 3 and adopt wet etch process, etching liquid is 160 ℃ of hot phosphoric acid, to the rate of etch of silicon nitride is
Etching period is 5min.
As shown in Figure 9, remove part silicon nitride layer 3 after, the silica material of the sidewall of formation groove 6 parts (be shallow trench isolation from 5 sidewall) is carried out the part removal.Remove partial oxidation sidewall silicon material and adopt wet etch process, etching liquid adopts HF: H
2O (weight ratio) is 1: 200 hydrofluoric acid solution, to the rate of etch of silica is
Etching period is 5～10min.
As shown in figure 10, remove part silicon nitride layer 3 again.This process is identical with the technical process of aforementioned removal part silicon nitride layer 3, repeats no more.
As shown in figure 11, again the silica material of the sidewall of formation groove 6 parts (be shallow trench isolation from 5 sidewall) being carried out part removes.This process is identical with the technical process of aforementioned removal partial sidewall material, repeats no more.
Carry out the process of above-mentioned removal part silicon nitride layer 3 and partial sidewall repeatedly.
As shown in figure 12, remove last residual silicon nitride layer 3.This process is identical with the technical process of aforementioned removal part silicon nitride layer 3, repeats no more.
Through above-mentioned removal part silicon nitride layer 3 and to after removing groove 6 sidewalls that silicon nitride layer 3 backs form and carrying out repetitive process that part removes, formed groove 6 is a kind of trapezoidal shape (A/F of groove 6 is greater than the bottom land width) that falls.In should the assurance of falling trapezoidal shape floating boom manufacturing process subsequently, polysilicon can deposit in this groove 6 fully, avoids occurring defective as shown in Figure 6, has improved the floating boom that supports and the stability of device, thereby has ensured the reliability of memory cell.The final step of said process is for removing silicon nitride layer 3 (as shown in figure 12), remove silicon nitride layer 3 and no longer remove the silica material of partial sidewall afterwards, though remove close the bottom portion of groove A/F partly that can form after the described silicon nitride layer 3 as shown in figure 12 slightly less than groove bottom land width, can't have influence on subsequently polysilicon deposition and floating boom manufacture process afterwards.
Polysilicon deposition subsequently and floating boom manufacture process afterwards all can adopt existing known floating boom manufacturing step to carry out, and repeat no more herein.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (5)
1. the removal method of silicon nitride layer in the floating boom manufacture process comprises:
Substrate is provided, and described substrate comprises silicon oxide layer and the silicon nitride layer that deposits successively on substrate and the substrate, and fleet plough groove isolation structure, and described fleet plough groove isolation structure is separated at least one separate part with described silicon nitride layer;
Remove the part silicon nitride layer;
Carry out following step repeatedly, all be removed up to silicon nitride layer:
Carry out the part removal to removing the recess sidewall that forms behind the part silicon nitride layer, and remove the part silicon nitride layer again.
2. the removal method of silicon nitride layer in the floating boom manufacture process according to claim 1 is characterized in that: described silicon nitride layer all is removed the formed slot opening width in back greater than the bottom portion of groove width.
3. the removal method of silicon nitride layer in the floating boom manufacture process according to claim 2, it is characterized in that: described groove cross section is trapezoidal.
4. according to the removal method of silicon nitride layer in each described floating boom manufacture process of claim 1 to 3, it is characterized in that: remove the part silicon nitride layer and adopt wet etch process, etching liquid is 160 ℃ of hot phosphoric acid, to the rate of etch of silicon nitride is
Etching period is 5min.
5. according to the removal method of silicon nitride layer in each described floating boom manufacture process of claim 1 to 3, it is characterized in that: recess sidewall is carried out part remove the employing wet etch process, etching liquid adopts HF: H
2O is 1: 200 hydrofluoric acid solution, to the rate of etch of silica is
Etching period is 5～10min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110456273.3A CN103187258B (en) | 2011-12-30 | 2011-12-30 | The minimizing technology of silicon nitride layer in floating boom manufacture process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110456273.3A CN103187258B (en) | 2011-12-30 | 2011-12-30 | The minimizing technology of silicon nitride layer in floating boom manufacture process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103187258A true CN103187258A (en) | 2013-07-03 |
| CN103187258B CN103187258B (en) | 2016-08-31 |
Family
ID=48678368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110456273.3A Active CN103187258B (en) | 2011-12-30 | 2011-12-30 | The minimizing technology of silicon nitride layer in floating boom manufacture process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187258B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943549A (en) * | 2014-04-28 | 2014-07-23 | 上海华力微电子有限公司 | Removing method of shallow groove oxide hole and floating gate polycrystalline silicon concave point |
| CN103943478A (en) * | 2014-04-03 | 2014-07-23 | 武汉新芯集成电路制造有限公司 | Method for manufacturing floating gate structure |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN105336696A (en) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | Method for improving STI and FG poly filling hole process window simultaneously |
| CN105470201A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Flash memory device process for simultaneously improving shallow trench isolation (STI) filling holes and floating gate polycrystalline silicon (FG Poly) filling holes |
| CN106298678A (en) * | 2016-08-22 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method for improving of the control gate coefficient of coup |
| CN106469730A (en) * | 2015-08-18 | 2017-03-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor structure |
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| CN110610856A (en) * | 2019-09-20 | 2019-12-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113223996A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | ETOX structure flash memory floating gate filling method and flash memory thereof |
| CN113808930A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060030137A1 (en) * | 2004-08-04 | 2006-02-09 | Kim Jong-Won | Methods for reducing void formation in semiconductor devices and related devices |
| JP2006045656A (en) * | 2004-08-09 | 2006-02-16 | Fuji Xerox Co Ltd | Method for producing silicon structural body, method for producing metallic mold for molding, method for producing formed member, silicon structural body, inkjet recording head, and image forming apparatus |
| KR20070118348A (en) * | 2006-06-12 | 2007-12-17 | 삼성전자주식회사 | Method of manufacturing a non-volatile memory device |
-
2011
- 2011-12-30 CN CN201110456273.3A patent/CN103187258B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060030137A1 (en) * | 2004-08-04 | 2006-02-09 | Kim Jong-Won | Methods for reducing void formation in semiconductor devices and related devices |
| JP2006045656A (en) * | 2004-08-09 | 2006-02-16 | Fuji Xerox Co Ltd | Method for producing silicon structural body, method for producing metallic mold for molding, method for producing formed member, silicon structural body, inkjet recording head, and image forming apparatus |
| KR20070118348A (en) * | 2006-06-12 | 2007-12-17 | 삼성전자주식회사 | Method of manufacturing a non-volatile memory device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943478A (en) * | 2014-04-03 | 2014-07-23 | 武汉新芯集成电路制造有限公司 | Method for manufacturing floating gate structure |
| CN103943549A (en) * | 2014-04-28 | 2014-07-23 | 上海华力微电子有限公司 | Removing method of shallow groove oxide hole and floating gate polycrystalline silicon concave point |
| CN103943549B (en) * | 2014-04-28 | 2016-08-17 | 上海华力微电子有限公司 | A kind of shallow trench oxide cavity and the removing method of floating gate polysilicon concave point |
| CN105336696A (en) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | Method for improving STI and FG poly filling hole process window simultaneously |
| CN105470201A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Flash memory device process for simultaneously improving shallow trench isolation (STI) filling holes and floating gate polycrystalline silicon (FG Poly) filling holes |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN106469730B (en) * | 2015-08-18 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor structure |
| CN106469730A (en) * | 2015-08-18 | 2017-03-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor structure |
| CN106298678A (en) * | 2016-08-22 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method for improving of the control gate coefficient of coup |
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| US10784117B2 (en) | 2018-05-23 | 2020-09-22 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Defect relieving method for floating gate, and semiconductor structure |
| CN110610856A (en) * | 2019-09-20 | 2019-12-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113223996A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | ETOX structure flash memory floating gate filling method and flash memory thereof |
| CN113808930A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103187258B (en) | 2016-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103187258A (en) | Method for removing silicon nitride layer in floating gate manufacturing process | |
| CN101779284B (en) | Method to fabricate adjacent silicon fins of differing heights | |
| CN102150253B (en) | The formation method of autoregistration groove | |
| CN103594336B (en) | A kind of Double-patterning method | |
| JP4455618B2 (en) | Manufacturing method of semiconductor device | |
| CN104752361B (en) | The forming method of semiconductor structure | |
| CN105336695A (en) | Formation method of semiconductor device | |
| CN102005375B (en) | Method for constructing floating gate | |
| JP2009200464A (en) | Flash memory device and method of manufacturing the same | |
| CN101944538B (en) | Semiconductor structures and manufacturing method thereof | |
| CN104217986A (en) | Shallow trench isolation structure manufacturing method and NAND flash memory manufacturing method | |
| US9472413B2 (en) | Method for producing a pattern in an integrated circuit and corresponding integrated circuit | |
| KR100875079B1 (en) | Method of manufacturing a flash memory device | |
| US6921705B2 (en) | Method for forming isolation layer of semiconductor device | |
| CN104752358B (en) | Flush memory device and forming method thereof | |
| US7781279B2 (en) | Method for manufacturing a memory | |
| JP2007305958A (en) | Method of manufacturing semiconductor element | |
| KR100898674B1 (en) | Method for fabricating semiconductor device | |
| TWI508232B (en) | Non-volatile memory cell and method of the same | |
| US20120112262A1 (en) | Method for producing a floating gate memory structure | |
| JP2008042171A (en) | Flash memory device and method of manufacturing the same | |
| US20050042812A1 (en) | Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure | |
| TW200903732A (en) | Method for manufacturing flash memory | |
| JP2008118100A (en) | Method of fabricating flash memory device | |
| KR20100008966A (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |