CN113223996A - ETOX structure flash memory floating gate filling method and flash memory thereof - Google Patents
ETOX structure flash memory floating gate filling method and flash memory thereof Download PDFInfo
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- CN113223996A CN113223996A CN202110467586.2A CN202110467586A CN113223996A CN 113223996 A CN113223996 A CN 113223996A CN 202110467586 A CN202110467586 A CN 202110467586A CN 113223996 A CN113223996 A CN 113223996A
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- etching
- floating gate
- semiconductor substrate
- isolation material
- hard mask
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- 238000000034 method Methods 0.000 title claims abstract description 36
- SJHPCNCNNSSLPL-CSKARUKUSA-N (4e)-4-(ethoxymethylidene)-2-phenyl-1,3-oxazol-5-one Chemical group O1C(=O)C(=C/OCC)\N=C1C1=CC=CC=C1 SJHPCNCNNSSLPL-CSKARUKUSA-N 0.000 title claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 49
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention discloses a method for filling an ETOX structure flash memory floating gate, which comprises the following steps: step S1, depositing a hard mask layer on a semiconductor substrate, providing the semiconductor substrate, and depositing the patterned hard mask layer on the semiconductor substrate; step S2, etching to form shallow trenches, and etching part of the semiconductor substrate by using the patterned hard mask layer as a mask to form a plurality of shallow trenches, wherein the bottoms of the shallow trenches are positioned in the semiconductor substrate; step S3, filling and forming an isolation material layer, and filling an isolation material in the shallow trench to form the isolation material layer, wherein the isolation material is silicon dioxide; step S4, planarizing the isolation material layer to form a shallow trench isolation structure, wherein the planarization method is a chemical mechanical polishing method; step S5, etching back the hard mask layer, wherein the etching back comprises a three-time etching back process; step S6, filling the floating gate.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for filling a floating gate of an ETOX flash memory and a flash memory thereof.
Background
In the manufacturing process of a power device semiconductor, an STI process is used in an ETOX structure flash memory.
Flash memory, which is the mainstream of non-volatile semiconductor memory technology, is currently the flash memory of etox (eprom Tunnel oxide) structure, i.e. a Floating Gate (Floating Gate) surrounded by six dielectric faces is used to store electrons. When electrons are injected into the floating gate, because the periphery of the floating gate is provided with the dielectric medium, potential wells are generated based on different work functions of the polysilicon and the silicon oxide, the electrons are kept in the polysilicon due to the existence of the potential wells, and the probability of escaping the electrons is greatly reduced through the existence of the potential wells, so that the durability of stored information is ensured.
Shallow Trench Isolation (STI) is a Shallow Trench Isolation. Typically used in sub-0.25 um processes, the trench is formed by depositing, patterning, and etching silicon using a silicon nitride mask, and the trench is filled with a deposited oxide to isolate the floating gate.
STI structures are typically formed by first depositing a silicon nitride layer over a semiconductor substrate and then patterning the silicon nitride layer to form a hard mask. The substrate is then etched to form steep trenches between adjacent devices. Finally, filling oxide into the trench to form an element isolation structure.
STI structures often exhibit an inverted trapezoidal morphology that is not conducive to floating gate fill, which can lead to void carry-over and reliability issues.
Disclosure of Invention
The invention aims to solve the technical problem that before filling a floating gate of an ETOX structure flash memory, an inverted trapezoid of an STI structure is corrected, and gaps are prevented from being left when filling the floating gate.
The invention provides a method for filling an ETOX structure flash memory floating gate, which comprises the following steps:
step S1, depositing a hard mask layer on the semiconductor substrate,
providing the semiconductor substrate, and depositing and forming the patterned hard mask layer on the semiconductor substrate;
step S2, etching to form a shallow trench,
etching part of the semiconductor substrate by taking the patterned hard mask layer as a mask to form a plurality of shallow trenches, wherein the bottoms of the shallow trenches are positioned in the semiconductor substrate;
step S3, filling to form isolation material layer,
filling an isolation material in the shallow trench to form the isolation material layer, wherein the isolation material is silicon dioxide;
step S4, planarizing the isolation material layer to form a shallow trench isolation structure,
the planarization method is a chemical mechanical polishing method;
step S5, etching back the hard mask layer,
the back etching comprises a three-time back etching process, namely a first back etching, a second back etching and a third back etching, wherein etching solutions for the first back etching, the second back etching and the third back etching comprise hydrofluoric acid solution and phosphoric acid solution;
step S6, filling the floating gate.
Preferably, in step S1, the semiconductor substrate is made of monocrystalline silicon, and the hard mask layer includes a silicon nitride layer.
Preferably, the hard mask layer is formed using any one of chemical vapor deposition, physical vapor deposition, or atomic layer vapor deposition.
Preferably, in step S3, the isolation material layer is formed in the shallow trench by using high density plasma chemical vapor deposition.
Preferably, in the step S4, before the chemical mechanical polishing method is performed, a deburring step is further included, and the deburring step is performed by introducing etching gas to remove burrs on the surface of the isolation material layer.
Preferably, in the step S6, the floating gate material is polysilicon or doped polysilicon.
The invention also provides an ETOX structure flash memory which is prepared by adopting the floating gate filling method of the ETOX structure flash memory.
Compared with the prior art, the method can correct the inverted trapezoid of the shallow trench isolation structure, avoid the leaving of gaps during the filling of the floating gate, and ensure the process reliability of the device.
Drawings
Fig. 1 is a schematic diagram of a prior art STI structure that generally exhibits an inverted trapezoidal shape.
FIG. 2 is a schematic diagram of the steps of the ETOX flash floating gate filling method.
Fig. 3 is a schematic diagram of the device structure after step S4.
Fig. 4 is a schematic diagram of the device structure after the first etching back in step S5.
Fig. 5 is a schematic diagram of the device structure after the second etching back in step S5.
Fig. 6 is a schematic diagram of the device structure after the third etching back in step S5.
FIG. 7 is a photomicrograph of an STI having an inverted trapezoid shape after a prior art single etch back.
Fig. 8 is a photomicrograph of the STI straightened after the three times of etching-back in step S5.
Detailed Description
The method for filling the floating gate of the ETOX structure flash memory of the embodiment comprises the following steps as shown in FIG. 2:
in step S1, a hard mask layer is deposited on the semiconductor substrate.
Providing a semiconductor substrate 1, and forming a patterned hard mask layer 2 on the semiconductor substrate 1;
the material of the semiconductor substrate 1 is, for example, single crystal silicon. The hard mask layer 2 includes a silicon nitride layer, such as a silicon oxynitride (PDSN) pad, and may be formed using chemical vapor deposition, physical vapor deposition, atomic layer vapor deposition, and the like.
Step S2, forming a shallow trench by etching.
For example, a portion of the semiconductor substrate 1 is etched using the patterned hard mask layer 2 as a mask to form a plurality of shallow trenches, the bottoms of which are located in the semiconductor substrate 1.
And step S3, filling and forming an isolation material layer.
The shallow trenches are filled with an isolation material to form an isolation material layer, for example, the isolation material may be silicon dioxide, and HDP-CVD (high density plasma chemical vapor deposition) is used to form the silicon dioxide layer in the shallow trenches and on the semiconductor substrate.
In step S4, the isolation material layer is planarized to form a shallow trench isolation structure.
As shown in fig. 3, the isolation material layer is planarized to form a shallow trench isolation structure 3. The planarization method may be a Chemical Mechanical Polishing (CMP) method.
The chemical mechanical polishing method can also be used for deburring before the chemical mechanical polishing method, and the etching gas is introduced to remove burrs on the surface of the silicon dioxide, so that the surface of the wafer is prevented from being scratched by the burrs during polishing.
In step S5, the hard mask layer is etched back.
The hard mask layer is etched back for multiple times. The back etching adopts wet etching, and the etching solution contains hydrofluoric acid solution and phosphoric acid solution. The combination of hydrofluoric acid solution and phosphoric acid solution can remove the hard mask layer and the isolation material on the side wall of the shallow trench isolation structure simultaneously, and the side wall with the thickness of about 20-30 angstroms can be removed each time.
The etching solution for the first etching, the second etching and the third etching comprises hydrofluoric acid solution and phosphoric acid solution. Fig. 4 is a schematic view of the structure of the device after the first etching. Fig. 5 is a schematic structural diagram of the device after the second etching in step S5. Fig. 6 is a schematic view of the device structure after the third etching in step S5.
Each etch removes a portion of the isolation material that removed the sidewalls of the shallow trench isolation structure. Therefore, the inverted trapezoid of the shallow trench isolation structure can be corrected through three times of back etching.
The technical effects can be seen in fig. 7 and 8, fig. 7 is the shape after only one etching back, which is an inverted trapezoid, fig. 8 is the shape after three etching back in the present embodiment, the STI shape is straighter, and the improvement is obvious.
Step S6, filling the floating gate.
The floating gate material, which may be polysilicon or doped polysilicon, is filled.
In addition, the invention also provides an ETOX structure flash memory, and the flash memory is prepared by any one of the above ETOX structure flash memory floating gate filling methods.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (7)
1. A method for filling an ETOX structure flash memory floating gate is characterized by comprising the following steps:
step S1, depositing a hard mask layer on the semiconductor substrate,
providing the semiconductor substrate, and depositing and forming the patterned hard mask layer on the semiconductor substrate;
step S2, etching to form a shallow trench,
etching part of the semiconductor substrate by taking the patterned hard mask layer as a mask to form a plurality of shallow trenches, wherein the bottoms of the shallow trenches are positioned in the semiconductor substrate;
step S3, filling to form isolation material layer,
filling an isolation material in the shallow trench to form the isolation material layer, wherein the isolation material is silicon dioxide;
step S4, planarizing the isolation material layer to form a shallow trench isolation structure,
the planarization method is a chemical mechanical polishing method;
step S5, etching back the hard mask layer,
the back etching comprises a three-time back etching process, a first back etching, a second back etching and a third back etching,
the etching solution for the first back etching, the second back etching and the third back etching contains hydrofluoric acid solution and phosphoric acid solution;
step S6, filling the floating gate.
2. The method of ETOX structure flash floating gate fill of claim 1, wherein:
in step S1, the semiconductor substrate is made of monocrystalline silicon, and the hard mask layer includes a silicon nitride layer.
3. The ETOX structure flash floating gate fill method of claim 2, wherein:
the hard mask layer is formed using any one of chemical vapor deposition, physical vapor deposition, or atomic layer vapor deposition.
4. The method of ETOX structure flash floating gate fill of claim 1, wherein:
in step S3, a high-density plasma chemical vapor deposition is used to form the isolation material layer in the shallow trench.
5. The method of ETOX structure flash floating gate fill of claim 1, wherein:
the step S4 further includes a deburring step before the chemical mechanical polishing method,
and the deburring step is to introduce etching gas to remove burrs on the surface of the isolation material layer.
6. The method of ETOX structure flash floating gate fill of claim 1, wherein:
in step S6, the floating gate material is polysilicon or doped polysilicon.
7. An ETOX structure flash memory, comprising:
the ETOX structure flash memory is prepared by the method of any one of the preceding claims.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110467586.2A CN113223996A (en) | 2021-04-28 | 2021-04-28 | ETOX structure flash memory floating gate filling method and flash memory thereof |
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| CN202110467586.2A CN113223996A (en) | 2021-04-28 | 2021-04-28 | ETOX structure flash memory floating gate filling method and flash memory thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881534A (en) * | 2005-06-13 | 2006-12-20 | 海力士半导体有限公司 | Method of manufacturing a floating gate of a flash memory device |
| CN103187258A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for removing silicon nitride layer in floating gate manufacturing process |
| CN106601744A (en) * | 2015-10-13 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Embedded flash memory, manufacturing method thereof and electronic device |
| CN112670235A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | STI planarization method |
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2021
- 2021-04-28 CN CN202110467586.2A patent/CN113223996A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881534A (en) * | 2005-06-13 | 2006-12-20 | 海力士半导体有限公司 | Method of manufacturing a floating gate of a flash memory device |
| CN103187258A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Method for removing silicon nitride layer in floating gate manufacturing process |
| CN106601744A (en) * | 2015-10-13 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Embedded flash memory, manufacturing method thereof and electronic device |
| CN112670235A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | STI planarization method |
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Application publication date: 20210806 |