CN116847655A - Method for manufacturing flash memory device - Google Patents
Method for manufacturing flash memory device Download PDFInfo
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- CN116847655A CN116847655A CN202310789490.7A CN202310789490A CN116847655A CN 116847655 A CN116847655 A CN 116847655A CN 202310789490 A CN202310789490 A CN 202310789490A CN 116847655 A CN116847655 A CN 116847655A
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- layer
- floating gate
- substrate
- flash memory
- isolation
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 239
- 238000002955 isolation Methods 0.000 claims abstract description 99
- 238000007667 floating Methods 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 239000011241 protective layer Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000007517 polishing process Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 abstract description 9
- 230000002829 reductive effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention provides a manufacturing method of a flash memory device, which comprises the steps of forming an isolation layer in an isolation groove in a substrate, wherein the surface of the isolation layer is higher than the substrate, and part of the side wall of the isolation layer is exposed; forming a floating gate layer to cover the surface of the substrate and the surface and part of the side wall of the isolation layer, wherein the thickness of the floating gate layer is smaller than the height difference between the surface of the substrate and the surface of the isolation layer; forming a protective layer on the floating gate layer; flattening to make the height difference between the surface of the isolation layer and the surface of the floating gate layer on the substrate smaller than a certain thickness so as to expose the floating gate layer on the side wall of the isolation layer; and removing the protective layer to expose the floating gate layer. The invention controls the thickness of the floating gate layer in forming, and protects the floating gate layer in the planarization process by forming the protective layer, thereby avoiding the thickness uniformity of the floating gate layer from being reduced, and improving the shape stability and the storage performance of the flash memory device.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a method for manufacturing a flash memory device.
Background
With the development of technology, data storage media applications are directed to flash memory from traditional nonvolatile memory, and mass solid state storage devices using flash memory as a main storage medium have become one of the mainstream schemes of data storage today. Nord Flash (Nord Flash) has taken an increasingly important place in the non-volatile memory field due to its low cost, low power consumption, fast access speed, and other performance advantages.
FIG. 4 is a schematic diagram of a Nord flash memory. Referring to fig. 4, the conventional Nord flash memory includes a substrate 100, a gate dielectric layer 110 and a floating gate layer 120 are sequentially disposed on the substrate 100, a shallow trench isolation structure 101 is disposed in the floating gate layer 120, and the shallow trench isolation structure 101 extends into the substrate 100. The thickness of the floating gate layer 120 is a key parameter that determines the Memory (Memory) performance of the Nord flash Memory. The conventional process typically adjusts the floating gate layer of the Nord flash to a target thickness by a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP). However, the floating gate layer prepared by the chemical mechanical mask process suffers from the problem of poor thickness uniformity.
In view of this, there is a need for a method of controlling the thickness uniformity of the floating gate layer while reducing the thickness of the floating gate layer to improve the memory performance of the flash memory device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory device, which is used for controlling the thickness uniformity of a floating gate layer while reducing the thickness of the floating gate layer so as to improve the storage performance of the flash memory device.
In order to achieve the above object, the present invention provides a method for manufacturing a flash memory device, comprising:
providing a substrate, wherein a hard mask layer is formed on the substrate, an isolation trench is formed in the hard mask layer, and the isolation trench extends into the substrate;
filling an isolation layer in the isolation trench, and removing the hard mask layer to expose part of the side wall of the isolation layer;
forming a floating gate layer, wherein the floating gate layer covers the surface of the substrate, the surface of the isolation layer and part of the side wall, and the thickness of the floating gate layer is smaller than the height difference between the surface of the substrate and the surface of the isolation layer;
forming a protective layer on the floating gate layer;
carrying out planarization treatment to ensure that the height difference between the surface of the isolation layer and the surface of the floating gate layer on the substrate is smaller than a certain thickness so as to expose the floating gate layer on the side wall of the isolation layer; the method comprises the steps of,
and removing the protective layer to expose the floating gate layer.
Optionally, after the planarization treatment, the residual thickness of the protective layer is 5% -15% of the total thickness of the protective layer.
Optionally, the planarization process is performed using a chemical mechanical polishing process.
Optionally, a wet etching process is used to remove the protective layer.
Optionally, the material of the isolation layer is the same as the material of the protection layer.
Optionally, removing part of the isolation layer while removing the protection layer, so that the surface of the isolation layer is flush with the surface of the floating gate layer on the substrate.
Optionally, the protective layer is a high temperature oxide layer.
Optionally, the forming process of the isolation trench includes:
forming a patterned photoresist layer on the hard mask layer;
and etching the hard mask layer and the substrate by taking the patterned photoresist layer as a mask so as to form the isolation trench in the hard mask layer and the substrate.
Optionally, a gate dielectric layer is further formed between the substrate and the floating gate layer.
Optionally, the method for manufacturing a flash memory device is used for manufacturing a Nord flash memory.
In summary, the present invention provides a method for manufacturing a flash memory device, in which an isolation layer is formed in an isolation trench in a substrate, the surface of the isolation layer is higher than the substrate, and a portion of a sidewall of the isolation layer is exposed; forming a floating gate layer to cover the surface of the substrate and the surface and part of the side wall of the isolation layer, wherein the thickness of the floating gate layer is smaller than the height difference between the surface of the substrate and the surface of the isolation layer; forming a protective layer on the floating gate layer; carrying out planarization treatment to ensure that the height difference between the surface of the isolation layer and the surface of the floating gate layer on the substrate is smaller than a certain thickness so as to expose the floating gate layer on the side wall of the isolation layer; and removing the protective layer to expose the floating gate layer. The thickness of the floating gate layer in the finally formed flash memory device is reduced by controlling the thickness of the floating gate layer in the forming process, and meanwhile, the floating gate layer is protected in the planarization process by forming the protective layer, so that the thickness uniformity of the floating gate layer is prevented from being reduced, and the shape stability and the storage performance of the flash memory device are improved.
Drawings
FIGS. 1-4 are schematic diagrams illustrating partial steps of a method for fabricating a Nord flash memory;
FIG. 5 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention;
fig. 6 to 11 are schematic structural diagrams corresponding to each step in a method for manufacturing a flash memory device according to an embodiment of the invention;
wherein, the reference numerals are as follows:
100-a substrate; 101-isolation trenches; 102 an isolation layer; 110-a gate dielectric layer; a 111-hard mask layer; 120-floating gate layer;
200-substrate; 201-an isolation trench; 202 an isolation layer; 210-a gate dielectric layer; 211-a hard mask layer; 220-a floating gate layer; 230-a protective layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 to fig. 4 are schematic structural diagrams corresponding to partial steps in a method for manufacturing a Nord flash memory.
First, referring to fig. 1, a substrate 100 is provided, and a gate dielectric layer 110 and a hard mask layer 111 are formed on the substrate 100; a patterned photoresist layer (not shown) is formed on the hard mask layer 111, and the hard mask layer 111, the gate dielectric layer 110 and the substrate 100 are etched using the patterned photoresist layer as a mask to form isolation trenches 101. Optionally, the substrate 100 is a silicon substrate. Optionally, the gate dielectric layer 110 is a silicon oxide layer. Optionally, the hard mask layer 111 is a silicon nitride layer.
Subsequently, referring to fig. 2, an isolation material (not shown) is filled in the isolation trench 101, and the isolation material extends to cover the hard mask layer 111; performing planarization to remove the isolation material on the hard mask layer 111 to form an isolation layer 102, wherein the isolation layer 102 is level with the hard mask layer 111; and removing the hard mask layer 111. Optionally, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is used for planarization. Optionally, a wet etching process is used to remove the hard mask layer 111.
Next, referring to fig. 3, a floating gate layer 120 is formed on the gate dielectric layer 110 and the isolation layer 102, and a thickness D1 of the floating gate layer 120 is greater than a height difference H1 between the surface of the isolation layer 102 and the substrate 100 (where the thickness of the gate dielectric layer 110 is negligible).
Subsequently, referring to fig. 4, a planarization process is performed to thin the floating gate layer 120, so that the surface of the isolation layer 102 is exposed. Optionally, a chemical mechanical polishing process is used to planarize the substrate. At this time, the thickness D1' of the floating gate layer 120 is equal to the height difference H1 between the surface of the isolation layer 102 and the substrate 100 (here, the thickness of the gate dielectric layer 110 is negligible).
However, in the manufacturing process of the Nord flash memory, when the thickness of the floating gate layer is thinned through the chemical mechanical masking process, the thickness uniformity of the floating gate layer is adversely affected to some extent. Meanwhile, the thickness of the floating gate layer formed by the existing method is still thicker, which is not beneficial to improving the storage performance of the Nord flash memory.
In order to solve the above problems, the present invention provides a method for manufacturing a flash memory device, which reduces the thickness of a floating gate layer and simultaneously controls the thickness uniformity of the floating gate layer to improve the storage performance of the flash memory device.
Fig. 5 is a flowchart of a method for manufacturing a flash memory device according to the present embodiment. Referring to fig. 5, the method for manufacturing a flash memory device according to the present embodiment includes:
step S01: providing a substrate, wherein a hard mask layer is formed on the substrate, an isolation trench is formed in the hard mask layer, and the isolation trench extends into the substrate;
step S02: filling an isolation layer in the isolation trench, and removing the hard mask layer to expose part of the side wall of the isolation layer;
step S03: forming a floating gate layer, wherein the floating gate layer covers the surface of the substrate, the surface of the isolation layer and part of the side wall, and the thickness of the floating gate layer is smaller than the height difference between the surface of the substrate and the surface of the isolation layer;
step S04: forming a protective layer on the floating gate layer;
step S05: carrying out planarization treatment to ensure that the height difference between the surface of the isolation layer and the surface of the floating gate layer on the substrate is smaller than a certain thickness so as to expose the floating gate layer on the side wall of the isolation layer; the method comprises the steps of,
step S06: removing the protective layer to expose the floating gate layer 。
Fig. 6 to 11 are schematic structural diagrams corresponding to each step in the method for manufacturing a flash memory device according to the present embodiment. The method of manufacturing the flash memory device according to the present embodiment is described in detail below with reference to fig. 6 to 11.
First, referring to fig. 6, step S01 is performed to provide a substrate 200, wherein a hard mask layer 211 is formed on the substrate 200, an isolation trench 201 is formed in the hard mask layer 211, and the isolation trench 201 extends into the substrate 100.
Illustratively, the forming of the isolation trench 202 includes: forming a patterned photoresist layer (not shown) on the hard mask layer 211; etching the hard mask layer 211 and the substrate 200 with the patterned photoresist layer as a mask to form the isolation trenches 202 within the hard mask layer 211 and the substrate 200; and removing the patterned photoresist layer. Optionally, a plasma etching process is used to etch the hard mask layer 211 and the substrate 200. Optionally, a wet cleaning process is used to remove the patterned photoresist layer.
In this embodiment, the substrate 200 is a silicon substrate, and the hard mask layer 211 is a silicon nitride layer. Optionally, a gate dielectric layer 210 is further formed between the substrate 200 and the hard mask layer 211, and the gate dielectric layer 210 is a silicon oxide layer.
Next, referring to fig. 7, step S02 is performed to fill the isolation layer 202 in the isolation trench 201, and remove the hard mask layer 211 to expose a portion of the sidewall of the isolation layer 201.
Illustratively, the filling process of the isolation layer 202 includes: filling the isolation trenches 201 with an isolation material (not shown) extending over the hard mask layer 211; a planarization process is performed to remove the isolation material on the hard mask layer 211 to form an isolation layer 202, and the isolation layer 202 is flush with the hard mask layer 211. Optionally, the isolation material is deposited by a chemical vapor deposition process, and planarization is performed by a chemical mechanical polishing process. Optionally, the isolation layer 202 is a silicon oxide layer.
In this embodiment, the hard mask layer 211 is removed by a wet etching process, so that a sidewall of a portion of the isolation layer 201 higher than the substrate 200 is exposed.
Subsequently, referring to fig. 8, step S03 is performed to form a floating gate layer 220, the floating gate layer 220 covers the surface of the substrate 200 and the surface and part of the sidewall of the isolation layer 202, and the thickness D2 of the floating gate layer 220 is smaller than the height difference H2 between the surface of the substrate 200 and the surface of the isolation layer 202.
Note that, since the thickness D2 of the floating gate layer 220 is smaller than the height difference H2 between the surface of the substrate 200 and the surface of the isolation layer 202, the surface of the floating gate layer 220 on the substrate 200 is lower than the surface of the isolation layer 202. Optionally, the thickness of the floating gate layer 220 ranges from 10nm to 60nm.
Next, referring to fig. 9, step S04 is performed to form a protection layer 230 on the floating gate layer 220. In this embodiment, the passivation layer 230 is formed by a thermal oxidation growth process, and the passivation layer 230 is a high temperature oxide layer (High Temperature Oxidation, HTO).
Subsequently, referring to fig. 10, a planarization process is performed to make a height difference H3 between the surface of the isolation layer 202 and the surface of the floating gate layer 220 on the substrate 200 smaller than a certain thickness, so as to expose the floating gate layer 220 on the sidewall of the isolation layer 202. Optionally, the planarization process is performed using a chemical mechanical polishing process.
In this embodiment, after the planarization process, the remaining thickness of the protection layer 230 is 5% -15% of the total thickness of the protection layer 230, and the protection layer 230 protects the floating gate layer 220 during the planarization process, so as to avoid a reduction in thickness uniformity of the floating gate layer 220.
Next, referring to fig. 11, step S06 is performed to remove the protection layer 230 to expose the floating gate layer 220. Optionally, a wet etching process is used to remove the protective layer 230.
In this embodiment, the material of the isolation layer 202 is the same as the material of the protection layer 230, and is silicon oxide. Thus, the protective layer 230 is removed, and a portion of the spacer 202 is removed, so that the surface of the remaining spacer 202 is flush with the surface of the floating gate layer 220 on the substrate 200. Optionally, the etching thickness of the isolation layer 202 in the wet etching process is 4 nm-6 nm.
In this embodiment, the method for manufacturing the flash memory device is used for manufacturing the Nord flash memory, and in other embodiments of the present invention, the method for manufacturing the flash memory device may be used for manufacturing other semiconductor devices with the same or similar structures, which is not limited in the present invention.
As can be seen from comparing fig. 4 and 11, in the conventional method for manufacturing the Nord device, the thickness D1' of the floating gate layer 120 is relatively thick, and when the thickness of the floating gate layer 120 is reduced by the chemical mechanical masking process, the uniformity of the thickness of the floating gate layer 120 is negatively affected to some extent. In the method for manufacturing a flash memory device according to the embodiment, the thickness D2 of the floating gate layer 220 is relatively thin, and the method for manufacturing a flash memory device according to the embodiment forms the protective layer 230 between the forming process and the planarization process of the floating gate layer 220, so as to avoid the thickness uniformity of the floating gate layer 220 from being reduced during the planarization process, thereby improving the storage performance of the flash memory device finally formed.
In summary, the present invention provides a method for manufacturing a flash memory device, in which an isolation layer is formed in an isolation trench in a substrate, the surface of the isolation layer is higher than the substrate, and a portion of a sidewall of the isolation layer is exposed; forming a floating gate layer to cover the surface of the substrate and the surface and part of the side wall of the isolation layer, wherein the thickness of the floating gate layer is smaller than the height difference between the surface of the substrate and the surface of the isolation layer; forming a protective layer on the floating gate layer; carrying out planarization treatment to ensure that the height difference between the surface of the isolation layer and the surface of the floating gate layer on the substrate is smaller than a certain thickness so as to expose the floating gate layer on the side wall of the isolation layer; and removing the protective layer to expose the floating gate layer. The thickness of the floating gate layer in the finally formed flash memory device is reduced by controlling the thickness of the floating gate layer in the forming process, and meanwhile, the floating gate layer is protected in the planarization process by forming the protective layer, so that the thickness uniformity of the floating gate layer is prevented from being reduced, and the shape stability and the storage performance of the flash memory device are improved.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a hard mask layer is formed on the substrate, an isolation trench is formed in the hard mask layer, and the isolation trench extends into the substrate;
filling an isolation layer in the isolation trench, and removing the hard mask layer to expose part of the side wall of the isolation layer;
forming a floating gate layer, wherein the floating gate layer covers the surface of the substrate, the surface of the isolation layer and part of the side wall, and the thickness of the floating gate layer is smaller than the height difference between the surface of the substrate and the surface of the isolation layer;
forming a protective layer on the floating gate layer;
carrying out planarization treatment to ensure that the height difference between the surface of the isolation layer and the surface of the floating gate layer on the substrate is smaller than a certain thickness so as to expose the floating gate layer on the side wall of the isolation layer; the method comprises the steps of,
and removing the protective layer to expose the floating gate layer.
2. The method of manufacturing a flash memory device according to claim 1, wherein a remaining thickness of the protective layer after the planarization process is 5% to 15% of a total thickness of the protective layer.
3. The method of manufacturing a flash memory device according to claim 1 or 2, wherein the planarization process is performed using a chemical mechanical polishing process.
4. The method of manufacturing a flash memory device of claim 1, wherein the protective layer is removed using a wet etching process.
5. The method of manufacturing a flash memory device of claim 4, wherein a material of the spacer layer is the same as a material of the protective layer.
6. The method of manufacturing a flash memory device according to claim 5, wherein a portion of the spacer is removed while removing the protective layer so that a surface of the spacer is flush with a surface of the floating gate layer on the substrate.
7. The method of manufacturing a flash memory device of claim 1, wherein the protective layer is a high temperature oxide layer.
8. The method of manufacturing a flash memory device of claim 1, wherein the forming of the isolation trench comprises:
forming a patterned photoresist layer on the hard mask layer;
and etching the hard mask layer and the substrate by taking the patterned photoresist layer as a mask so as to form the isolation trench in the hard mask layer and the substrate.
9. The method of manufacturing a flash memory device of claim 1, wherein a gate dielectric layer is further formed between the substrate and the floating gate layer.
10. The method of manufacturing a flash memory device of claim 1, wherein the method of manufacturing a flash memory device is used to manufacture a Nord flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310789490.7A CN116847655A (en) | 2023-06-29 | 2023-06-29 | Method for manufacturing flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310789490.7A CN116847655A (en) | 2023-06-29 | 2023-06-29 | Method for manufacturing flash memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116847655A true CN116847655A (en) | 2023-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310789490.7A Pending CN116847655A (en) | 2023-06-29 | 2023-06-29 | Method for manufacturing flash memory device |
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| Country | Link |
|---|---|
| CN (1) | CN116847655A (en) |
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2023
- 2023-06-29 CN CN202310789490.7A patent/CN116847655A/en active Pending
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