CN116206964A - Method for manufacturing flash memory device - Google Patents
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- CN116206964A CN116206964A CN202310320106.9A CN202310320106A CN116206964A CN 116206964 A CN116206964 A CN 116206964A CN 202310320106 A CN202310320106 A CN 202310320106A CN 116206964 A CN116206964 A CN 116206964A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 246
- 238000007667 floating Methods 0.000 claims abstract description 82
- 239000011229 interlayer Substances 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 abstract description 9
- 238000001039 wet etching Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000877 morphologic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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Abstract
The invention provides a manufacturing method of a flash memory device, which comprises the steps of sequentially forming a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer with an opening on a substrate; forming a first side wall on the side wall of the opening and removing the control gate layer exposed by the opening; forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening to expose the floating gate layer below the opening; removing the floating gate layer exposed at the bottom of the opening, and forming a word line in the opening; and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate. The invention cancels the wet etching process of the interlayer dielectric layer before the preparation process of the second side wall, and ensures that the interlayer dielectric layer protects the floating gate layer from being damaged by etching in the preparation process of the second side wall, thereby ensuring the stable morphology of the floating gate and the floating gate tip formed subsequently and improving the stability and yield of the product performance.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a method for manufacturing a flash memory device.
Background
The flash memory device is used as a nonvolatile memory, and the threshold voltage of a transistor or a memory unit is changed to control the switch of a gate channel, so that the aim of storing data is fulfilled, and the data stored in the memory cannot disappear due to power interruption. In the existing flash memory device, the sharpness of the tip of the floating gate can influence the coupling voltage of the floating gate during programming and erasing, thereby influencing the performance of the flash memory device during programming and erasing. Therefore, precisely controlling the tip of the floating gate has a strong practical meaning for controlling the performance of the flash memory.
Referring to fig. 1 to 3, in the conventional manufacturing process of the flash memory device, a wet etching process is generally used to remove the interlayer dielectric layer 20 exposed at the bottom of the opening 10, so that the floating gate layer 30 under the opening 10 is exposed; next, a sidewall 40 is formed on the sidewall of the opening 10 through a sidewall deposition and etching process. The etching process of the sidewall 40 includes a Main etching process (Main etching, ME, typically dry etching) and an Over etching process (Over etching, OE, typically wet etching).
The sidewall 40 is subjected to an Over Etch (OE) process for a longer period of time in order to increase the process window for the subsequent process. However, with continued reference to fig. 3, the longer the over-etching time of the sidewall 40, the greater the etching damage to the floating gate layer 30 exposed at the bottom of the opening 10, and the greater the size of the damaged pit 31. Referring to fig. 4, the pit 31 is generated to damage the floating gate tip a of the floating gate 32 formed later. The larger the size of the pit 31, the more blunt the floating gate tip a is subsequently formed, thereby affecting the performance of the finally formed flash memory device and even causing the flash memory device to fail in severe cases.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory device, which reduces or avoids damage to a floating gate layer in the preparation process of a side wall and ensures the stable appearance of a floating gate and a floating gate tip.
In order to achieve the above object, the present invention provides a method for manufacturing a flash memory device, comprising:
providing a substrate, wherein a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate, and an opening exposing the control gate layer is formed on the hard mask layer;
forming a first side wall on the side wall of the opening, and removing the control gate layer exposed by the opening to expose the interlayer dielectric layer below the opening;
forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening to expose the floating gate layer below the opening;
removing the floating gate layer exposed at the bottom of the opening, and forming a word line in the opening; the method comprises the steps of,
and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate.
Optionally, forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening includes:
forming a second side wall material layer on the surface of the hard mask layer, the side wall of the opening and the bottom of the opening;
performing main etching to remove the surface of the hard mask layer and the second side wall material layer at the bottom of the opening so as to form a second side wall on the side wall of the opening; the method comprises the steps of,
and performing over etching to further etch the second side wall, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening, so that the top end of the second side wall is lower than the top end of the first side wall, and the floating gate layer below the opening is exposed.
Optionally, etching the second side wall and the interlayer dielectric layer by adopting anisotropic dry etching.
Optionally, the second side wall is an ON laminated structure formed by stacking a silicon oxide layer and a silicon nitride layer.
Optionally, the interlayer dielectric layer is an ONO laminated structure formed by stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer in sequence.
Optionally, after removing the floating gate layer exposed by the opening, before forming the word line, the method further includes:
and forming a third side wall on the side wall and the bottom wall of the opening.
Optionally, the third side wall is a silicon oxide layer.
Optionally, a gate dielectric layer is further formed between the substrate and the floating gate layer.
Optionally, the hard mask layer is a silicon nitride layer.
Optionally, the method for manufacturing the flash memory device is used for manufacturing the split gate flash memory device 。
In summary, the present invention provides a method for manufacturing a flash memory device, in which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer having an opening are sequentially formed on a substrate; forming a first side wall on the side wall of the opening and removing the control gate layer exposed by the opening; forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening to expose the floating gate layer below the opening; removing the floating gate layer exposed at the bottom of the opening, and forming a word line in the opening; and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate. The invention cancels the wet etching process of the interlayer dielectric layer before the preparation process of the second side wall, and ensures that the interlayer dielectric layer protects the floating gate layer from being damaged by etching in the preparation process of the second side wall, thereby ensuring the stable morphology of the floating gate and the floating gate tip formed subsequently and improving the stability and yield of the product performance.
Drawings
FIGS. 1 to 4 are schematic views illustrating the structure of a flash memory device corresponding to a portion of steps in the manufacturing process;
FIG. 5 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention;
fig. 6 to 10 are schematic structural diagrams corresponding to each step in a method for manufacturing a flash memory device according to an embodiment of the invention;
wherein, the reference numerals are as follows:
10-opening; 20-an interlayer dielectric layer; 30-a floating gate layer; 31-pit; 32-floating gate; 40-side walls;
100-a substrate; 101-a gate dielectric layer; 110-a floating gate layer; 111-floating gate; 120-an interlayer dielectric layer; 130-a control gate layer; 131-a control gate; 140-a hard mask layer; 150-opening; 151-a first side wall; 152-a second side wall; 153-a third side wall; 160-word lines;
A. b-floating gate tip.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 5 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention. Referring to fig. 5, the method for manufacturing a flash memory device according to the present embodiment includes:
step S01: providing a substrate, wherein a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate, and an opening exposing the control gate layer is formed on the hard mask layer;
step S02: forming a first side wall on the side wall of the opening, and removing the control gate layer exposed by the opening to expose the interlayer dielectric layer below the opening;
step S03: forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening to expose the floating gate layer below the opening;
step S04: removing the floating gate layer exposed at the bottom of the opening, and forming a word line in the opening; the method comprises the steps of,
step S05: and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate.
Fig. 6 to 10 are schematic structural diagrams corresponding to each step in the method for manufacturing a flash memory device according to the present embodiment. The method of manufacturing the flash memory device according to the present embodiment is described in detail below with reference to fig. 6 to 10.
First, referring to fig. 6, step S01 is performed to provide a substrate 100, where a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130, and a hard mask layer 140 are sequentially formed on the substrate 100, and an opening 150 exposing the control gate layer 130 is formed on the hard mask layer 140.
Illustratively, the process of forming the opening 150 includes: sequentially depositing a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130 and a hard mask layer 140 on the substrate 100; next, the hard mask layer 140 is patterned, a patterned photoresist layer (not shown) is formed on the hard mask layer 140, and the hard mask layer 140 is etched using the patterned photoresist layer as a mask to form an opening 150 on the hard mask layer 140. Optionally, after forming the opening 150, the patterned photoresist layer is removed by a photoresist removal process. Alternatively, the floating gate layer 110, the interlayer dielectric layer 120, the control gate layer 130, and the hard mask layer 140 are formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD), respectively.
In this embodiment, the substrate 100 is a silicon substrate, the floating gate layer 110 and the control gate layer 130 are polysilicon layers, the hard mask layer 140 is a silicon nitride layer, and the interlayer dielectric layer 120 is an ONO stack structure formed by stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer in sequence. Optionally, a gate dielectric layer 101 is further formed between the substrate 100 and the floating gate layer 110, and the gate dielectric layer 101 is a silicon oxide layer. In other embodiments of the present invention, the materials and structures of the foregoing film layers may be adjusted according to actual needs, for example, the material of the gate dielectric layer 101 may be replaced by other oxide materials (such as ethyl orthosilicate), which is not limited in the present invention.
Next, referring to fig. 7, step S02 is performed to form a first sidewall 151 on a sidewall of the opening 150, and remove the control gate layer 130 exposed by the opening 150, so as to expose the interlayer dielectric layer 120 under the opening 150.
Illustratively, the forming the first side wall 151 and removing the control gate layer 130 exposed by the opening 150 includes: depositing a first sidewall material layer (not shown) within the opening 150, the first sidewall material layer extending over the surface of the hard mask layer 140 on both sides of the opening 150; etching to remove the surface of the hard mask layer 140 and the first sidewall material layer at the bottom of the opening 150, so as to form a first sidewall 151 on the sidewall of the opening 150; next, the control gate layer 130 exposed by the opening 150 is etched using the hard mask layer 140 and the first sidewall 151 as a mask, so that the interlayer dielectric layer 120 under the opening 150 is exposed. Optionally, the first side wall 151 is a silicon oxide layer.
Subsequently, referring to fig. 8, step S03 is performed to form a second sidewall 152 on the sidewall of the opening 150, and remove the interlayer dielectric layer 120 exposed at the bottom of the opening 150, so as to expose the floating gate layer 110 under the opening 150.
Illustratively, forming the second sidewall 152 on the sidewall of the opening 150 includes: forming a second sidewall material layer (not shown) on the surface of the hard mask layer 140, the sidewall of the opening 150, and the bottom of the opening 150; performing main etching to remove the surface of the hard mask layer 140 and the second sidewall material layer at the bottom of the opening 150, so as to form a second sidewall 152 on the sidewall of the opening 150; and, performing over etching to further etch the second side wall 152, and simultaneously removing the interlayer dielectric layer 120 exposed at the bottom of the opening 150, so that the top end of the second side wall 152 is lower than the top end of the first side wall 151, and exposing the floating gate layer 110 under the opening 150.
In this embodiment, an anisotropic dry etching process is used to etch the second sidewall 152 and the interlayer dielectric layer 120. Wherein, the etching selectivity ratio of the over etching process to the silicon nitride layer and the polysilicon layer is higher than that of the main etching process to the silicon nitride layer and the polysilicon layer. Optionally, the second sidewall 152 is an ON stack structure formed by stacking a silicon oxide layer and a silicon nitride layer.
It should be noted that, in step S02, the interlayer dielectric layer 120 at the bottom of the opening 150 is not removed, so the second sidewall material layer at the bottom of the opening 150 is directly deposited on the surface of the interlayer dielectric layer 120. After the main etching is completed, the second sidewall material layer at the bottom of the opening 150 is removed, so that the interlayer dielectric layer 120 at the bottom of the opening 150 is exposed, and at this time, the interlayer dielectric layer 120 is not etched or is damaged by etching with a partial thickness. Meanwhile, since the interlayer dielectric layer 120 at the bottom of the opening 150 is exposed after the main etching, the interlayer dielectric layer 120 always covers the floating gate layer 110 below the opening in the over etching process, and the interlayer dielectric layer 120 can be completely removed in the over etching process by adjusting the etching time or other parameters of the over etching process.
As described above, since the floating gate layer 110 below the opening 150 is always covered by the interlayer dielectric layer 120 in the over-etching process, the floating gate layer 110 is not damaged by etching in the process of preparing the second sidewall 152, so that the stability of the floating gate morphology formed later is ensured.
Next, referring to fig. 9, step S04 is performed to remove the floating gate layer 110 exposed at the bottom of the opening 150, and form the word line 160 in the opening 150.
Illustratively, the forming of the word line 160 includes: etching the floating gate layer 110 exposed by the opening 150 and the gate dielectric layer 101 under the opening 150 by using the hard mask layer 140, the first side wall 151 and the second side wall 152 as masks, so that the opening 150 exposes the substrate 100; forming a third side wall 153 on the side wall and the bottom of the opening 150 (the forming process of the third side wall 153 is similar to the forming process of the first side wall 151, and will not be repeated here); a word line material layer (not shown) is deposited in the opening 150 and on the hard mask layer 140 on both sides of the opening 150, and the word line material layer is planarized and etched to form a word line 160 in the opening 150. Optionally, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is used for planarization. Optionally, the third sidewall 153 is a silicon oxide layer. The word line 160 is a polysilicon layer.
Subsequently, referring to fig. 10, step S05 is performed to remove the hard mask layer 140 and the control gate layer 130, the interlayer dielectric layer 120 and the floating gate layer 110 under the hard mask layer 140 to form the control gate 131 and the floating gate 111. Optionally, a dry etching process is used to remove the hard mask layer 140 and the control gate layer 130, the interlayer dielectric layer 120, the floating gate layer 110 and the gate dielectric layer 101 under the hard mask layer 140.
In this embodiment, the method for manufacturing a flash memory device is used to manufacture a split gate flash memory device, and in other embodiments of the present invention, the method for manufacturing a flash memory device may also be used to manufacture other types of flash memory devices or other semiconductor devices with the same structure, which is not limited in this invention.
Comparing fig. 4 and 10, it can be seen that the floating gate tip a is relatively blunt in the conventional flash memory device, which affects the coupling voltage of the floating gate 32 during programming and erasing, thereby affecting the performance of the flash memory device during programming and erasing. In the method for manufacturing the flash memory device according to the embodiment, the wet etching process of the interlayer dielectric layer 120 performed before the preparation process of the second side wall 152 is omitted, so that the interlayer dielectric layer 120 protects the floating gate layer from being damaged by etching in the preparation process of the second side wall 152, and the floating gate tip B in the finally manufactured floating gate 111 is sharper, thereby ensuring the morphological stability and performance stability of the flash memory device.
In summary, the present invention provides a method for manufacturing a flash memory device, in which a floating gate layer, an interlayer dielectric layer, a control gate layer, and a hard mask layer having an opening are sequentially formed on a substrate; forming a first side wall on the side wall of the opening and removing the control gate layer exposed by the opening; forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening to expose the floating gate layer below the opening; removing the floating gate layer exposed at the bottom of the opening, and forming a word line in the opening; and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate. The invention cancels the wet etching process of the interlayer dielectric layer before the preparation process of the second side wall, and ensures that the interlayer dielectric layer protects the floating gate layer from being damaged by etching in the preparation process of the second side wall, thereby ensuring the stable morphology of the floating gate and the floating gate tip formed subsequently and improving the stability and yield of the product performance.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate, and an opening exposing the control gate layer is formed on the hard mask layer;
forming a first side wall on the side wall of the opening, and removing the control gate layer exposed by the opening to expose the interlayer dielectric layer below the opening;
forming a second side wall on the side wall of the opening, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening to expose the floating gate layer below the opening;
removing the floating gate layer exposed at the bottom of the opening, and forming a word line in the opening; the method comprises the steps of,
and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate.
2. The method of manufacturing a flash memory device as claimed in claim 1, wherein forming a second sidewall on the sidewall of the opening while removing the interlayer dielectric layer exposed at the bottom of the opening comprises:
forming a second side wall material layer on the surface of the hard mask layer, the side wall of the opening and the bottom of the opening;
performing main etching to remove the surface of the hard mask layer and the second side wall material layer at the bottom of the opening so as to form a second side wall on the side wall of the opening; the method comprises the steps of,
and performing over etching to further etch the second side wall, and simultaneously removing the interlayer dielectric layer exposed at the bottom of the opening, so that the top end of the second side wall is lower than the top end of the first side wall, and the floating gate layer below the opening is exposed.
3. The method of manufacturing a flash memory device of claim 2, wherein the second sidewall and the interlayer dielectric layer are etched using an anisotropic dry etching process.
4. The method of manufacturing a flash memory device as claimed in claim 3, wherein the second sidewall is an ON stack structure of a silicon oxide layer and a silicon nitride layer stacked.
5. The method of manufacturing a flash memory device according to claim 1 or 4, wherein the interlayer dielectric layer is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer in this order.
6. The method of manufacturing a flash memory device of claim 1, further comprising, after removing the floating gate layer exposed by the opening, before forming the word line:
and forming a third side wall on the side wall and the bottom wall of the opening.
7. The method of claim 6, wherein the third sidewall is a silicon oxide layer.
8. The method of manufacturing a flash memory device of claim 1, wherein a gate dielectric layer is further formed between the substrate and the floating gate layer.
9. The method of manufacturing a flash memory device of claim 1, wherein the hard mask layer is a silicon nitride layer.
10. The method of manufacturing a flash memory device of claim 1, wherein the method of manufacturing a flash memory device is used to manufacture a split gate flash memory device.
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