CN116322051A - Method for manufacturing flash memory device - Google Patents
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- CN116322051A CN116322051A CN202310471124.7A CN202310471124A CN116322051A CN 116322051 A CN116322051 A CN 116322051A CN 202310471124 A CN202310471124 A CN 202310471124A CN 116322051 A CN116322051 A CN 116322051A
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Abstract
The invention provides a manufacturing method of a flash memory device, which comprises the steps of sequentially forming a floating gate material layer, an erasing gate material layer and a hard mask layer on a substrate; forming a first opening exposing the floating gate material layer in the hard mask layer and the erase gate material layer through a first photolithography and etching process; filling a first side wall material layer in the first opening; forming a second opening exposing the substrate in the first side wall material layer and the floating gate material layer through a second photoetching and etching process, and forming a first side wall by the remaining first side wall material layer; forming a source line in the second opening; and removing part of the hard mask layer and the erasing gate material layer and the floating gate material layer below the hard mask layer through a third photoetching and etching process so as to form a floating gate and an erasing gate on two sides of the source line. The first opening, the second opening, the floating gate and the erasing gate are formed respectively through multiple photoetching and etching processes, so that the process steps of the flash memory device are simplified, and the overall height of the flash memory device is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a method for manufacturing a flash memory device.
Background
With the development of technology, data storage medium application is changed from some traditional nonvolatile memories to flash memories, and a mass solid-state storage device using flash memory as a main storage medium has become one of the mainstream schemes of data storage today. Flash memory devices have gained increasing importance in the memory field due to their low cost, low power consumption, fast access speed, and other performance advantages.
The existing flash memory device is usually formed by adopting a Self-aligned (Self-aligned) mode, and because a multi-step side wall needs to be formed in the preparation process, the height of a finally formed flash memory unit is higher, and the flash memory unit is inconvenient to integrate with a logic process of a high-order node (for example, 28nm or 40 nm). In addition, in the manufacturing process of the flash memory device, the multi-step side wall deposition and etching process causes the complexity of the process program of the flash memory device to be increased, and the production efficiency is reduced.
In view of this, there is a need for a method to reduce the overall height of a flash memory device and simplify the process steps of the flash memory device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory device, which reduces the overall height of the flash memory device and simplifies the process steps of the flash memory device.
In order to achieve the above object, the present invention provides a method for manufacturing a flash memory device, comprising:
providing a substrate, wherein a floating gate material layer, an erasing gate material layer and a hard mask layer are sequentially formed on the substrate;
performing a first photoetching and etching process to form a first opening exposing the floating gate material layer in the hard mask layer and the erasing gate material layer;
filling a first side wall material layer in the first opening;
performing a second photoetching and etching process, forming a second opening exposing the substrate in the first side wall material layer and the floating gate material layer, and forming a first side wall by the residual first side wall material layer;
forming a source line in the second opening; the method comprises the steps of,
and performing a third photoetching and etching process, and removing part of the hard mask layer and the erasing gate material layer and the floating gate material layer below the hard mask layer to form a floating gate and an erasing gate on two sides of the source line.
Optionally, after forming the floating gate and the erase gate, the method further includes:
forming second side walls on the side walls of the floating gate and the erasing gate, which are far away from the source line;
and forming a word line on one side of the second side wall far away from the floating gate, and forming a third side wall on the side wall of the word line.
Optionally, after the second photolithography and etching process, before forming the source line, the method further includes:
forming a source region in the substrate exposed by the second opening;
and forming a source line dielectric layer on the side wall and the bottom of the second opening.
Optionally, after forming the third sidewall, the method further includes:
and forming a drain region in the substrate at one side of the third side wall far away from the word line.
Optionally, an ion implantation process is used to form the source region and the drain region respectively.
Optionally, a floating gate dielectric layer is further formed between the substrate and the floating gate material layer, and a tunneling dielectric layer is further formed between the floating gate material layer and the erase gate material layer.
Optionally, the floating gate dielectric layer and the tunneling dielectric layer are stacked structures formed by a silicon oxide layer, a silicon nitride layer or a combination thereof.
Optionally, the first side wall, the second side wall, the third side wall and the source line dielectric layer are silicon oxide layers.
Optionally, the hard mask layer is a silicon nitride layer.
Optionally, the flash memory device is a split gate memory.
In summary, the present invention provides a method for manufacturing a flash memory device, in which a floating gate material layer, an erase gate material layer and a hard mask layer are sequentially formed on a substrate; forming a first opening exposing the floating gate material layer in the hard mask layer and the erase gate material layer through a first photolithography and etching process; filling a first side wall material layer in the first opening; forming a second opening exposing the substrate in the first side wall material layer and the floating gate material layer through a second photoetching and etching process, and forming a first side wall by the residual first side wall material layer; forming a source line in the second opening; and removing part of the hard mask layer and the erasing gate material layer and the floating gate material layer below the hard mask layer through a third photoetching and etching process so as to form a floating gate and an erasing gate on two sides of the source line. The first opening, the second opening, the floating gate and the erasing gate are formed respectively through multiple photoetching and etching processes, so that the process steps of the flash memory device are simplified, and the overall height of the flash memory device is reduced.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory device according to an embodiment of the present invention;
fig. 2 to 12 are schematic structural diagrams corresponding to each step in a method for manufacturing a flash memory device according to an embodiment of the present invention;
wherein, the reference numerals are as follows:
100-a substrate; 101-source region; 102-drain region; 110-a layer of floating gate material; 111-a floating gate dielectric layer; 112-floating gate; 120-an erase gate material layer; 121-tunneling the dielectric layer; 122-erase gate; 130-a hard mask layer; 131-a first opening; 132-a first side wall material layer; 133-a second opening; 134-a first side wall; 140-source line; 141-a source line dielectric layer; 150-a second side wall; 160-word lines; 161-third side wall.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the invention. Referring to fig. 1, the method for manufacturing a flash memory device according to the present embodiment includes:
step S01: providing a substrate, wherein a floating gate material layer, an erasing gate material layer and a hard mask layer are sequentially formed on the substrate;
step S02: performing a first photoetching and etching process to form a first opening exposing the floating gate material layer in the hard mask layer and the erasing gate material layer;
step S03: filling a first side wall material layer in the first opening;
step S04: performing a second photoetching and etching process, forming a second opening exposing the substrate in the first side wall material layer and the floating gate material layer, and forming a first side wall by the residual first side wall material layer;
step S05: forming a source line in the second opening;
step S06: and performing a third photoetching and etching process, and removing part of the hard mask layer and the erasing gate material layer and the floating gate material layer below the hard mask layer to form a floating gate and an erasing gate on two sides of the source line.
Fig. 2 to 12 are schematic structural diagrams corresponding to each step in the method for manufacturing a flash memory device according to the present embodiment. The method for manufacturing the flash memory device according to the present embodiment is described in detail below with reference to fig. 2 to 12.
First, referring to fig. 2, step S01 is performed to provide a substrate 100, on which a floating gate material layer 110, an erase gate material layer 120, and a hard mask layer 130 are sequentially formed on the substrate 100.
In this embodiment, a floating gate dielectric layer 111 is further formed between the substrate 100 and the floating gate material layer 110. A tunneling dielectric layer 121 is further formed between the floating gate material layer 110 and the erase gate material layer 120. In this embodiment, the substrate 100 is a silicon substrate. The floating gate material layer 110 and the erase gate material layer 120 are polysilicon layers. The floating gate dielectric layer 111 and the tunneling dielectric layer 121 are stacked structures (including an ON stacked structure formed by stacking a silicon oxide layer and a silicon nitride layer, and an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer) formed by stacking a silicon oxide layer, a silicon nitride layer, or a combination thereof. The hard mask layer is a silicon nitride layer. In other embodiments of the present invention, the specific materials of each film layer of the flash memory device may be adjusted according to the process requirements, which is not limited by the present invention.
Illustratively, the process of forming the flash memory device shown in FIG. 2 includes: providing a substrate 100, and depositing a floating gate dielectric layer 111 on the substrate 100; depositing a floating gate material layer 110 on the floating gate dielectric layer 111, and performing planarization treatment on the floating gate material layer 110 to form a separate floating gate material layer 110 by stopping on the shallow trench isolation structure; forming a tunneling dielectric layer 121 on the floating gate material layer 110; depositing an erase gate material layer 120 on the tunneling dielectric layer 121; and depositing a hard mask layer 130 on the erase gate material layer 120. Optionally, a planarization process is performed using a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP); the film layers are respectively deposited and formed by adopting a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
Next, referring to fig. 3, step S02 is performed to perform a first photolithography and etching process to form a first opening 131 exposing the floating gate material layer 110 in the hard mask layer 130 and the erase gate material layer 120.
Illustratively, the forming of the first opening 131 includes: a first photolithography and etching process is performed to form a patterned first photoresist layer (not shown) on the hard mask layer 130, and the hard mask layer 130, the erase gate material layer 120 and the tunneling dielectric layer 121 are etched using the patterned first photoresist layer as a mask to form a first opening 131 exposing the floating gate material layer 110. Optionally, after the first photolithography and etching process is completed, the method further includes: and removing the patterned first photoresist layer.
Next, referring to fig. 4, step S03 is performed to fill the first sidewall material layer 132 in the first opening 131.
Illustratively, the process of filling the first sidewall material layer 132 includes: and depositing a first sidewall material layer 132 in the first opening 131 and on the surface of the hard mask layer 130, and performing planarization treatment on the first sidewall material layer 132 to remove the first sidewall material layer 132 except the first opening 131, so that the first sidewall material layer 132 fills the first opening 131. Optionally, a chemical mechanical polishing process is used to planarize the substrate.
In this embodiment, the first sidewall material layer 132 is a silicon oxide layer, and in other embodiments of the present invention, the material of the first sidewall material layer 132 may be adjusted according to actual needs, which is not limited in the present invention.
Subsequently, referring to fig. 5, a second photolithography and etching process is performed in step S04, and a second opening 133 exposing the substrate 100 is formed in the first sidewall material layer 132 and the floating gate material layer 110, and the remaining first sidewall material layer 132 forms a first sidewall 134.
Illustratively, the forming the first sidewall 134 includes: a second photolithography and etching process is performed to form a patterned second photoresist layer (not shown in the figure) on the hard mask layer 130 and the first sidewall material layer 132, the floating gate material layer 110 and the floating gate dielectric layer 111 are etched with the patterned second photoresist layer as a mask to form a second opening 133 exposing the substrate 100, where the remaining first sidewall material layer 132 forms the first sidewall 134. Optionally, after the second photolithography and etching process is completed, the method further includes: and removing the patterned second photoresist layer.
Next, referring to fig. 6 to 8, step S05 is performed to form a source line 140 in the second opening 134.
Illustratively, the forming of the source line 140 includes: referring to fig. 6, an ion implantation process is performed to form a source region 101 in the substrate 100 exposed by the second opening 133; referring to fig. 7, a source line dielectric material is deposited on the side wall and the bottom of the second opening 133 and extends to cover the first side walls 134 on both sides of the second opening 133, and etching is performed on the source line dielectric material to remove the source line dielectric material on the bottom of the second opening 133 and the source line dielectric material outside the second opening 133, so as to form a source line dielectric layer 141 covering the side wall of the second opening 133; next, referring to fig. 8, the second opening 133 is filled with a source line material and extends to cover the first side walls 134 on both sides of the second opening 133, the source line material is planarized, the source line material on the first side walls 134 is removed, and the source line material in the second opening 133 is made to be level with the surface of the first side walls 134, so as to form the source line 140. Optionally, a dry etching process is adopted to etch the source line adhesive material; the planarization process is performed by a chemical mechanical polishing process.
In this embodiment, the source line dielectric layer 141 is a silicon oxide layer, and in other embodiments of the present invention, the source line dielectric layer 141 may be a silicon nitride layer or a stacked structure formed by stacking a silicon oxide layer and a silicon nitride layer. In this embodiment, the source line 140 is a polysilicon layer.
Subsequently, referring to fig. 9 and 10, step S06 is performed to perform a third photolithography and etching process, and remove portions of the hard mask layer 130 and the erase gate material layer 120 and the floating gate material layer 110 thereunder, so as to form the floating gate 112 and the erase gate 122 on both sides of the source line 140.
Illustratively, the forming of the floating gate 112 and the erase gate 122 includes: a third photolithography and etching process is performed, and a patterned third photoresist layer (not shown) is formed on the hard mask layer 130, the first sidewall 134 and the source line 140, and the patterned third photoresist layer is used as a mask to etch a portion of the hard mask layer 130 and the erase gate material layer 120, the tunneling dielectric layer 121, the floating gate material layer 110 and the floating gate dielectric layer 111 under the hard mask layer 130, so as to form the floating gate 112 and the erase gate 122. Optionally, after the third photolithography and etching process is completed, the method further includes: and removing the patterned third photoresist layer.
It should be noted that, during the third photolithography and etching process, the shapes of the floating gate 112 and the erase gate 122 are defined by the patterned third photoresist layer, and the sizes and shapes of the floating gate 112 and the erase gate 122 may be adjusted by adjusting the pattern of the third photoresist layer, so as to adjust the shapes of the flash memory device.
Referring to fig. 10, after forming the floating gate 112 and the erase gate 122, it further includes: a second sidewall 150 is formed on the floating gate 112 and the sidewall of the erase gate 122 away from the source line 140. Specifically, the process of forming the second sidewall 150 includes: a second sidewall material layer (not shown) is deposited on the substrate 100, the hard mask layer 130, the first sidewall 134 and the source line 140, where the second sidewall material layer covers sidewalls of the hard mask layer 130, the floating gate 112 and the erase gate 122 on a side far from the source line 140; the second sidewall material layer is etched to form second sidewalls 150 on sidewalls of the floating gate 112 and the erase gate 122 remote from the source line 140. Optionally, the second sidewall 150 is a silicon oxide layer.
In addition, referring to fig. 11 and 12, after forming the second sidewall 150, the method for manufacturing the flash memory device further includes: forming a word line 160 on a side of the second sidewall 150 away from the floating gate 112, and forming a third sidewall 161 on a sidewall of the word line 160; a drain region 102 is formed in the substrate 100 on the side of the third sidewall 161 remote from the word line 160.
Specifically, the process of forming the word line 160, the third sidewall 161, and the drain region 102 includes: referring to fig. 11, a word line dielectric material layer and a word line material layer (not shown) are sequentially deposited on the substrate 100, the second sidewall 150, the hard mask layer 130, the first sidewall 134 and the source line 140, and a patterned fourth photoresist layer (not shown) is formed on the word line material layer, and the word line material layer and the word line dielectric material layer are etched with the patterned fourth photoresist layer as a mask to form the word line 160 and the word line dielectric layer (the word line dielectric layer is formed between the word line 160 and the substrate 100, not shown); removing the patterned fourth photoresist layer; a third sidewall material layer (not shown) is etched on the substrate 100, the word line 160, the hard mask layer 130, the first sidewall 134 and the source line 140 to form a third sidewall 161 on a sidewall of the word line 160 away from the floating gate 112; and performing an ion implantation process to form a drain region 102 in the substrate 100 on the side of the third sidewall 161 away from the word line 160. Optionally, the third side wall 161 and the word line dielectric layer are both silicon oxide layers, and the third side wall 161 may also be a stacked structure formed by stacking a silicon oxide layer and a silicon nitride layer.
It should be noted that the specific preparation process and preparation process of each step in the method for manufacturing the flash memory device may be adjusted according to actual process requirements, for example, a self-aligned process may be used to form the word line 160, which is a preparation method well known to those skilled in the art, and the present invention is not further developed.
In this embodiment, the method for manufacturing the flash memory device is used for manufacturing the split gate memory, and in other embodiments of the present invention, the method for manufacturing the flash memory device may be used for manufacturing other semiconductor devices with the same or similar structures, which is not limited in the present invention.
In the existing manufacturing method of the flash memory device, such as a Self-aligned (Self-aligned) method, multiple deposition and etching processes are required to form multiple side walls, and the preparation process of the multiple side walls increases the complexity of the process program of the flash memory device and reduces the production efficiency. Meanwhile, the flash memory device finally formed by the method has high height and is inconvenient to integrate with a logic process of a high-order node (for example, 28nm or 40 nm). In the method for manufacturing the flash memory device, the first opening, the second opening and the shapes of the floating gate and the erasing gate are respectively formed through multiple photoetching and etching processes, the shapes of different structures in the flash memory device are defined through photoetching, the process steps of the flash memory device are simplified, the overall height of the flash memory device is reduced, and therefore the flash memory device is integrated with a logic process of a high-order node (for example, 28nm or 40 nm).
In summary, the present invention provides a method for manufacturing a flash memory device, in which a floating gate material layer, an erase gate material layer and a hard mask layer are sequentially formed on a substrate; forming a first opening exposing the floating gate material layer in the hard mask layer and the erase gate material layer through a first photolithography and etching process; filling a first side wall material layer in the first opening; forming a second opening exposing the substrate in the first side wall material layer and the floating gate material layer through a second photoetching and etching process, and forming a first side wall by the residual first side wall material layer; forming a source line in the second opening; and removing part of the hard mask layer and the erasing gate material layer and the floating gate material layer below the hard mask layer through a third photoetching and etching process so as to form a floating gate and an erasing gate on two sides of the source line. The first opening, the second opening, the floating gate and the erasing gate are formed respectively through multiple photoetching and etching processes, so that the process steps of the flash memory device are simplified, and the overall height of the flash memory device is reduced.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a floating gate material layer, an erasing gate material layer and a hard mask layer are sequentially formed on the substrate;
performing a first photoetching and etching process to form a first opening exposing the floating gate material layer in the hard mask layer and the erasing gate material layer;
filling a first side wall material layer in the first opening;
performing a second photoetching and etching process, forming a second opening exposing the substrate in the first side wall material layer and the floating gate material layer, and forming a first side wall by the residual first side wall material layer;
forming a source line in the second opening; the method comprises the steps of,
and performing a third photoetching and etching process, and removing part of the hard mask layer and the erasing gate material layer and the floating gate material layer below the hard mask layer to form a floating gate and an erasing gate on two sides of the source line.
2. The method of manufacturing a flash memory device of claim 1, further comprising, after forming the floating gate and the erase gate:
forming second side walls on the side walls of the floating gate and the erasing gate, which are far away from the source line;
and forming a word line on one side of the second side wall far away from the floating gate, and forming a third side wall on the side wall of the word line.
3. The method of manufacturing a flash memory device of claim 2, further comprising, after performing the second photolithography and etching process, before forming the source line:
forming a source region in the substrate exposed by the second opening;
and forming a source line dielectric layer on the side wall and the bottom of the second opening.
4. The method of manufacturing a flash memory device of claim 3, further comprising, after forming the third sidewall:
and forming a drain region in the substrate at one side of the third side wall far away from the word line.
5. The method of manufacturing a flash memory device as claimed in claim 4, wherein the source region and the drain region are formed by ion implantation process, respectively.
6. The method of manufacturing a flash memory device of claim 4, wherein a floating gate dielectric layer is further formed between the substrate and the floating gate material layer, and a tunneling dielectric layer is further formed between the floating gate material layer and the erase gate material layer.
7. The method of manufacturing a flash memory device of claim 6, wherein the floating gate dielectric layer and the tunneling dielectric layer are a stacked structure of a silicon oxide layer, a silicon nitride layer, or a combination thereof.
8. The method of manufacturing a flash memory device of claim 4, wherein the first sidewall, the second sidewall, the third sidewall, and the source line dielectric layer are silicon oxide layers.
9. The method of manufacturing a flash memory device of claim 1, wherein the hard mask layer is a silicon nitride layer.
10. The method of manufacturing a flash memory device of claim 1, wherein the flash memory device is a split gate memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310471124.7A CN116322051A (en) | 2023-04-27 | 2023-04-27 | Method for manufacturing flash memory device |
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| CN202310471124.7A CN116322051A (en) | 2023-04-27 | 2023-04-27 | Method for manufacturing flash memory device |
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