CN103187258B - The minimizing technology of silicon nitride layer in floating boom manufacture process - Google Patents
The minimizing technology of silicon nitride layer in floating boom manufacture process Download PDFInfo
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- CN103187258B CN103187258B CN201110456273.3A CN201110456273A CN103187258B CN 103187258 B CN103187258 B CN 103187258B CN 201110456273 A CN201110456273 A CN 201110456273A CN 103187258 B CN103187258 B CN 103187258B
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Abstract
The invention discloses the minimizing technology of silicon nitride layer in a kind of floating boom manufacture process, including: substrate is provided, described substrate comprises substrate and substrate is sequentially depositing silicon oxide layer and silicon nitride layer, and fleet plough groove isolation structure, described silicon nitride layer is separated at least one separate part by described fleet plough groove isolation structure；Remove partial nitridation silicon layer；Following step is repeated, until silicon nitride layer is all removed: the recess sidewall formed after removing partial nitridation silicon layer is carried out part removal, and again removes partial nitridation silicon layer.The groove structure formed by the method for the present invention, its cross section is the opening reverse trapezoid shape more than bottom width, this groove structure is in floating boom manufacturing process subsequently, wherein during deposit polycrystalline silicon, ensure that polysilicon is fully filled with whole groove, leave a void defect the most in a groove, it is ensured that prepared floating boom and the quality of memory element, ensure the reliability of memory element.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly to silicon nitride layer in a kind of floating boom manufacture process
Minimizing technology.
Background technology
Autoregistration floating boom (self align floating gate) is widely used in flash memory (flash memory)
In the manufacture process of the memory element of NOR flash memory.
The preparation method of a kind of floating boom of prior art includes procedure below:
As it is shown in figure 1, be sequentially depositing silicon oxide layer 2 and silicon nitride layer in wafer substrate 1 such as silicon substrate
3, shallow trench 4 is formed on substrate 1 by photoetching, this shallow trench 4 runs through silicon nitride layer 3 and silicon oxide
Layer 2, as shown in Figure 2.Continue cvd silicon oxide, form shallow trench isolation (STI) 5, such as Fig. 3 institute
Show.Shallow trench isolation 5 is carried out cmp (CMP) until expose silicon nitride layer 3 on surface,
Now silicon nitride layer 3 is divided into some absolute construction separated from one another, such as Fig. 4 institute by shallow trench isolation 5
Show.As it is shown in figure 5, remove silicon nitride layer 3, form several grooves 6.Deposit polycrystalline silicon is also changed
Learn mechanical lapping and form polysilicon 7 separated from one another as shown in Figure 6.After forming polysilicon, continue
Continuous each existing technical process subsequently being prepared floating boom, to form FGS floating gate structure.
In the manufacture process of above-mentioned prior art, refer to Fig. 4 to Fig. 6, silicon nitride layer 3 passes through dry method
Or the method for wet etching disposably removes, after the described silicon nitride layer 3 of removal forms groove 6, recessed
The A/F of groove 6 is less than slot bottom width, and when deposit polycrystalline silicon 7 in groove 6, polysilicon 7 is also
It is not easy to be fully filled with whole groove 6, and space easily occurs in groove 6, produce defect 8 (such as Fig. 6
Shown in), affect the preparation of floating boom, and then memory element hydraulic performance decline was even lost efficacy.
Summary of the invention
In view of this, the present invention provides the minimizing technology of silicon nitride layer in a kind of floating boom manufacture process, to protect
When card performs follow-up floating boom manufacture process craft after removing described silicon nitride layer, it is deposited on removal nitridation
Polysilicon in the groove that silicon layer is formed can be fully filled with whole groove, it is to avoid the generation of defect.
The technical scheme is that and be achieved in that:
The minimizing technology of silicon nitride layer in a kind of floating boom manufacture process, including:
There is provided substrate, described substrate comprises substrate and substrate is sequentially depositing silicon oxide layer and silicon nitride
Layer, and fleet plough groove isolation structure, described silicon nitride layer is separated at least by described fleet plough groove isolation structure
One separate part；
Remove partial nitridation silicon layer；
Following step is repeated, until silicon nitride layer is all removed:
The recess sidewall formed after removing partial nitridation silicon layer is carried out part removal, and again removes part
Silicon nitride layer.
Further, the slot opening width that described silicon nitride layer is formed after being all removed is more than groove-bottom
Portion's width.
Further, described groove cross section is inverted trapezoidal.
Further, removing partial nitridation silicon layer and use wet etch process, etching liquid is 160 DEG C of hot phosphoric acid,
To the rate of etch of silicon nitride it is
Etching period is 5min.
Further, recess sidewall carrying out part and removes employing wet etch process, etching liquid uses
HF∶H2O is the hydrofluoric acid solution of 1: 200, to the rate of etch of silicon oxide is
During etching
Between be 5～10min.
From such scheme it can be seen that the minimizing technology institute of silicon nitride layer the floating boom manufacture process of the present invention
The new method proposed, replaces the step of disposable removing silicon nitride layer in existing manufacture Floating-gate Technology, and it will
The removal process of silicon nitride layer uses the mode that multistep performs, and all removes the silicon nitride of part in each step
Layer, and in each step, after removing partial nitridation silicon layer, the sidewall of the groove formed is also carried out portion
Dividing and remove, therefore during performing each step, the width between the sidewall of groove is just widened, with
The increase of step, the silicon nitride layer often removing a part widens recess sidewall, such institute shape the most accordingly
The groove structure become, the width of its opening is just wider than the width of bottom portion of groove, treats to remove whole silicon nitride layers
Divided by rear, it is the opening reverse trapezoid shape more than bottom width that whole groove just defines cross section.This
The groove structure of shape is in floating boom manufacturing process subsequently, when deposit polycrystalline silicon wherein, it is possible to protect
Card polysilicon is fully filled with whole groove, leaves a void defect the most in a groove, it is ensured that prepared is floating
Grid and the quality of memory element, ensured the reliability of memory element.
Accompanying drawing explanation
Fig. 1 to Fig. 4 for prior art and the embodiment of the present invention prepare in floating boom method from provide substrate to
Shallow trench isolation is carried out device architecture evolution schematic diagram in chemical mechanical planarization process；
Fig. 5 and Fig. 6 is that prior art prepares silicon nitride layer and the deposit polycrystalline silicon process removed in floating boom method
Device architecture evolution schematic diagram；
Fig. 7 is the flow chart of the minimizing technology of silicon nitride layer in floating boom manufacture process of the present invention；
Fig. 8 to Figure 12 illustrates for device architecture evolution during using the inventive method to remove silicon nitride layer
Figure.
In accompanying drawing, the title corresponding to each label is as follows:
1, substrate, 2, silicon oxide layer, 3, silicon nitride layer, 4, shallow trench, 5, shallow trench isolation, 6,
Groove, 7, polysilicon, 8, defect
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearer, develop simultaneously referring to the drawings
Embodiment, is described in further detail the present invention.
The minimizing technology of silicon nitride layer in the floating boom manufacture process of the present invention, as it is shown in fig. 7, comprises:
There is provided substrate, described substrate comprises substrate and substrate is sequentially depositing silicon oxide layer and silicon nitride
Layer, and fleet plough groove isolation structure, described silicon nitride layer is separated at least by described fleet plough groove isolation structure
One separate part；
Remove partial nitridation silicon layer；
Following step is repeated, until silicon nitride layer is all removed:
The recess sidewall formed after removing partial nitridation silicon layer is carried out part removal, and again removes part
Silicon nitride layer.
In conjunction with floating boom manufacture process, the method for the present invention is further elaborated.
Referring to figs. 1 through Fig. 4, wafer substrate 1 such as silicon substrate is sequentially depositing silicon oxide layer 2 and nitridation
Silicon layer 3.Wherein, substrate 1 can comprise any can be as the basis building semiconductor device thereon
Material, such as silicon substrate.
Formed shallow trench 4 on substrate 1 by photoetching, this shallow trench 4 runs through silicon nitride layer 3 and oxidation
Silicon layer 2.Form the method for shallow trench 4 such as: coat photoresist at crystal column surface, photoresist is carried out
Expose and develop, predefined figure is transferred on photoresist, then with remaining photoresist as mask
Performing etching, part the most covered by photoresist on wafer is sequentially etched silicon nitride layer 3, silicon oxide
Layer 2 and section substrate 1, form shallow trench 4.The bottom of this shallow trench 4 is positioned in substrate 1.
In the substrate being formed after shallow trench 4, continue cvd silicon oxide, this silica-filled enter shallow ridges
Groove 4 is formed shallow trench isolation (STI) 5, and covers by above-mentioned photoetching process nitrogen separated from one another
SiClx layer 3.Afterwards, device surface is carried out cmp (CMP), be covered in institute to remove
State the silicon oxide on silicon nitride layer 3, until silicon nitride layer 3 exposing surface.
Said process is prior art, uses existing conventional method to realize, specific embodiment this
Place repeats no more.
With reference to Fig. 8 to Figure 12, the specific embodiment removing described silicon nitride layer 3 is as follows.
As shown in Figure 8, remove partial nitridation silicon layer 3, make the height of described silicon nitride layer 3 less than oxidation
The shallow trench isolation 5 of silicon, forms groove 6.Remove partial nitridation silicon layer 3 and use wet etch process, carve
Erosion liquid is 160 DEG C of hot phosphoric acid, to the rate of etch of silicon nitride is
Etching period is 5min.
As it is shown in figure 9, remove after partial nitridation silicon layer 3, to the sidewall of formed groove 6 part (i.e.
Shallow trench isolation 5 sidewall) silica material carry out part removal.Remove partial oxidation sidewall silicon material
Material uses wet etch process, and etching liquid uses HF: H2O (weight ratio) is the hydrofluoric acid solution of 1: 200,
To the rate of etch of silicon oxide it is
Etching period is 5～10min.
As shown in Figure 10, partial nitridation silicon layer 3 is again removed.This process and aforementioned removal partial silicon nitride
The technical process of layer 3 is identical, repeats no more.
As shown in figure 11, again to the sidewall of formed groove 6 part (i.e. the sidewall of shallow trench isolation 5)
Silica material carry out part removal.The technical process phase of this process and aforementioned removal partial sidewall material
With, repeat no more.
Above-mentioned removal partial nitridation silicon layer 3 and the process of partial sidewall are repeated.
As shown in figure 12, last remaining silicon nitride layer 3 is removed.This process and aforementioned removal partial nitridation
The technical process of silicon layer 3 is identical, repeats no more.
Through above-mentioned removal partial nitridation silicon layer 3 and to groove 6 sidewall formed after removing silicon nitride layer 3
After carrying out the repetitive process of part removal, the groove 6 formed be in a kind of reverse trapezoid shape (groove 6
A/F is more than slot bottom width).This reverse trapezoid shape ensures in floating boom manufacturing process subsequently, polycrystalline
Silicon can be deposited in this groove 6 fully, it is to avoid defect as shown in Figure 6 occurs, improves institute
The floating boom supported and the stability of device, thus ensured the reliability of memory element.Said process
Final step, for removing silicon nitride layer 3 (as shown in figure 12), is no longer removed after removing silicon nitride layer 3
The silica material of partial sidewall, although can be formed as shown in figure 12 after removing described silicon nitride layer 3
A/F near bottom portion of groove part is slightly smaller than groove slot bottom width, but can't have influence on subsequently
Polysilicon deposition and floating boom manufacture process afterwards.
Polysilicon deposition subsequently and floating boom manufacture process afterwards all can use existing known floating boom system
Making step to carry out, here is omitted.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all at this
Within the spirit of invention and principle, any modification, equivalent substitution and improvement etc. done, should be included in
Within the scope of protection of the invention.
Claims (2)
1. a minimizing technology for silicon nitride layer in floating boom manufacture process, including:
There is provided substrate, described substrate comprises substrate and substrate is sequentially depositing silicon oxide layer and silicon nitride
Layer, and fleet plough groove isolation structure, described silicon nitride layer is separated at least by described fleet plough groove isolation structure
One separate part；
Remove partial nitridation silicon layer；
Following step is repeated, until silicon nitride layer is all removed:
The recess sidewall formed after removing partial nitridation silicon layer is carried out part removal, and again removes part
Silicon nitride layer；
And then, the slot opening width that described silicon nitride layer is formed after being all removed is more than bottom portion of groove
Width；Wherein,
Removing partial nitridation silicon layer and use wet etch process, etching liquid is hot phosphoric acid；
Recess sidewall carrying out part and removes employing wet etch process, etching liquid uses hydrofluoric acid solution；
Wherein,
Described hot phosphoric acid Temperature is 160 DEG C, to the rate of etch of silicon nitride isEtching period
For 5min；
HF:H in described hydrofluoric acid solution2The weight ratio of O is 1:200, to the rate of etch of silicon oxide isEtching period is 5～10min.
The minimizing technology of silicon nitride layer in floating boom manufacture process the most according to claim 1, it is special
Levy and be: described groove cross section is inverted trapezoidal.
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| CN103943478A (en) * | 2014-04-03 | 2014-07-23 | 武汉新芯集成电路制造有限公司 | Method for manufacturing floating gate structure |
| CN103943549B (en) * | 2014-04-28 | 2016-08-17 | 上海华力微电子有限公司 | A kind of shallow trench oxide cavity and the removing method of floating gate polysilicon concave point |
| CN105470201A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Flash memory device process for simultaneously improving shallow trench isolation (STI) filling holes and floating gate polycrystalline silicon (FG Poly) filling holes |
| CN105336696A (en) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | Method for improving STI and FG poly filling hole process window simultaneously |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN106469730B (en) * | 2015-08-18 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor structure |
| CN106298678A (en) * | 2016-08-22 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method for improving of the control gate coefficient of coup |
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| CN110610856A (en) * | 2019-09-20 | 2019-12-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113223996A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | ETOX structure flash memory floating gate filling method and flash memory thereof |
| CN113808930A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
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