CN115579401A - Semiconductor dielectric layer structure and manufacturing method - Google Patents
Semiconductor dielectric layer structure and manufacturing method Download PDFInfo
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- CN115579401A CN115579401A CN202211399824.1A CN202211399824A CN115579401A CN 115579401 A CN115579401 A CN 115579401A CN 202211399824 A CN202211399824 A CN 202211399824A CN 115579401 A CN115579401 A CN 115579401A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000003647 oxidation Effects 0.000 claims abstract description 63
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 50
- 238000011065 in-situ storage Methods 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 36
- 230000008021 deposition Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 230000009471 action Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The invention discloses a semiconductor dielectric layer structure and a manufacturing method thereof. The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, a first deposition oxidation layer is arranged on the surface of the silicon nitride layer, a second deposition oxidation layer is arranged on the surface of the first deposition oxidation layer, a part of the second deposition oxidation layer, the silicon nitride layer and the thermal oxidation layer are hollowed to form a contact hole, the bottom end in the contact hole extends to the surface of the epitaxial layer, the bottom end edge in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon, the gate oxidation layer on the inner wall of the grooves is exposed, and the second deposition oxidation layer and the gate oxidation layer jointly form a side wall structure of the in-situ doped polycrystalline silicon. The invention can avoid exposing the sharp corner of the semiconductor interface due to the etching of the contact hole.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor dielectric layer structure and a manufacturing method thereof.
Background
The reason why the schottky barrier lowering is formed is: the charge in the semiconductor causes an induced charge on one side of the schottky metal. If electrons are present in the semiconductor, the schottky metal induces a positive charge. Whereby the electrons form a mirror image directed towards the metal. The combined action of the electric field and the image force reduces the Schottky barrier. The larger the electric field, the more the schottky barrier is lowered. The reverse leakage current and the Schottky barrier height are in an exponential relationship, and the reverse leakage current is exponentially increased along with the reduction of the Schottky barrier.
At present, the trench MOS Schottky is etched in a contact hole, and in order to ensure that an oxide layer is etched cleanly, over-etching is inevitably caused to a gate oxide layer, so that a sharp corner of a semiconductor interface is exposed, as shown in figure 1. The schottky barrier is formed by etching completely the exposed semiconductor interface. It is conceivable that the schottky barrier interface necessarily also presents sharp corners. Such sharp corners will form electric field spikes when a reverse voltage is applied. The formation of the electric field spike will cause a rapid increase in leakage current at the sharp corner under the schottky barrier lowering effect described above. How to avoid or reduce the influence of sharp corners is always a problem to be solved in the design and production manufacturing process of the trench MOS schottky. Shown in FIG. 1: 1 denotes a thermal oxide layer masking the trench etch, 2 denotes an epitaxial layer, 3 denotes a gate oxide layer, 4 denotes an in-situ doped polysilicon layer, and 5 denotes a deposited oxide layer.
Disclosure of Invention
The embodiment of the invention provides a semiconductor dielectric layer structure and a manufacturing method thereof, aiming at solving the problem of sharp corner in the conventional Schottky barrier interface.
The invention provides a semiconductor medium layer structure which comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, the filling height of the polycrystalline silicon in the grooves is within the range of 200-400 nm above a semiconductor interface, a first deposited oxidation layer is arranged on the surface of the silicon nitride layer, a second deposited oxidation layer is arranged on the surface of the first deposited oxidation layer, the second deposited oxidation layer, the silicon nitride layer and a part of the thermal oxidation layer are hollowed to form a contact hole, the first deposited oxidation layer is attached to the side wall of the contact hole, the bottom end in the contact hole extends to the surface of the epitaxial layer to expose the epitaxial layer, the bottom end edge in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer on the inner wall of the grooves, and the second deposited oxidation layer and the gate oxidation layer together form a side wall structure of the in-situ doped polycrystalline silicon.
Further, the thickness of the thermal oxidation layer is 27-33 nm.
Further, the thickness of the silicon nitride layer is not less than 500nm.
Further, the thickness of the first deposited oxide layer is 360-440 nm.
Further, the thickness of the second deposited oxide layer is 180-220 nm.
In another aspect, the present application further provides a method for manufacturing a semiconductor dielectric layer structure as described in any one of the above, where the method includes:
growing a thermal oxidation layer on an epitaxial layer of a semiconductor, and depositing a silicon nitride layer on the surface of the thermal oxidation layer;
etching a window of a groove on the thermal oxidation layer and the silicon nitride layer through an etching process;
etching grooves on the epitaxial layer by using the window, and generating a thermal oxidation layer on the inner wall of each groove to serve as a gate oxidation layer;
depositing in-situ doped polysilicon, and etching back to make the in-situ doped polysilicon interface fall in the range of 200-400 nm above the semiconductor interface;
depositing the silicon nitride layer and the surface of the in-situ doped polysilicon after the back etching is finished to generate a first deposited oxide layer;
sixthly, photoresist coating and photoetching are carried out on the surface of the first deposition oxide layer, and the formed photoresist pattern is used as a masking layer for etching the contact hole;
seventhly, etching the first deposited oxide layer at the corresponding position by dry etching based on the photoresist pattern until the silicon nitride layer and the in-situ doped polysilicon are exposed to form a contact hole;
step eight, removing the photoresist, and corroding the exposed silicon nitride layer in the contact hole until the exposed silicon nitride layer in the contact hole is corroded cleanly;
ninthly, depositing on the surfaces of the in-situ doped polycrystalline silicon exposed in the first deposited oxide layer and the contact hole to generate a second deposited oxide layer;
and step ten, etching the second deposited oxide layer, controlling the etching amount to be 330 +/-30 nm, and forming the in-situ doped polycrystalline silicon side wall structure by the second deposited oxide layer and the gate oxide layer which are remained after etching to obtain the semiconductor dielectric layer structure.
Further, the etching the first deposited oxide layer at the corresponding position by dry etching until the silicon nitride layer and the in-situ doped polysilicon are exposed further includes:
and carrying out wet etching on the first deposited oxide layer until the first deposited oxide layer in the contact hole is completely etched.
And further, etching the exposed silicon nitride layer in the contact hole by wet etching.
Further, wet etching is carried out on the silicon nitride layer exposed in the contact hole through phosphoric acid.
And further, etching the second deposited oxide layer by dry etching.
The embodiment of the invention provides a semiconductor dielectric layer structure and a manufacturing method thereof. The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, the filling height of the polycrystalline silicon in the grooves is within the range of 200-400 nm above a semiconductor interface, a first deposited oxidation layer is arranged on the surface of the silicon nitride layer, a second deposited oxidation layer is arranged on the surface of the first deposited oxidation layer, a part of the second deposited oxidation layer, the silicon nitride layer and the thermal oxidation layer are hollowed to form a contact hole, a first deposited oxidation layer is attached to the side wall of the contact hole, the bottom end in the contact hole extends to the surface of the epitaxial layer to expose the epitaxial layer, the bottom end edge in the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer on the inner wall of the grooves, and the second deposited oxidation layer and the gate oxidation layer form a side wall structure of the in-situ doped polycrystalline silicon. Compared with the prior art, the semiconductor medium layer structure of this application, a part fretwork based on second deposit oxide layer and silicon nitride layer and thermal oxidation layer forms the contact hole, bottom in the contact hole extends to epitaxial layer surface, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon, expose the gate oxide of slot inner wall, second deposit oxide and gate oxide form the side wall structure of normal position doping polycrystalline silicon jointly, it comes to avoid the closed angle at semiconductor interface to expose because of the contact hole sculpture, thereby make the closed angle can not appear at schottky barrier interface, reduce the influence that schottky barrier reduces.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic diagram of a semiconductor dielectric layer structure with sharp corners in the prior art;
fig. 2 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 10 is a schematic structural diagram illustrating a method for fabricating a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 11 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 12 is a schematic structural diagram of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the invention;
fig. 13 is a schematic structural diagram of a semiconductor dielectric layer structure according to an embodiment of the invention.
The figure is as follows: 1. an epitaxial layer; 2. a thermal oxidation layer; 3. a silicon nitride layer; 4. a gate oxide layer; 5. in-situ doping polycrystalline silicon; 6. a first deposition oxide layer; 7. photoresist; 8. and secondly, depositing an oxide layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As shown in fig. 1, an embodiment of the present invention provides a semiconductor dielectric layer structure, which includes a semiconductor substrate, an epitaxial layer 1 is disposed on a surface of the semiconductor substrate, the epitaxial layer 1 is provided with a plurality of trenches, a thermal oxide layer 2 is disposed on a surface of the epitaxial layer 1, in-situ doped polysilicon 5 is filled in the trenches, a gate oxide layer 4 is formed between the in-situ doped polysilicon 5 and the trenches, a silicon nitride layer 3 is disposed on a surface of the thermal oxide layer 2 adjacent to the trenches, a filling height of the polysilicon in the trenches is within a range of 200 to 400nm above a semiconductor interface, a first deposited oxide layer 6 is disposed on a surface of the silicon nitride layer 3, a second deposited oxide layer 8 is disposed on a surface of the first deposited oxide layer 6, the second deposited oxide layer 8 and a portion of the silicon nitride layer 3 and the thermal oxide layer 2 form contact holes, first deposited oxide layers 6 are attached to sidewalls of the contact holes, bottom ends in the contact holes extend to the surface of the epitaxial layer 1 to expose the epitaxial layer 1, and bottom ends in the contact holes extend to the in-situ doped polysilicon 5 to expose the gate oxide layer 4 on the inner walls of the trenches, and the second deposited oxide layer 8 and the gate oxide layer 4 together form an in-situ doped polysilicon 5 structure. Compared with the prior art, the semiconductor medium layer structure of this application forms the contact hole based on the partial fretwork of second deposit oxide layer 8 and silicon nitride layer 3 and thermal oxidation layer 2, bottom in the contact hole extends to epitaxial layer 1 surface, and bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 5, expose trench inner wall's gate oxide 4, second deposit oxide layer and gate oxide 4 form normal position doping polycrystalline silicon 5's side wall structure jointly, the closed angle of having avoided semiconductor interface is because of the contact hole sculpture naked exposure, thereby make the closed angle can not appear in schottky barrier interface, reduce the influence that schottky barrier reduces.
In one embodiment, the thermal oxide layer 2 has a thickness of 27 to 33nm, the silicon nitride layer 3 has a thickness of not less than 500nm, the first deposited oxide layer 6 has a thickness of 360 to 440nm, and the second deposited oxide layer 8 has a thickness of 180 to 220nm.
Fig. 2 is a schematic flow chart of a method for manufacturing the semiconductor dielectric layer structure according to an embodiment of the present invention.
Step one, growing a thermal oxidation layer 2 with the thickness of 27-33 nm on an epitaxial layer 1 of a semiconductor; then, a silicon nitride layer 3 with a thickness of 760 to 840nm is deposited on the surface of the thermal oxide layer 2, as shown in FIG. 2.
And step two, as shown in fig. 3, etching windows of the grooves on the thermal oxidation layer 2 and the silicon nitride layer 3 through an etching process to be used as masking layers for subsequently etching the grooves.
Step three, as shown in fig. 4, a groove is etched on the epitaxial layer 1 by using the window; as shown in fig. 5, a thermal oxide layer 2 is formed on the inner wall of each trench as a gate oxide layer 4. When the groove is etched, the silicon nitride has a certain loss, but the thickness of the silicon nitride is ensured to be more than 500nm. The control of the remaining thickness of silicon nitride can be achieved by changing its deposition thickness or adjusting the trench etch recipe to improve the selectivity.
Step four, as shown in fig. 6, the in-situ doped polysilicon 5 is deposited and etched back, and the interface of the in-situ doped polysilicon 5 after etching back is controlled within the range of 200-400 nm above the semiconductor interface. Wherein the semiconductor interface refers to the top of the epitaxial layer.
And step five, as shown in fig. 7, depositing on the surface of the silicon nitride layer 3 and the in-situ doped polysilicon 5 after the etching back is finished to generate a first deposited oxide layer 6 with the thickness of 360-440 nm.
And step six, as shown in fig. 8, coating and photoetching a photoresist 7 on the surface of the first deposition oxide layer 6, and taking the formed photoresist 7 as a masking layer for etching the contact hole.
And seventhly, as shown in fig. 9, etching the first deposited oxide layer 6 at the corresponding position by dry etching based on the photoresist 7 pattern until the silicon nitride layer 3 and the in-situ doped polysilicon 5 are exposed, and forming a contact hole. It is to be understood that the loss of the silicon nitride layer 3 and the in-situ doped polysilicon 5 in this step is negligible. After the dry etching, the wet etching time of the first deposited oxide layer 6 can be increased by a small amount, so as to ensure that the first deposited oxide layer 6 in the contact hole is etched cleanly.
Step eight, as shown in fig. 10, the photoresist 7 is removed; as shown in fig. 11, wet etching is performed by using phosphoric acid to etch the exposed silicon nitride layer 3 in the contact hole until the exposed silicon nitride layer 3 in the contact hole is completely etched. The wet etch in this step has negligible loss to the first deposited oxide layer 6 and the in situ doped polysilicon 5.
Step nine, as shown in fig. 12, depositing is performed on the surface of the exposed in-situ doped polysilicon 5 in the first deposited oxide layer 6 and the contact hole, and a second deposited oxide layer 8 with the thickness of 180-220 nm is generated.
Step ten, as shown in fig. 13, the second deposited oxide layer 8 is etched, the etching amount is controlled to be 330 +/-30 nm, and the second deposited oxide layer 8 and the gate oxide layer 4 which are left after etching jointly form a side wall structure of the in-situ doped polysilicon 5, so that a semiconductor medium layer structure is obtained. As can be seen from fig. 13, the resulting semiconductor interface has no sharp corners.
The utility model discloses a semiconductor medium layer structure, partly fretwork based on second deposit oxide layer 8 and silicon nitride layer 3 and thermal oxide layer 2 forms the contact hole, bottom in the contact hole extends to epitaxial layer 1 surface, and bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 5, expose trench inner wall's gate oxide 4, second deposit oxide layer and gate oxide 4 form normal position doping polycrystalline silicon 5's side wall structure jointly, the closed angle of having avoided the semiconductor interface is because of the contact hole sculpture exposes, thereby make the closed angle can not appear in schottky barrier interface, reduce the influence that schottky barrier reduces.
The embodiments are described in a progressive mode in the specification, the emphasis of each embodiment is on the difference from the other embodiments, and the same and similar parts among the embodiments can be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
It should also be noted that, in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion.
It should be noted that the present invention is not limited to the particular embodiments described herein, and that the present invention includes all embodiments that are within the scope of the present invention. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. The semiconductor medium layer structure is characterized by comprising a semiconductor substrate, wherein an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, the filling height of the polycrystalline silicon in the grooves is within the range of 200-400 nm above a semiconductor interface, a first deposited oxidation layer is arranged on the surface of the silicon nitride layer, a second deposited oxidation layer is arranged on the surface of the first deposited oxidation layer, the second deposited oxidation layer, the silicon nitride layer and a part of the thermal oxidation layer are hollowed to form a contact hole, the side wall of the contact hole is attached with the first deposited oxidation layer, the bottom in the contact hole extends to the surface of the epitaxial layer, the epitaxial layer is exposed, the bottom edge in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon, the gate oxidation layer is exposed out of the inner wall of the groove, and the second deposited oxidation layer and the gate oxidation layer form the structure of the in-situ doped polycrystalline silicon.
2. The semiconductor dielectric layer structure of claim 1, wherein the thermal oxide layer has a thickness of 27-33 nm.
3. The semiconductor dielectric layer structure of claim 1, wherein the silicon nitride layer has a thickness of not less than 500nm.
4. The semiconductor dielectric layer structure of claim 1 wherein the first deposited oxide layer has a thickness of 360 to 440nm.
5. The semiconductor dielectric layer structure of claim 1 wherein the thickness of the second deposited oxide layer is 180-220 nm.
6. A method for fabricating a semiconductor dielectric layer structure according to any one of claims 1 to 5, wherein the method for fabricating comprises:
growing a thermal oxidation layer on an epitaxial layer of a semiconductor, and depositing a silicon nitride layer on the surface of the thermal oxidation layer;
etching a window of a groove on the thermal oxidation layer and the silicon nitride layer through an etching process;
etching grooves on the epitaxial layer by using the window, and generating a thermal oxidation layer on the inner wall of each groove to serve as a gate oxidation layer;
depositing in-situ doped polysilicon, and etching back to make the in-situ doped polysilicon interface fall in the range of 200-400 nm above the semiconductor interface;
depositing the silicon nitride layer and the surface of the in-situ doped polysilicon after the back etching is finished to generate a first deposited oxide layer;
sixthly, photoresist coating and photoetching are carried out on the surface of the first deposition oxide layer, and the formed photoresist pattern is used as a masking layer for etching the contact hole;
seventhly, etching the first deposited oxide layer at the corresponding position by dry etching based on the photoresist pattern until the silicon nitride layer and the in-situ doped polysilicon are exposed to form a contact hole;
step eight, removing the photoresist, and corroding the silicon nitride layer exposed in the contact hole until the silicon nitride layer exposed in the contact hole is corroded cleanly;
step nine, depositing on the surfaces of the exposed in-situ doped polysilicon in the first deposited oxide layer and the contact hole to generate a second deposited oxide layer;
and step ten, etching the second deposited oxide layer, controlling the etching amount to be 330 +/-30 nm, and forming the in-situ doped polycrystalline silicon side wall structure by the second deposited oxide layer and the gate oxide layer which are remained after etching to obtain the semiconductor dielectric layer structure.
7. The method for manufacturing the semiconductor dielectric layer structure according to claim 6, wherein the etching the first deposited oxide layer at the corresponding position by dry etching until the silicon nitride layer and the in-situ doped polysilicon are exposed further comprises:
and carrying out wet etching on the first deposited oxide layer until the first deposited oxide layer in the contact hole is completely etched.
8. The method of claim 6, wherein the silicon nitride layer exposed in the contact hole is etched by wet etching.
9. The method of claim 8, wherein the exposed silicon nitride layer in the contact hole is wet etched with phosphoric acid.
10. The method of claim 6, wherein the second deposited oxide layer is etched by dry etching.
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