CN218585993U - Semiconductor dielectric layer structure - Google Patents

Abstract

The utility model discloses a semiconductor dielectric layer structure. The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, a first deposition oxidation layer is arranged on the surface of the silicon nitride layer, a second deposition oxidation layer is arranged on the surface of the first deposition oxidation layer, a part of the second deposition oxidation layer, the silicon nitride layer and the thermal oxidation layer are hollowed to form a contact hole, the bottom end in the contact hole extends to the surface of the epitaxial layer, the bottom end edge in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon, the gate oxidation layer of the inner wall of the grooves is exposed, and the second deposition oxidation layer and the gate oxidation layer jointly form a side wall structure of the in-situ doped polycrystalline silicon. The utility model discloses can avoid the closed angle at semiconductor interface to expose because of the contact hole sculpture.

Description

Semiconductor dielectric layer structure

Technical Field

The utility model relates to a semiconductor device technical field especially relates to a semiconductor medium layer structure.

Background

The reason for the schottky barrier lowering is that: the charge in the semiconductor causes an induced charge on one side of the schottky metal. If electrons are present in the semiconductor, the schottky metal induces a positive charge. Whereby the electrons form a mirror image directed towards the metal. The combined action of the electric field and the image force reduces the Schottky barrier. The larger the electric field, the more the schottky barrier is lowered. The reverse leakage current and the Schottky barrier height are in an exponential relationship, and the reverse leakage current is exponentially increased along with the reduction of the Schottky barrier.

At present, the trench MOS Schottky is etched in a contact hole, and in order to ensure that an oxide layer is etched cleanly, over-etching is inevitably caused to a gate oxide layer, so that a sharp corner of a semiconductor interface is exposed, as shown in figure 1. The schottky barrier is formed by etching completely the exposed semiconductor interface. It is conceivable that the schottky barrier interface will necessarily also exhibit sharp corners. Such sharp corners will form electric field spikes when a reverse voltage is applied. The formation of the electric field spike will cause a rapid increase in leakage current at the sharp corner under the schottky barrier lowering effect described above. How to avoid or reduce the influence of sharp corners is always a problem to be solved in the design and production manufacturing process of the trench MOS schottky. Shown in FIG. 1: 1 denotes a thermal oxide layer masking the trench etch, 2 denotes an epitaxial layer, 3 denotes a gate oxide layer, 4 denotes an in-situ doped polysilicon layer, and 5 denotes a deposited oxide layer.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a semiconductor dielectric layer structure aims at solving the problem that has the closed angle in the current schottky barrier interface.

The utility model provides a semiconductor medium layer structure, semiconductor medium layer structure includes the semiconductor substrate, the semiconductor substrate surface is equipped with the epitaxial layer, the epitaxial layer is equipped with a plurality of slots, the epitaxial layer surface is equipped with thermal oxidation layer, the slot intussuseption is filled with normal position doping polycrystalline silicon, be formed with gate oxide layer between normal position doping polycrystalline silicon and the slot, the adjacent thermal oxidation layer surface of slot is equipped with silicon nitride layer, the packing height of ditch inslot polycrystalline silicon falls in the 200 ~ 400nm within range of semiconductor interface top, silicon nitride layer surface is equipped with first deposition oxide layer, first deposition oxide layer surface is equipped with second deposition oxide layer, second deposition oxide layer and silicon nitride layer and a part fretwork of thermal oxidation layer forms the contact hole, the contact hole lateral wall adheres to first deposition oxide layer, bottom in the contact hole extends to epitaxial layer surface makes the epitaxial layer exposes, just bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon exposes trench inner wall's gate oxide layer, second deposition oxide layer and gate oxide layer form jointly the structure of normal position doping polycrystalline silicon.

Further, the thickness of the thermal oxidation layer is 27-33 nm.

Further, the thickness of the silicon nitride layer is not less than 500nm.

Further, the thickness of the first deposited oxide layer is 360-440 nm.

Further, the thickness of the second deposited oxide layer is 180-220 nm.

The embodiment of the utility model provides a semiconductor dielectric layer structure. The semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, the filling height of the polycrystalline silicon in the grooves is within the range of 200-400 nm above a semiconductor interface, a first deposited oxidation layer is arranged on the surface of the silicon nitride layer, a second deposited oxidation layer is arranged on the surface of the first deposited oxidation layer, a part of the second deposited oxidation layer, the silicon nitride layer and the thermal oxidation layer are hollowed to form a contact hole, a first deposited oxidation layer is attached to the side wall of the contact hole, the bottom end in the contact hole extends to the surface of the epitaxial layer to expose the epitaxial layer, the bottom end edge in the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer on the inner wall of the grooves, and the second deposited oxidation layer and the gate oxidation layer form a side wall structure of the in-situ doped polycrystalline silicon. Compared with the prior art, the semiconductor medium layer structure of this application, a part fretwork based on second deposit oxide layer and silicon nitride layer and thermal oxidation layer forms the contact hole, bottom in the contact hole extends to epitaxial layer surface, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon, expose the gate oxide of slot inner wall, second deposit oxide and gate oxide form the side wall structure of normal position doping polycrystalline silicon jointly, it comes to avoid the closed angle at semiconductor interface to expose because of the contact hole sculpture, thereby make the closed angle can not appear at schottky barrier interface, reduce the influence that schottky barrier reduces.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic diagram of a semiconductor dielectric layer structure with sharp corners in the prior art;

fig. 2 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to the present invention;

fig. 3 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to the present invention;

fig. 10 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of an embodiment of a method for manufacturing a semiconductor dielectric layer structure according to the present invention;

fig. 13 is a schematic structural diagram of a semiconductor dielectric layer structure according to an embodiment of the present invention.

The figure is as follows: 1. an epitaxial layer; 2. a thermal oxidation layer; 3. a silicon nitride layer; 4. a gate oxide layer; 5. in-situ doping polycrystalline silicon; 6. a first deposition oxide layer; 7. photoresist; 8. and secondly, depositing an oxide layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As shown in fig. 1, the embodiment of the utility model provides a semiconductor medium layer structure, semiconductor medium layer structure includes the semiconductor substrate, the semiconductor substrate surface is equipped with epitaxial layer 1, epitaxial layer 1 is equipped with a plurality of slots, epitaxial layer 1 surface is equipped with thermal oxidation layer 2, the slot intussuseption is filled with normal position doping polycrystalline silicon 5, be formed with gate oxide 4 between normal position doping polycrystalline silicon 5 and the slot, the adjacent thermal oxidation layer 2 surface of slot is equipped with silicon nitride layer 3, the packing height of polycrystalline silicon falls in 200 ~ 400nm within range above the semiconductor interface in the slot, silicon nitride layer 3 surface is equipped with first deposition oxide layer 6, first deposition oxide layer 6 surface is equipped with second deposition oxide layer 8, second deposition oxide layer 8 and silicon nitride layer 3 and thermal oxidation layer 2's partly fretwork form the contact hole, the contact hole lateral wall adheres to first deposition oxide layer 6, bottom in the contact hole extends to epitaxial layer 1 surface, make epitaxial layer 1 expose, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 5, expose trench inner wall's gate oxide 4, second deposition oxide layer 8 and gate oxide 4 form the gate oxide structure of normal position doping polycrystalline silicon 5 jointly. Compared with the prior art, the semiconductor medium layer structure of this application forms the contact hole based on second deposit oxide layer 8 and silicon nitride layer 3 and thermal oxide layer 2's partly fretwork, bottom in the contact hole extends to epitaxial layer 1 surface, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 5, expose trench inner wall's gate oxide 4, second deposit oxide layer and gate oxide 4 form the side wall structure of normal position doping polycrystalline silicon 5 jointly, the closed angle of having avoided semiconductor interface is because of contact hole sculpture and the naked exposure comes, thereby make the closed angle can not appear at schottky barrier interface, reduce the influence that schottky barrier reduces.

In one embodiment, the thermal oxide layer 2 has a thickness of 27 to 33nm, the silicon nitride layer 3 has a thickness of not less than 500nm, the first deposited oxide layer 6 has a thickness of 360 to 440nm, and the second deposited oxide layer 8 has a thickness of 180 to 220nm.

Fig. 2 is a schematic flow chart of a method for manufacturing the semiconductor dielectric layer structure according to an embodiment of the present invention.

Step one, growing a thermal oxidation layer 2 with the thickness of 27-33 nm on an epitaxial layer 1 of a semiconductor; then, a silicon nitride layer 3 with a thickness of 760 to 840nm is deposited on the surface of the thermal oxide layer 2, as shown in FIG. 2.

And step two, as shown in fig. 3, etching windows of the grooves on the thermal oxidation layer 2 and the silicon nitride layer 3 through an etching process to be used as masking layers for subsequent groove etching.

Step three, as shown in fig. 4, a groove is etched on the epitaxial layer 1 by using the window; as shown in fig. 5, a thermal oxide layer 2 is formed on the inner wall of each trench as a gate oxide layer 4. When the groove is etched, silicon nitride has certain loss, but the thickness of the silicon nitride is ensured to be more than 500nm. The control of the remaining thickness of silicon nitride can be achieved by changing its deposition thickness or adjusting the trench etch recipe to improve the selectivity.

And step four, as shown in fig. 6, depositing the in-situ doped polysilicon 5, and etching back the in-situ doped polysilicon 5, wherein the interface of the in-situ doped polysilicon 5 after etching back is controlled within the range of 200-400 nm above the semiconductor interface. Wherein the semiconductor interface refers to the top of the epitaxial layer.

And step five, as shown in fig. 7, depositing on the surface of the silicon nitride layer 3 and the in-situ doped polysilicon 5 after the etching back is finished to generate a first deposited oxide layer 6 with the thickness of 360-440 nm.

And step six, as shown in fig. 8, coating and photoetching the photoresist 7 on the surface of the first deposition oxide layer 6, and using the formed photoresist 7 as a masking layer for etching the contact hole.

And seventhly, as shown in fig. 9, etching the first deposited oxide layer 6 at the corresponding position by dry etching based on the photoresist 7 pattern until the silicon nitride layer 3 and the in-situ doped polysilicon 5 are exposed, and forming a contact hole. It is to be understood that the loss of the silicon nitride layer 3 and the in-situ doped polysilicon 5 in this step is negligible. After the dry etching, the wet etching time of the first deposited oxide layer 6 can be increased by a small amount, so as to ensure that the first deposited oxide layer 6 in the contact hole is etched cleanly.

Step eight, as shown in fig. 10, the photoresist 7 is removed; as shown in fig. 11, the exposed silicon nitride layer 3 in the contact hole is etched by wet etching with phosphoric acid until the exposed silicon nitride layer 3 in the contact hole is completely etched. The wet etch in this step has negligible loss to the first deposited oxide layer 6 and the in situ doped polysilicon 5.

Step nine, as shown in fig. 12, depositing is performed on the first deposited oxide layer 6 and the surface of the exposed in-situ doped polysilicon 5 in the contact hole, so as to generate a second deposited oxide layer 8 with a thickness of 180-220 nm.

Tenthly, as shown in fig. 13, etching the second deposited oxide layer 8, controlling the etching amount to be 330 +/-30 nm, and forming a side wall structure of the in-situ doped polycrystalline silicon 5 by the second deposited oxide layer 8 and the gate oxide layer 4 which are remained after etching together to obtain the semiconductor medium layer structure. As can be seen from fig. 13, the resulting semiconductor interface has no sharp corners.

The utility model discloses a semiconductor medium layer structure, partly fretwork based on second deposit oxide layer 8 and silicon nitride layer 3 and thermal oxide layer 2 forms the contact hole, bottom in the contact hole extends to epitaxial layer 1 surface, and the bottom edge in the contact hole bottom extends to normal position doping polycrystalline silicon 5, expose trench inner wall's gate oxide 4, second deposit oxide layer and gate oxide 4 form the side wall structure of normal position doping polycrystalline silicon 5 jointly, the closed angle of having avoided semiconductor interface is because of contact hole sculpture and the naked exposure comes, thereby make the closed angle can not appear in schottky barrier interface, reduce the influence that schottky barrier reduced.

The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the scope of the appended claims.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion.

It should be noted that the present invention is not limited to the particular embodiments described herein, and that the present invention includes all embodiments that are within the scope of the present invention. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

Claims (5)

1. The semiconductor medium layer structure is characterized in that the semiconductor medium layer structure comprises a semiconductor substrate, an epitaxial layer is arranged on the surface of the semiconductor substrate, a plurality of grooves are formed in the epitaxial layer, a thermal oxidation layer is arranged on the surface of the epitaxial layer, in-situ doped polycrystalline silicon is filled in the grooves, a gate oxidation layer is formed between the in-situ doped polycrystalline silicon and the grooves, a silicon nitride layer is arranged on the surface of the thermal oxidation layer adjacent to the grooves, the filling height of the polycrystalline silicon in the grooves is within the range of 200-400 nm above a semiconductor interface, a first deposited oxidation layer is arranged on the surface of the silicon nitride layer, a second deposited oxidation layer is arranged on the surface of the first deposited oxidation layer, the second deposited oxidation layer, the silicon nitride layer and a part of the thermal oxidation layer are hollowed to form a contact hole, the first deposited oxidation layer is attached to the side wall of the contact hole, the bottom end in the contact hole extends to the surface of the epitaxial layer to expose the epitaxial layer, the bottom end edge in the bottom of the contact hole extends to the in-situ doped polycrystalline silicon to expose the gate oxidation layer of the groove, and the second deposited oxidation layer and the gate oxidation layer form a side wall structure of the in-situ doped polycrystalline silicon.

2. The semiconductor dielectric layer structure of claim 1, wherein the thermal oxide layer has a thickness of 27-33 nm.

3. The semiconductor dielectric layer structure of claim 1, wherein the silicon nitride layer has a thickness of not less than 500nm.

4. The semiconductor dielectric layer structure of claim 1 wherein the first deposited oxide layer has a thickness of 360 to 440nm.

5. The semiconductor dielectric layer structure of claim 1 wherein the thickness of the second deposited oxide layer is 180-220 nm.

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