TW201926437A - Method of manufacturing trench gate MOSFET - Google Patents
Method of manufacturing trench gate MOSFET Download PDFInfo
- Publication number
- TW201926437A TW201926437A TW106142745A TW106142745A TW201926437A TW 201926437 A TW201926437 A TW 201926437A TW 106142745 A TW106142745 A TW 106142745A TW 106142745 A TW106142745 A TW 106142745A TW 201926437 A TW201926437 A TW 201926437A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- dielectric constant
- trench
- low dielectric
- insulating layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002131 composite material Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 59
- 239000004020 conductor Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 21
- 230000005669 field effect Effects 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 230000003071 parasitic effect Effects 0.000 description 9
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
本發明是有關於一種電晶體的製造方法，且特別是有關於一種溝槽式閘極金氧半場效電晶體的製造方法。The present invention relates to a method of fabricating a transistor, and more particularly to a method of fabricating a trench gate MOS field effect transistor.
功率開關電晶體在電源管理領域已廣泛使用，理想的功率開關必須具有低寄生電容（parasitic capacitance）的特性，以確保功率開關電晶體的反應速度以提供良好的功率轉換效率。Power switching transistors have been widely used in power management. Ideal power switches must have low parasitic capacitance characteristics to ensure the power of the switching transistor to provide good power conversion efficiency.
在習知的功率開關電晶體結構中，溝槽電極結構包含在上部的閘電極（gate）與在下部的源電極（source)。在閘電極底面的兩側具有齒狀凸出，會縮短閘極與汲極（drain）之間的距離，導致閘極與汲極間的寄生電容（Qgd）增加，進而影響功率開關電晶體的切換速度。習知製程可藉由控制源電極的蝕刻高度以消除閘電極底面兩側的齒狀凸出結構，但源電極的蝕刻很難精確控制，導致製程成本增加且品質不穩定。In a conventional power switching transistor structure, the trench electrode structure includes a gate electrode at the upper portion and a source electrode at the lower portion. There are toothed protrusions on both sides of the bottom surface of the gate electrode, which shortens the distance between the gate and the drain, resulting in an increase in parasitic capacitance (Qgd) between the gate and the drain, thereby affecting the power switching transistor. Switch speed. The conventional process can eliminate the tooth-like convex structure on both sides of the bottom surface of the gate electrode by controlling the etching height of the source electrode, but the etching of the source electrode is difficult to precisely control, resulting in an increase in process cost and unstable quality.
因此，如何不增加製程成本，且能穩定製造低閘極-汲極間寄生電容的功率開關電晶體，為業界亟欲改善的問題。Therefore, how to increase the manufacturing process cost and stabilize the power switching transistor with low gate-drain parasitic capacitance is an improvement problem in the industry.
本發明提供一種溝槽式閘極金氧半場效電晶體的製造方法，可利用現有的製程提供品質穩定的低寄生電容的溝槽式閘極金氧半場效電晶體。The invention provides a method for manufacturing a trench gate MOS field effect transistor, which can provide a trench gate MOSFET with low stability and low quality parasitic capacitance by using an existing process.
本發明提供一種溝槽式閘極金氧半場效電晶體的製造方法，其包括以下步驟。於基底上形成磊晶層。於磊晶層中形成溝槽。於溝槽的表面上順應性地形成複合介電層。於溝槽的下部填入第一導體層。於第一導體層上形成第一絕緣層。於形成第一絕緣層的步驟之後，移除部分複合介電層，以裸露出部分磊晶層。於溝槽內形成第二絕緣層，且第二絕緣層覆蓋第一絕緣層。於溝槽的上部形成第二導體層。The invention provides a method for manufacturing a trench gate MOS field effect transistor, which comprises the following steps. An epitaxial layer is formed on the substrate. A trench is formed in the epitaxial layer. A composite dielectric layer is conformally formed on the surface of the trench. A first conductor layer is filled in a lower portion of the trench. A first insulating layer is formed on the first conductor layer. After the step of forming the first insulating layer, a portion of the composite dielectric layer is removed to expose a portion of the epitaxial layer. A second insulating layer is formed in the trench, and the second insulating layer covers the first insulating layer. A second conductor layer is formed on an upper portion of the trench.
在本發明的一實施例中，所述第二絕緣層與第二導體層之間的界面實質上平滑。In an embodiment of the invention, the interface between the second insulating layer and the second conductor layer is substantially smooth.
在本發明的一實施例中，形成所述第二絕緣層的方法包括進行化學氣相沉積（CVD）製程。In an embodiment of the invention, a method of forming the second insulating layer includes performing a chemical vapor deposition (CVD) process.
在本發明的一實施例中，形成所述複合介電層的步驟包括於溝槽的表面上依序形成第一低介電常數層、高介電常數層以及第二低介電常數層。In an embodiment of the invention, the step of forming the composite dielectric layer includes sequentially forming a first low dielectric constant layer, a high dielectric constant layer, and a second low dielectric constant layer on a surface of the trench.
在本發明的一實施例中，所述第一低介電常數層以及第二低介電常數層的介電常數小於4，且所述高介電常數層的介電常數大於4。In an embodiment of the invention, the first low dielectric constant layer and the second low dielectric constant layer have a dielectric constant of less than 4, and the high dielectric constant layer has a dielectric constant greater than 4.
在本發明的一實施例中，所述第一低介電常數層與第二低介電常數層的材料各自包括氧化矽，且所述高介電常數層的材料包括氮化矽。In an embodiment of the invention, the materials of the first low dielectric constant layer and the second low dielectric constant layer each comprise yttrium oxide, and the material of the high dielectric constant layer comprises tantalum nitride.
在本發明的一實施例中，所述第二低介電常數層的厚度大於所述第一低介電常數層的厚度。In an embodiment of the invention, the thickness of the second low dielectric constant layer is greater than the thickness of the first low dielectric constant layer.
在本發明的一實施例中，形成所述第一低介電常數層的方法包括進行熱氧化製程，且形成所述第二低介電常數層的方法包括進行化學氣相沉積製程。In an embodiment of the invention, a method of forming the first low dielectric constant layer includes performing a thermal oxidation process, and a method of forming the second low dielectric constant layer includes performing a chemical vapor deposition process.
在本發明的一實施例中，於移除部分所述複合介電層之後，剩餘的所述高介電常數層凸出於相鄰的所述第一低介電常數層與所述第二低介電常數層。In an embodiment of the invention, after removing a portion of the composite dielectric layer, the remaining high dielectric constant layer protrudes from the adjacent first low dielectric constant layer and the second Low dielectric constant layer.
在本發明的一實施例中，於移除部分所述複合介電層之後，所述第一絕緣層的頂面高於剩餘的所述複合介電層的頂面。In an embodiment of the invention, after removing a portion of the composite dielectric layer, a top surface of the first insulating layer is higher than a top surface of the remaining composite dielectric layer.
基於所述，本發明的製造方法簡單、製程裕度寬，且可利用現有的製程輕易地製作出低閘極-汲極間寄生電容的溝槽式閘極金氧半場效電晶體。Based on the above, the manufacturing method of the present invention is simple, the process margin is wide, and a trench gate MOS field effect transistor having a low gate-drain parasitic capacitance can be easily fabricated using an existing process.
為讓本發明的所述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The features and advantages of the invention will be apparent from the description and appended claims.
圖1A至1H為依據本發明一實施例所繪示的一種溝槽式閘極金氧半場效電晶體的製造方法的剖面示意圖。1A to 1H are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to an embodiment of the invention.
請參照圖1A，於基底102上形成磊晶層104。在一實施例中，基底102為具有第一導電型的半導體基底，例如是N型重摻雜的矽基底。在一實施例中，磊晶層104為具有第一導電型的磊晶層，例如是N型輕摻雜的磊晶層，且其形成方法包括進行選擇性磊晶生長（selective epitaxy growth，SEG）製程。Referring to FIG. 1A, an epitaxial layer 104 is formed on the substrate 102. In one embodiment, substrate 102 is a semiconductor substrate having a first conductivity type, such as an N-type heavily doped germanium substrate. In one embodiment, the epitaxial layer 104 is an epitaxial layer having a first conductivity type, such as an N-type lightly doped epitaxial layer, and the formation method includes selective epitaxy growth (SEG). )Process.
接著，於磊晶層104中形成溝槽106。在一實施例中，於磊晶層104上形成罩幕層。接著，以罩幕層為罩幕進行蝕刻製程，以移除部分磊晶層104。然後，移除罩幕層。Next, a trench 106 is formed in the epitaxial layer 104. In one embodiment, a mask layer is formed on the epitaxial layer 104. Then, an etching process is performed with the mask layer as a mask to remove a portion of the epitaxial layer 104. Then, remove the mask layer.
請參照圖1B，於溝槽106的表面上形成複合介電層114。在一實施例中，形成複合介電層114的步驟包括於溝槽106的表面上依序形成第一低介電常數層108、高介電常數層110以及第二低介電常數層112。第一低介電常數層108以及第二低介電常數層112的介電常數例如是小於4，且高介電常數層110的介電常數例如是大於4、大於6或大於7。在一實施例中，第一低介電常數層108以及第二低介電常數層112的材料各自包括氧化矽，且高介電常數層110的材料包括氮化矽。Referring to FIG. 1B, a composite dielectric layer 114 is formed on the surface of the trench 106. In one embodiment, the step of forming the composite dielectric layer 114 includes sequentially forming a first low dielectric constant layer 108, a high dielectric constant layer 110, and a second low dielectric constant layer 112 on the surface of the trench 106. The dielectric constant of the first low dielectric constant layer 108 and the second low dielectric constant layer 112 is, for example, less than 4, and the dielectric constant of the high dielectric constant layer 110 is, for example, greater than 4, greater than 6, or greater than 7. In one embodiment, the materials of the first low dielectric constant layer 108 and the second low dielectric constant layer 112 each comprise yttrium oxide, and the material of the high dielectric constant layer 110 comprises tantalum nitride.
在一實施例中，形成第一低介電常數層108與第二低介電常數層112的方法包括進行熱氧化製程或化學氣相沉積（CVD）製程，形成高介電常數層110的方法包括進行化學氣相沉積製程。In one embodiment, the method of forming the first low dielectric constant layer 108 and the second low dielectric constant layer 112 includes performing a thermal oxidation process or a chemical vapor deposition (CVD) process to form the high dielectric constant layer 110 Including the chemical vapor deposition process.
在一實施例中，第一低介電常數層108以及第二低介電常數層112的材料均包括氧化矽，但其密度因其形成方式而有所不同。例如，當第一低介電常數層108由熱氧化製程所形成時，其結構較緊密，密度較高；而當第二低介電常數層112由化學氣相沉積製程所形成時，其結構較鬆散，密度較低。或者，當第一低介電常數層108以及第二低介電常數層112均由化學氣相沉積製程所形成時，第一低介電常數層108以及第二低介電常數層112具有類似的密度。在一實施例中，第二低介電常數層112的厚度大於第一低介電常數層108的厚度。In one embodiment, the materials of the first low dielectric constant layer 108 and the second low dielectric constant layer 112 each include yttrium oxide, but the density thereof varies depending on the manner in which it is formed. For example, when the first low dielectric constant layer 108 is formed by a thermal oxidation process, the structure is relatively tight and the density is high; and when the second low dielectric constant layer 112 is formed by a chemical vapor deposition process, the structure thereof It is loose and has a low density. Alternatively, when the first low dielectric constant layer 108 and the second low dielectric constant layer 112 are both formed by a chemical vapor deposition process, the first low dielectric constant layer 108 and the second low dielectric constant layer 112 have similarities. Density. In an embodiment, the thickness of the second low dielectric constant layer 112 is greater than the thickness of the first low dielectric constant layer 108.
請參照圖1C，於溝槽106的下部填入第一導體層116。在一實施例中，於複合介電層114上形成導體材料，且導體材料填滿溝槽106。導體材料包括摻雜多晶矽，且其形成方法包括進行化學氣相沉積製程。接著，移除部分導體材料，直到剩餘的導體材料的頂面低於磊晶層104的頂面。所述移除步驟包括進行化學機械研磨（CMP）製程及/或回蝕刻製程。Referring to FIG. 1C, a first conductor layer 116 is filled in the lower portion of the trench 106. In one embodiment, a conductor material is formed over the composite dielectric layer 114 and the conductor material fills the trenches 106. The conductor material includes doped polysilicon and the method of forming includes performing a chemical vapor deposition process. Next, a portion of the conductor material is removed until the top surface of the remaining conductor material is below the top surface of the epitaxial layer 104. The removing step includes performing a chemical mechanical polishing (CMP) process and/or an etch back process.
請參照圖1D，於第一導體層116上形成第一絕緣層118。在一實施例中，第一絕緣層118的材料包括氧化矽，且其形成方法包括進行熱氧化製程。由於第一絕緣層118是由熱氧化製程所形成，故其結構較緊密。在一實施例中，第一絕緣層118的頂面低於磊晶層104的頂面。Referring to FIG. 1D, a first insulating layer 118 is formed on the first conductor layer 116. In an embodiment, the material of the first insulating layer 118 includes hafnium oxide, and the method of forming the method includes performing a thermal oxidation process. Since the first insulating layer 118 is formed by a thermal oxidation process, the structure is relatively tight. In an embodiment, the top surface of the first insulating layer 118 is lower than the top surface of the epitaxial layer 104.
請參照圖1E，於形成第一絕緣層118的步驟之後，移除部分複合介電層114，以裸露出部分磊晶層104。在一實施例中，移除部分複合介電層114的步驟會裸露出溝槽106的上側壁，且剩餘的複合介電層114稱為複合介電層114a。在一實施例中，複合介電層114a包括第一低介電常數層108a、高介電常數層110a以及第二低介電常數層112a。在一實施例中，高介電常數層110a凸出於相鄰的第一低介電常數層108a與第二低介電常數層112a。在一實施例中，第一絕緣層118的頂面高於複合介電層114a的頂面。Referring to FIG. 1E, after the step of forming the first insulating layer 118, a portion of the composite dielectric layer 114 is removed to expose a portion of the epitaxial layer 104. In one embodiment, the step of removing a portion of the composite dielectric layer 114 exposes the upper sidewall of the trench 106, and the remaining composite dielectric layer 114 is referred to as a composite dielectric layer 114a. In one embodiment, the composite dielectric layer 114a includes a first low dielectric constant layer 108a, a high dielectric constant layer 110a, and a second low dielectric constant layer 112a. In one embodiment, the high dielectric constant layer 110a protrudes from the adjacent first low dielectric constant layer 108a and second low dielectric constant layer 112a. In an embodiment, the top surface of the first insulating layer 118 is higher than the top surface of the composite dielectric layer 114a.
請參照圖1F，於溝槽106內形成第二絕緣層120，且第二絕緣層120覆蓋溝槽106的上側壁以及複合介電層114a和第一絕緣層118的表面。此外，遮罩絕緣層（screen insulating layer）121形成為覆蓋磊晶層104的表面。在一實施例中，第二絕緣層120以及遮罩絕緣層121的材料包括氧化矽，且其形成方法包括進行至少一化學氣相沉積製程。在一實施例中，可於同一步驟中同時形成第二絕緣層120以及遮罩絕緣層121。在另一實施例中，可於不同步驟中分別形成第二絕緣層120以及遮罩絕緣層121。Referring to FIG. 1F, a second insulating layer 120 is formed in the trench 106, and the second insulating layer 120 covers the upper sidewall of the trench 106 and the surfaces of the composite dielectric layer 114a and the first insulating layer 118. Further, a screen insulating layer 121 is formed to cover the surface of the epitaxial layer 104. In an embodiment, the material of the second insulating layer 120 and the mask insulating layer 121 includes yttrium oxide, and the forming method thereof comprises performing at least one chemical vapor deposition process. In an embodiment, the second insulating layer 120 and the mask insulating layer 121 may be simultaneously formed in the same step. In another embodiment, the second insulating layer 120 and the mask insulating layer 121 may be formed in different steps, respectively.
特別要說明的是，移除部分複合介電層114是指完全移除溝槽106的上側壁上的複合介電層114，不會殘留任何複合介電層114作為閘介電層，如圖1E所示。而後續形成作為閘介電層的第二絕緣層120時（如圖1F所示），可將第一絕緣層118因移除部分複合介電層114而損耗的厚度補回。In particular, removing a portion of the composite dielectric layer 114 means completely removing the composite dielectric layer 114 on the upper sidewall of the trench 106 without leaving any composite dielectric layer 114 as a gate dielectric layer. 1E is shown. When the second insulating layer 120 is formed as a gate dielectric layer (as shown in FIG. 1F), the thickness of the first insulating layer 118 which is lost due to the removal of a portion of the composite dielectric layer 114 can be replenished.
請參照圖1G，於溝槽106的上部形成第二導體層122。在一實施例中，於磊晶層104上形成導體材料，且導體材料填滿溝槽106。在一實施例中，導體材料包括摻雜多晶矽，且其形成方法包括進行化學氣相沉積製程。之後，進行化學機械研磨製程及/或回蝕刻製程，以移除溝槽106外的導體材料。在一實施例中，第二絕緣層120與第二導體層122之間的界面實質上平滑。Referring to FIG. 1G, a second conductor layer 122 is formed on the upper portion of the trench 106. In one embodiment, a conductor material is formed on the epitaxial layer 104 and the conductor material fills the trenches 106. In one embodiment, the conductor material comprises doped polysilicon and the method of forming comprises performing a chemical vapor deposition process. Thereafter, a chemical mechanical polishing process and/or an etch back process is performed to remove the conductor material outside the trenches 106. In an embodiment, the interface between the second insulating layer 120 and the second conductor layer 122 is substantially smooth.
請參照圖1H，於磊晶層104中形成主體層124。在一實施例中，主體層124為具有第二導電型的主體層，例如是P型主體層，且其形成方法包括進行離子植入製程。Referring to FIG. 1H, a body layer 124 is formed in the epitaxial layer 104. In one embodiment, the body layer 124 is a body layer having a second conductivity type, such as a P-type body layer, and the method of forming includes performing an ion implantation process.
然後，於主體層124中形成摻雜區126。在一實施例中，摻雜區126為具有第一導電型的摻雜區126，例如是N型重摻雜區，且其形成方法包括進行離子植入製程。Doped regions 126 are then formed in body layer 124. In one embodiment, the doped region 126 is a doped region 126 having a first conductivity type, such as an N-type heavily doped region, and the method of forming includes performing an ion implantation process.
接著，於磊晶層104上形成介電層128。在一實施例中，介電層128的材料包括氧化矽、硼磷矽玻璃（BPSG）、磷矽玻璃（PSG）、氟矽玻璃（FSG）或未摻雜矽玻璃（USG），且其形成方法包括進行化學氣相沉積製程。Next, a dielectric layer 128 is formed on the epitaxial layer 104. In an embodiment, the material of the dielectric layer 128 comprises yttrium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), fluorocarbon glass (FSG) or undoped bismuth glass (USG), and the formation thereof The method includes performing a chemical vapor deposition process.
繼之，形成接觸栓130，且接觸栓130與摻雜區126電性連接。在一實施例中，形成貫穿介電層128及摻雜區126的至少二開口。形成所述開口的方法包括進行微影蝕刻製程。之後，於所述開口中填入導體層以構成接觸栓130。導體層的材料包括金屬，例如鋁，且其形成方法包括進行化學氣相沉積製程。至此，完成本發明的溝槽式閘極金氧半場效電晶體10的製作。Then, the contact plug 130 is formed, and the contact plug 130 is electrically connected to the doping region 126. In one embodiment, at least two openings are formed through the dielectric layer 128 and the doped regions 126. The method of forming the opening includes performing a photolithography process. Thereafter, a conductor layer is filled in the opening to constitute a contact plug 130. The material of the conductor layer includes a metal such as aluminum, and the method of forming the same includes performing a chemical vapor deposition process. So far, the fabrication of the trench gate MOS field effect transistor 10 of the present invention has been completed.
在一實施例中，於移除部分複合介電層114的步驟（圖1E）之後以及於形成第二絕緣層120的步驟（圖1F）之前，於溝槽106的側壁上形成襯層119，以形成如圖2之溝槽式閘極金氧半場效電晶體11。在一實施例中，襯層119的材料包括氧化矽，且其形成方法包括進行熱氧化製程。在一實施例中，襯層119位於磊晶層104與第二絕緣層120之間。In an embodiment, a liner 119 is formed on the sidewall of the trench 106 after the step of removing a portion of the composite dielectric layer 114 (FIG. 1E) and before the step of forming the second insulating layer 120 (FIG. 1F). To form a trench gate MOS field effect transistor 11 as shown in FIG. In one embodiment, the material of the liner layer 119 includes hafnium oxide, and the method of forming the same includes performing a thermal oxidation process. In an embodiment, the liner layer 119 is between the epitaxial layer 104 and the second insulating layer 120.
在以上的實施例中，是以第一導電型為N型，第二導電型為P型為例來說明，但本發明並不以此為限。本領域具有通常知識者應了解，第一導電型也可以為P型，而第二導電型為N型。In the above embodiments, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. It should be understood by those of ordinary skill in the art that the first conductivity type may also be a P type while the second conductivity type is an N type.
在本發明的溝槽式閘極金氧半場效電晶體10/11中，第二導體層122（或上部電極）作為閘極，第一導體層116（或下部電極）作為遮蔽電極或源電極，摻雜區126作為源極，且基底102作為汲極。在一實施例中，第二絕緣層120的垂直部分作為閘介電層，而第二絕緣層120的水平部分以及第一絕緣層118共同作為閘極與遮蔽閘極之間的閘間絕緣層。In the trench gate MOS field effect transistor 10/11 of the present invention, the second conductor layer 122 (or upper electrode) serves as a gate, and the first conductor layer 116 (or lower electrode) serves as a shielding electrode or a source electrode. Doped region 126 acts as a source and substrate 102 acts as a drain. In one embodiment, the vertical portion of the second insulating layer 120 serves as a gate dielectric layer, and the horizontal portion of the second insulating layer 120 and the first insulating layer 118 collectively serve as a gate insulating layer between the gate and the shielding gate. .
在習知的方法中，先移除溝槽上部的側壁的氧化層，接著形成閘間絕緣層，再於溝槽上部形成閘極。習知方式所形成的閘間絕緣層具有明顯的階梯部，因此閘極的底面兩側會有齒狀凸出結構，對閘極-汲極間寄生電容（Qgd）有不良的影響。本發明的方法中，是先製作閘間絕緣層，接著移除溝槽上部的側壁的複合介電層，再於溝槽上部形成閘極。本發明方法所形成的閘間絕緣層具有不明顯的階梯部，因此閘極的底面大致平坦，不會有齒狀凸出結構。In a conventional method, an oxide layer on the sidewall of the upper portion of the trench is first removed, followed by an inter-gate insulating layer, and a gate is formed on the upper portion of the trench. The barrier insulating layer formed by the conventional method has a distinct step portion, so that the bottom surface of the gate electrode has a tooth-like convex structure, which adversely affects the parasitic capacitance (Qgd) between the gate and the drain. In the method of the present invention, the inter-gate insulating layer is first formed, then the composite dielectric layer on the sidewall of the upper portion of the trench is removed, and a gate is formed on the upper portion of the trench. The inter-gate insulating layer formed by the method of the present invention has an inconspicuous step portion, so that the bottom surface of the gate is substantially flat and does not have a toothed convex structure.
此外，習知閘極的底面兩側會有齒狀凸出結構而導致該處的閘間絕緣層的厚度變薄，進而增加閘極-汲極間寄生電容（Qgd）而造成元件效能下降。然而，本發明本發明之閘間絕緣層與閘極之間的界面實質上平滑。因此，本發明的閘間絕緣層可有效拉開閘極與汲極的距離，減少閘極-汲極間寄生電容（Qgd），進而大幅提升元件的效能。In addition, the conventional gate has a tooth-like convex structure on both sides of the bottom surface, which causes the thickness of the gate insulating layer to be thinner, thereby increasing the parasitic capacitance (Qgd) between the gate and the drain, resulting in a decrease in device performance. However, the interface between the gate insulating layer and the gate of the present invention is substantially smooth. Therefore, the inter-gate insulating layer of the present invention can effectively open the distance between the gate and the drain, and reduce the parasitic capacitance (Qgd) between the gate and the drain, thereby greatly improving the performance of the device.
基於所述，本發明的製造方法簡單、製程裕度寬，且可利用現有的製程輕易地製作出低閘極-汲極間寄生電容的溝槽式閘極金氧半場效電晶體，有效提升產品競爭力。Based on the above, the manufacturing method of the invention is simple, the process margin is wide, and the trench gate MOS field effect transistor with low parasitic capacitance between the gate and the drain can be easily fabricated by using the existing process, thereby effectively improving Product competitiveness.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、11‧‧‧溝槽式閘極金氧半場效電晶體10,11‧‧‧Groove gated MOS half-field effect transistor
102‧‧‧基底102‧‧‧Base
104‧‧‧磊晶層104‧‧‧ epitaxial layer
106‧‧‧溝槽106‧‧‧ trench
108、108a‧‧‧第一低介電常數層108, 108a‧‧‧ first low dielectric constant layer
110、110a‧‧‧高介電常數層110, 110a‧‧‧high dielectric constant layer
112、112a‧‧‧第二低介電常數層112, 112a‧‧‧ second low dielectric constant layer
114、114a‧‧‧複合介電層114, 114a‧‧‧Composite dielectric layer
116‧‧‧第一導體層116‧‧‧First conductor layer
118‧‧‧第一絕緣層118‧‧‧First insulation
120‧‧‧第二絕緣層120‧‧‧Second insulation
121‧‧‧遮罩絕緣層121‧‧‧Mask insulation
122‧‧‧第二導體層122‧‧‧Second conductor layer
124‧‧‧主體層124‧‧‧ body layer
126‧‧‧摻雜區126‧‧‧Doped area
128‧‧‧介電層128‧‧‧ dielectric layer
130‧‧‧接觸栓130‧‧‧Contact plug
圖1A至1H為依據本發明一實施例所繪示的一種溝槽式閘極金氧半場效電晶體的製造方法的剖面示意圖。 圖2為依據本發明另一實施例所繪示的一種溝槽式閘極金氧半場效電晶體的剖面示意圖。1A to 1H are schematic cross-sectional views showing a method of fabricating a trench gate MOS field effect transistor according to an embodiment of the invention. FIG. 2 is a cross-sectional view showing a trench gate MOS field effect transistor according to another embodiment of the invention.
Claims (8)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106142745A TWI726176B (en) | 2017-12-06 | 2017-12-06 | Method of manufacturing trench gate mosfet |
| CN201810163573.4A CN109887840B (en) | 2017-12-06 | 2018-02-27 | Manufacturing method of trench gate metal oxide semiconductor field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106142745A TWI726176B (en) | 2017-12-06 | 2017-12-06 | Method of manufacturing trench gate mosfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201926437A true TW201926437A (en) | 2019-07-01 |
| TWI726176B TWI726176B (en) | 2021-05-01 |
Family
ID=66924778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106142745A TWI726176B (en) | 2017-12-06 | 2017-12-06 | Method of manufacturing trench gate mosfet |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109887840B (en) |
| TW (1) | TWI726176B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI778671B (en) * | 2021-06-21 | 2022-09-21 | 新唐科技股份有限公司 | Semiconductor structure and method of forming the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112802895B (en) * | 2021-01-06 | 2022-04-08 | 江苏东海半导体股份有限公司 | Manufacturing method of low-capacitance split-gate trench IGBT device intermediate isolation oxide layer |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8497549B2 (en) * | 2007-08-21 | 2013-07-30 | Fairchild Semiconductor Corporation | Method and structure for shielded gate trench FET |
| US7897462B2 (en) * | 2008-11-14 | 2011-03-01 | Semiconductor Components Industries, L.L.C. | Method of manufacturing semiconductor component with gate and shield electrodes in trenches |
| US8415739B2 (en) * | 2008-11-14 | 2013-04-09 | Semiconductor Components Industries, Llc | Semiconductor component and method of manufacture |
| TWI512841B (en) * | 2012-07-13 | 2015-12-11 | Ubiq Semiconductor Corp | Method of forming trench gate mosfet |
| TWI570917B (en) * | 2014-12-31 | 2017-02-11 | 帥群微電子股份有限公司 | Trench power mosfet and manufacturing method thereof |
| US20170200803A1 (en) * | 2016-01-11 | 2017-07-13 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
| US9722071B1 (en) * | 2016-01-25 | 2017-08-01 | Sinopower Semiconductor, Inc. | Trench power transistor |
| TWI567979B (en) * | 2016-06-22 | 2017-01-21 | Sinopower Semiconductor Inc | Trench power transistor |
-
2017
- 2017-12-06 TW TW106142745A patent/TWI726176B/en active
-
2018
- 2018-02-27 CN CN201810163573.4A patent/CN109887840B/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI778671B (en) * | 2021-06-21 | 2022-09-21 | 新唐科技股份有限公司 | Semiconductor structure and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI726176B (en) | 2021-05-01 |
| CN109887840B (en) | 2023-05-09 |
| CN109887840A (en) | 2019-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11640973B2 (en) | Semiconductor device and method for fabricating the same | |
| US9865694B2 (en) | Split-gate trench power mosfet with protected shield oxide | |
| TWI470790B (en) | Trench gate mosfet | |
| KR100772114B1 (en) | Method of manufacturing semiconductor device | |
| TWI662652B (en) | Method of forming integrated circuit | |
| TWI512841B (en) | Method of forming trench gate mosfet | |
| KR100970282B1 (en) | Trench MOSFET and Manufacturing Method thereof | |
| TWI567830B (en) | Trench power transistor structure and manufacturing method thereof | |
| CN103578954A (en) | Semiconductor integrated circuit with metal gate | |
| US10079143B2 (en) | Method of forming semiconductor device having wick structure | |
| CN109887840B (en) | Manufacturing method of trench gate metal oxide semiconductor field effect transistor | |
| TWI750375B (en) | Trench gate mosfet and method of forming the same | |
| TWI737855B (en) | Power transistor and manufacturing method thereof | |
| TWM480763U (en) | Trench power MOSFET | |
| KR20190020249A (en) | Semiconductor device | |
| TWI675409B (en) | Shielded gate mosfet and fabricating method thereof | |
| TWI546956B (en) | Trench gate mosfet | |
| TWI435447B (en) | Power mosfet and method of fabricating the same | |
| TW201926470A (en) | Trench gate MOSFET | |
| US11664424B2 (en) | Device with epitaxial source/drain region | |
| TWI775695B (en) | Trench transistor and manufacturing method thereof | |
| TW201937607A (en) | Trench gate MOSFET | |
| CN117995775A (en) | Method for forming semiconductor structure | |
| TW202347774A (en) | Semiconductor device and method for fabricating the same | |
| TW202410469A (en) | Semiconductor device and methods of forming the same |