CN117637480B - Shielded gate trench MOSFET device and manufacturing process thereof - Google Patents
Shielded gate trench MOSFET device and manufacturing process thereof Download PDFInfo
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- CN117637480B CN117637480B CN202311506322.9A CN202311506322A CN117637480B CN 117637480 B CN117637480 B CN 117637480B CN 202311506322 A CN202311506322 A CN 202311506322A CN 117637480 B CN117637480 B CN 117637480B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000011241 protective layer Substances 0.000 claims abstract description 15
- 239000002243 precursor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 230000008021 deposition Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005429 filling process Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
The invention discloses a shielded gate trench MOSFET device and a manufacturing process thereof, wherein the manufacturing process comprises the following steps: preparing a substrate, forming an epitaxial layer on the substrate, and forming a deep trench on the epitaxial layer; setting a field oxide layer and shielding gate polysilicon in the deep trench; depositing a silicon nitride protective layer on the side wall of the field oxide layer and the upper surface of the shielding gate polysilicon; filling high-doped polysilicon in the deep trench, and etching the high-doped polysilicon; oxidizing the highly doped polysilicon to form an isolation oxide layer precursor; etching the silicon nitride protective layer and the field oxide layer to form an isolation oxide layer; and setting a gate oxide layer and gate polysilicon in the deep trench. The invention forms a gate-source electrode interval isolation oxide layer with regular morphology and reliable quality by adjusting the IPO process, and on the other hand, the invention is not limited by the HDP-CVD filling depth-to-width ratio process, and can be used for forming IPO with regular morphology for small cell size products.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a shielded gate trench MOSFET device and a manufacturing process thereof.
Background
At present, in the semiconductor device technology, compared with the traditional trench type MOSFET, the shielded gate trench type field effect transistor (Shielded-GATE TRENCH MOSFET, SGT-MOSFET) introduces horizontal depletion on the basis of vertical depletion of a PN junction, changes the electric field of the device from triangular distribution to approximately rectangular distribution, and can obtain higher breakdown voltage under the condition of adopting the epitaxial material specification with the same doping concentration. Meanwhile, the introduction of the shielding grid structure separated by the isolation oxide layer (IPO) can greatly reduce the Miller capacitance of the MOSFET and help to reduce the switching loss during the period.
In the prior art, there is a process for preparing a shielded gate power semiconductor device, as shown in fig. 1A to 1G, and the conventional SGT-MOSFET device manufacturing process includes the following steps:
preparing a substrate 1, forming an epitaxial layer 2 on the substrate 1, and forming a silicon dioxide barrier layer 3 on the epitaxial layer 2, as shown in fig. 1A;
Etching the epitaxial layer 2 and the barrier layer 3 to form deep trenches 4, as shown in fig. 1B;
forming a field oxide layer 6 on the side wall and bottom of the deep trench 4 as shown in fig. 1C;
A deposition of a first polysilicon 7 is performed to fill the deep trenches 4, as shown in figure 1D,
Forming a shielding gate polysilicon 7-1 by etching back the first polysilicon 7 twice, as shown in fig. 1E and 1F (only the active region trench is etched back for the second time, and a person skilled in the art can know about the processing method of the termination region trench from other related technical documents);
Forming an isolation oxide layer 9 above the shielding gate polysilicon 7-1 by etching back after HDP deposition, as shown in fig. 1G;
forming a gate oxide layer 10 on the side wall of the deep trench 4 above the isolation oxide layer 9 through thermal oxidation, refilling second polysilicon in the deep trench 4, and etching back to form a gate polysilicon 11, as shown in fig. 1H;
The following processes related to other source and drain are known to those skilled in the art from other related art documents according to the difference in performance requirements of the semiconductor device, and will not be described herein. Compared with the technology of directly generating the IPO and the gate oxide layer through one step of thermal oxidation in the prior art, the IPO shape generated by the HDP filling technology is better, however, as the cell size is continuously reduced, the depth-to-width ratio of HDP filling is continuously increased, and the depth-to-width ratio is more and more close to the performance limit of the current HDP filling machine, so that the voltage withstand between the gate and the source is often reduced due to the abnormal HDP filling shape.
Disclosure of Invention
Therefore, the invention aims to provide a shielded gate trench MOSFET device and a manufacturing process thereof, wherein an isolated oxide layer between a gate and a source with regular morphology and reliable quality is formed by adjusting an IPO process, and on the other hand, the invention is not limited by an HDP-CVD filling depth-to-width ratio process and can be used for forming the IPO with regular morphology for small cell size products.
In order to achieve the above object, the present invention provides a process for manufacturing a shielded gate trench MOSFET device, which is characterized by comprising the steps of:
preparing a substrate, forming an epitaxial layer on the substrate, and forming a deep trench on the epitaxial layer;
Setting a field oxide layer and shielding gate polysilicon in the deep trench;
depositing a silicon nitride protective layer on the exposed side wall of the deep trench and the upper surface of the shielding gate polysilicon;
Filling high-doped polysilicon in the deep trench, and etching the high-doped polysilicon;
Oxidizing the highly doped polysilicon to form an isolation oxide layer precursor;
Etching the exposed silicon nitride protective layer, further etching the exposed field oxide layer, and forming an isolation oxide layer, wherein the isolation oxide layer comprises an unetched part of the silicon nitride protective layer and an unetched part of an isolation oxide layer precursor;
and setting a gate oxide layer and gate polysilicon in the deep trench.
Preferably, a field oxide layer and shielding gate polysilicon are arranged in the deep trench, and the method specifically comprises the following steps:
setting a field oxide layer on the side wall and the bottom of the deep trench;
filling first polysilicon in the deep trench;
and etching the first polysilicon back to form shielding gate polysilicon.
Preferably, a gate oxide layer and gate polysilicon are disposed in the deep trench, and the method specifically comprises the following steps:
Forming a gate oxide layer on the exposed side wall of the deep trench through thermal oxidation and deposition;
filling second polysilicon in the deep trench;
And etching the second polysilicon back to form gate polysilicon.
Preferably, the ratio of the depth of the upper surface of the shielding gate polysilicon from the upper surface of the epitaxial layer to the width of the deep trench is greater than 2.5.
The invention further discloses a MOSFET device with the shielding gate groove manufactured by the manufacturing process, the unetched part of the silicon nitride protective layer is concave, and the unetched part of the isolation oxide layer precursor is positioned in the concave.
The beneficial effects of the invention are as follows:
(1) The invention forms a gate-source electrode interval isolation oxide layer with regular morphology and reliable quality by adjusting the IPO process;
(2) Compared with the traditional HDP-CVD process, the method is not limited by the HDP-CVD filling depth-to-width ratio process (namely, the method can be applied to the scene with the filling depth-to-width ratio exceeding 2.5), and can be used for forming IPO with regular morphology by small cell size products.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIGS. 1A-1H are schematic flow diagrams of the prior art;
FIGS. 2A-2G are schematic flow diagrams of the present invention;
Wherein:
1. a substrate; 2. an epitaxial layer; 3. a barrier layer; 4. deep trenches; 6. a field oxide layer; 7. a first polysilicon; 7-1 shielding gate polysilicon; 8. a silicon nitride protective layer; 9. an isolation oxide layer; 9-1 highly doped polysilicon; 9-2 isolating the oxide layer precursor; 10. a gate oxide layer; 11 gate polysilicon.
Detailed Description
The invention has the core of providing a shielded gate trench MOSFET device and a manufacturing process thereof, forming a gate-source electrode interval isolation oxide layer with regular morphology and reliable quality by adjusting an IPO process, and on the other hand, the invention is not limited by an HDP-CVD filling depth-to-width ratio process, and can be used for forming the IPO with regular morphology for small cell size products.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
Fig. 2A to 2G illustrate a process for manufacturing a shielded gate trench MOSFET according to the present embodiment, including the following steps:
S1: referring to the steps in the background art, as shown in fig. 1A to 1F, the steps include: preparing a substrate 1, forming an epitaxial layer 2 on the substrate 1, and forming a deep trench 4 on the epitaxial layer 2; forming a field oxide layer 6 on the side wall and the bottom of the deep trench 4 by a thermal oxidation and deposition mode, and then filling first polysilicon 7 in the deep trench 4 by a deposition mode; performing first dry etching on the first polysilicon 7; and then, performing second dry etching to etch the first polysilicon 7 to a required depth to form the shielding gate polysilicon 7-1.
S2: a silicon nitride protective layer 8 is deposited on the sidewalls of the exposed field oxide layer 6 and on the upper surface of the shield gate polysilicon 7-1 as shown in fig. 2A.
S3: the deep trench 4 is filled with highly doped polysilicon 9-1, and the highly doped polysilicon 9-1 is etched back and oxidized to form an isolation oxide precursor 9-2, as shown in fig. 2B and 2C.
S4: etching the exposed silicon nitride protective layer 8 as shown in fig. 2D;
s5: the exposed field oxide layer 6 is further etched and an isolation oxide layer 9 is formed, the isolation oxide layer 9 including an unetched portion of the silicon nitride protective layer 8 and an unetched portion of the isolation oxide layer precursor 9-2, the unetched portion of the silicon nitride protective layer 8 being concave, the unetched portion of the isolation oxide layer precursor 9-2 being located within the concave, as shown in fig. 2E:
s6: a gate oxide layer 10 is formed on the exposed side walls of the deep trench 4 by thermal oxidation and deposition, as shown in fig. 2F, and a thin oxide layer is formed on the upper surface of the isolation oxide layer 9, so as to avoid the contact between the gate polysilicon 11 formed in step S7 and the silicon nitride protection layer 8.
S7: and filling the second polysilicon in the deep trench, and etching back the second polysilicon to form gate polysilicon 11, as shown in fig. 2G.
In another aspect of this embodiment, a shielded gate trench MOSFET device is disclosed that can be fabricated by the fabrication process described above.
Similarly, regarding the manufacturing process of the other portions of the active region and the termination region, those skilled in the art can know the related processing methods from other related technical documents according to the difference in performance requirements of the semiconductor device, which will not be described herein.
In this embodiment, the filling depth-to-width ratio allowed by the filling process of polysilicon replaces the HDP filling process of oxide, which can reach more than 15, is far higher than the depth-to-width ratio allowed by the filling process of polysilicon with better storage morphology (i.e. about 2.5) in the prior art, and since polysilicon needs to be fully oxidized later, the silicon nitride protection layer 8 is additionally arranged to avoid oxidization of the side wall of the deep trench 4, and meanwhile, highly doped polysilicon is selected as polysilicon to be oxidized for filling, so that the IPO layer which is not limited by the depth-to-width ratio of the filling process of HDP-CVD is realized, and the method can be used for forming the IPO layer with the morphology rule degree similar to that of the HDP-CVD process for small cell size products.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. The manufacturing process of the shielded gate trench MOSFET device is characterized by comprising the following steps of:
preparing a substrate, forming an epitaxial layer on the substrate, and forming a deep trench on the epitaxial layer;
Setting a field oxide layer and shielding gate polysilicon in the deep trench;
Depositing a silicon nitride protective layer on the exposed side wall of the field oxide layer and the upper surface of the shielding gate polysilicon;
Filling high-doped polysilicon in the deep trench, and etching the high-doped polysilicon;
Oxidizing the highly doped polysilicon to form an isolation oxide layer precursor;
Etching the exposed silicon nitride protective layer, further etching the exposed field oxide layer and etching the isolation oxide layer precursor, and forming an isolation oxide layer, wherein the isolation oxide layer comprises a non-etched part of the silicon nitride protective layer and a non-etched part of the isolation oxide layer precursor;
and setting a gate oxide layer and gate polysilicon in the deep trench.
2. The process of claim 1, wherein providing a field oxide layer and a shield gate polysilicon in the deep trench comprises:
setting a field oxide layer on the side wall and the bottom of the deep trench;
filling first polysilicon in the deep trench;
and etching the first polysilicon back to form shielding gate polysilicon.
3. The process of claim 1, wherein disposing a gate oxide layer and a gate polysilicon in the deep trench comprises:
Forming a gate oxide layer on the exposed side wall of the deep trench through thermal oxidation and deposition;
filling second polysilicon in the deep trench;
And etching the second polysilicon back to form gate polysilicon.
4. The process of claim 1, wherein a ratio of a depth of the upper surface of the shield gate polysilicon from the upper surface of the epitaxial layer to a width of the deep trench is greater than 2.5.
5. A shielded gate trench MOSFET device formed by the process of any one of claims 1 to 4, wherein said unetched portion of the silicon nitride protective layer is recessed, and said unetched portion of the isolation oxide precursor is within said recess.
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| CN202311506322.9A CN117637480B (en) | 2023-11-13 | 2023-11-13 | Shielded gate trench MOSFET device and manufacturing process thereof |
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