KR101483721B1 - Power mosfet having recessed cell structure and fabrication method thereof - Google Patents

Power mosfet having recessed cell structure and fabrication method thereof Download PDF

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KR101483721B1
KR101483721B1 KR20130051789A KR20130051789A KR101483721B1 KR 101483721 B1 KR101483721 B1 KR 101483721B1 KR 20130051789 A KR20130051789 A KR 20130051789A KR 20130051789 A KR20130051789 A KR 20130051789A KR 101483721 B1 KR101483721 B1 KR 101483721B1
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conductive type
thermal oxidation
forming
semiconductor layer
step
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KR20130051789A
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Korean (ko)
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KR20140132526A (en
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윤기창
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주식회사 원코아에이
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

The present invention relates to a power MOSFET, and more particularly, to a power MOSFET having a new concave cell structure that fuses a conventional planar type and a trench type structure and a fabrication method thereof, It is possible not only to improve the thermal characteristics by raising the switching speed, but also to use the conventional planar manufacturing method as it is, and mass production is possible without increasing the manufacturing cost.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power MOSFET having a concave cell structure,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly, to a power MOSFET structure and a manufacturing method thereof.

Since electric and electronic products require increasingly lower heat generation and higher durability, the power MOSFETs used in electric and electronic products have extremely low on-resistance (Ron) and high breakdown voltage (BV), and A fast switching speed is required.

The conventional planar type MOSFET structure is simple in manufacturing method and it is easy to make a product having a high withstand voltage. On the other hand, it is difficult to reduce the on-resistance (Ron) related to the thermal characteristics and the gate area It is difficult to reduce the gate size. In order to lower the ON resistance, the concentration of the semiconductor layer, which is the current path, must be increased or decreased. In this case, the breakdown voltage (BV) is reduced. To reduce the gate area, the gate length must be reduced. Source region has a limitation in reducing the gate length due to the thermal diffusion of the p-well. Therefore, the conventional planar MOSFET structure has a problem that it can not satisfy both the heat, the breakdown voltage and the switching speed.

In addition, a trench-type MOSFET structure is generally used for electric and electronic products in which the internal pressure is as low as 200 V or less and a tens of amperes (A) current is required. This can reduce the on-resistance to a level much larger than that of the planar type, but on the contrary, it is difficult to maintain a high withstand voltage of 200 V or more.

FIG. 1 shows a typical trench-type MOSFET structure disclosed in Korean Patent No. 10-0480673. In order to solve the problem that the surface of the sidewall of the trench is roughened when the trench is formed and the channel resistance becomes large and the electric field is concentrated on the sharp portion of the trench corner, it is necessary to form the trench vertically before forming the gate oxide film, A sacrificial oxide film forming process and a wet etching process for removing an oxide film after forming an oxide film by an oxidation process are further disclosed.

That is, in Korean Patent No. 10-0480673, as shown in FIG. 1, an N-semiconductor layer 132 is formed on an N + drain (substrate) 130, A sacrificial oxide film forming process and a wet etching process are performed so as to form a deep trench 136 through etching and to smooth the sidewall of the trench 136 and to smooth the corner, The P-body 142 and the N + source region 144 are formed through impurity ion implantation and thermal diffusion and the gate electrode 140 and the source electrode 152 are separated from each other by an insulating film 146 are formed and then the source electrode 152 is formed.

However, as described in Korean Patent No. 10-0480673, the problem with the conventional trench MOSFET is that the N-semiconductor layer must be physically etched deeply in order to form a trench structurally, There is a problem that the electric field concentrates on a sharp point of the trench corner. To solve this problem, a separate sacrificial oxide film forming process and a wet etching process must be performed as in Korean Patent No. 10-0480673.

Further, even if a separate sacrificial oxide film forming process and a wet etching process are further performed as described in Korean Patent No. 10-0480673, there is a certain limit to round the corner of the bottom of the trench, and when the gate oxide film is formed, There is a problem that the gate oxide film is formed thin. As a result, there is a problem of reliability due to the dielectric strength of the gate oxide film, and the weak point of durability remains.

The present invention is a power MOSFET having a conventional planar MOSFET structure or a trench MOSFET structure, and it is difficult to satisfy all of the low resistance, high breakdown voltage and high speed switching required in current electrical and electronic products. Therefore, And a power MOSFET having a new concave cell structure in which a trench type structure is fused and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a power MOSFET comprising: a first conductive drain region formed in contact with a drain electrode in a lower portion and formed horizontally; A first conductive semiconductor layer formed on the first conductive type drain region; A gate electrode formed on the first conductivity type semiconductor layer so as to have a downward sloped surface on at least one side with a gate insulating film therebetween; A second conductive type body region formed on the first conductive type semiconductor layer with a lower portion of the lower surface of the gate electrode and the gate insulating film interposed therebetween; A first conductive type source region formed on the second conductive type body region with an upper portion of the downward sloping surface of the gate electrode and the gate insulating film interposed therebetween; And a second conductive contact region in contact with the first conductive type source region and formed on the second conductive type body region.

Here, the first conductive type semiconductor layer may have a concave groove structure inclined inward by the first conductive type source region, the second conductive type body region, and the first conductive type semiconductor layer, A gate electrode may be formed.

A method of manufacturing a power MOSFET according to the present invention includes forming a first conductive type drain region on a predetermined semiconductor substrate and forming a first conductive type semiconductor layer with a predetermined thickness on the first conductive type drain region, step; A second step of forming a pad oxide film on the first conductive type semiconductor layer and forming a mask material layer on the pad oxide film; A third step of etching the mask material layer through a photolithography process to form a thermal oxidation protection mask so that a part of the pad oxide layer is exposed; A fourth step of forming a local oxide film which is thick in the pad oxide film exposed through the thermal oxidation process and tapered into a bird's beak shape under the mask for thermal oxidation prevention; A fifth step of removing the thermal oxidation-resistant mask, the pad oxide film, and the local oxide film to form a downwardly sloped concave groove on the upper surface of the first conductive type semiconductor layer; A sixth step of forming a gate insulating film on the upper surface of the first conductivity type semiconductor layer through a thermal oxidation process; Depositing a gate material on the gate insulating layer and etching the gate material to form a gate electrode filled with the concave groove; An eighth step of forming a second conductive type body region in the first conductive type semiconductor layer to a lower side of an inclined surface of the concave groove through ion implantation with a second conductive type impurity on the entire surface of the substrate through a thermal drive-in process; Forming a first conductive type source region in the second conductive type body region to the upper side of the inclined surface of the concave groove through ion implantation with a first conductive type impurity on the entire surface of the substrate through a thermal drive-in process; And forming a sidewall insulation film on a side surface of the gate electrode, implanting ions of a second conductivity type impurity into the entire surface of the substrate, and performing a thermal drive-in process on the entire surface of the substrate, And forming a second conductive type contact region in contact with the second conductive type contact region.

The step of forming the first conductive type channel stopping layer in the first conductive type semiconductor layer using the thermal oxidation protection mask as the anti-doping mask may be further performed between the third step and the fourth step .

In the present invention, a LOCOS process, which has been used for device isolation in an integrated circuit process, is actively used instead of a trench process to form a recessed groove having a downwardly sloping shape in the form of a bird's beak formed in the epi- And forming the gate electrode in the concave groove substantially solves the problem of the channel resistance increase due to the conventional trench etching and the problem that the electric field is concentrated on the sharp portion of the trench corner.

Further, since the present invention is similar to the process of the conventional planar MOSFET structure, it is much simpler than the process of the conventional trench MOSFET structure, and the on-resistance can be structurally lowered and the switching speed and the gate- , It is possible to cope with heat generation required in electronic products, and further, the size of the device can be reduced, thereby contributing to cost reduction.

1 is a cross-sectional view showing a conventional trench type MOSFET structure.
FIGS. 2 to 8 are cross-sectional views illustrating a method of manufacturing a power MOSFET according to an embodiment of the present invention.
9 to 12 are cross-sectional views illustrating a method of manufacturing a power MOSFET according to another embodiment of the present invention.
13 to 15 are process cross-sectional views illustrating a method of manufacturing a power MOSFET according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[About structure Example ]

The power MOSFET according to the present invention basically includes a first conductive type (e.g., N type) drain region 10 formed in contact with a drain electrode (not shown) at the bottom and horizontally, as illustrated in FIG. A first conductive semiconductor layer (20) formed on the first conductive type drain region; A gate electrode (52) formed on the first conductivity type semiconductor layer with a gate insulating film (34) interposed therebetween and having a downward sloped surface on at least one side thereof; A second conductive type (e.g., P type) body region 60 formed on the first conductive type semiconductor layer with the gate insulating film interposed therebetween under the downward slope of the gate electrode; A first conductive type source region (70) formed on the second conductive type body region with an upper portion of the downward sloping surface of the gate electrode and the gate insulating film interposed therebetween; And a second conductive contact region (62) in contact with the first conductive type source region and formed on the second conductive type body region.

Here, the gate electrode 52 may have a wedge-shaped upper light blocking structure so as to have a downward sloped surface on the side thereof so as to have a smaller horizontal width while being directed downward toward the first conductive drain region 10.

The channel is inclined in the second conductive type body region 60 formed below the downward slope of the gate electrode 52 with the gate insulating film 34 interposed therebetween so that the gate size is smaller than that of the conventional planar MOSFET structure So that the top and bottom edges of the source region and the gate electrode can be gently formed more than the conventional trench type MOSFET structure, so that it is possible to simultaneously increase the switching speed and the dielectric breakdown voltage between the gate and the source.

If the first conductivity type is N-type, the second conductivity type is P-type and may be opposite to each other. In the present specification and the accompanying drawings, the first conductive type is described or indicated as N-type and the second conductive type is referred to as P-type for convenience, but they may be described or indicated opposite to each other.

In the present specification and the accompanying drawings, P- and P + refer to a P-type impurity doped layer, and both N- and N + refer to an N-type impurity doped layer, .

The power MOSFET according to the present invention can be implemented as shown in FIG.

That is, the N + source region 70, the P-body region 60, and the N-semiconductor layer 20 form a recessed trench inwardly inclined, and the gate insulating film 34 is interposed in the recessed trench The gate electrode 52 may be formed in a filled state.

In this case, the shape of the concave groove may be inclined only to one side on which the channel is to be formed, but it may be symmetrical with respect to two opposing surfaces, and when it is arbitrarily and vertically symmetrical in the front, rear, left, As shown in FIG.

In the latter case, the N < + > semiconductor layer 20 is brought into contact with the bottom of the gate electrode 52 with the gate insulating film 34 therebetween, and the N + source region 70 and the P- The P + contact region 62 surrounds the N + source region 70 on the P-body region 60, and the P + contact region 62 surrounds the N + source region 70 on the downwardly inclined surface of the gate electrode 52, Respectively.

The P-body region 60 is formed in the form of a P-well to form a channel under the gate electrode 52. Therefore, it is preferable that the P-body region 60 is formed so as to reach the bottom of at least concave grooves as shown in FIG. Do.

A source electrode 90 is connected to a predetermined contact plug 92 or directly to one side of the surface where the N + source region 70 and the P + contact region 62 are in contact. The contact plug 92 is used when the interlayer insulating film 80 is formed as usual. The connection structure with the source electrode 90 shown in Fig. 8 can be applied to the example in which each of the above-described components is symmetrical in four directions.

In addition, reference numeral 82 shown in FIG. 8 denotes an N + source region 70 formed of an N type impurity with a sidewall insulating film 82 formed on a side surface of the gate electrode 52, and then a P + Is used as an ion blocking mask.

In the above embodiments, the N-type semiconductor layer 20 is formed in the epitaxial layer or the semiconductor substrate itself as a low concentration doping layer than the N + drain region 10. In the bottom part of the recessed groove, N Type channel stop doping layer 40 is further formed.

By doing so, the interval between the both P-body regions 60 can be made as short as possible by the N-type channel stop doping layer 40, so that the overall capacitance is reduced and the switching speed of the device can be increased, Can be further lowered.

In addition, as described later, the concave groove is formed by forming a thick field oxide film (local oxide film) by high temperature thermal oxidation and removing it by wet etching, and then forming the gate insulating film 34 thereon. The gate insulating film can be prevented from being thinned at the corner due to the bottom of the smoothly inclined field oxide film, which is a disadvantage of the conventional trench structure, There is an advantage that the characteristics of the insulating film 34 can be improved.

The voltage applied between the source electrode 90 and the drain electrode (not shown) during turn-on is applied as a reverse bias between the P + contact region 62 and the N + drain region 10, Since the depletion layer is diffused in the horizontal direction between the P-body region 60 and the N-semiconductor layer 20, a high breakdown voltage (BV) is also possible.

[Manufacturing Method First Embodiment ]

Next, a method of manufacturing a power MOSFET according to an embodiment of the present invention will be described with reference to FIGS. 2 to 8. FIG.

First, as shown in FIG. 2, a first conductive type (e.g., N type) N + drain region 10 is formed in a predetermined semiconductor substrate, and an N- (Step 1).

Here, the semiconductor substrate may be a silicon substrate, and the reverse surface of the substrate on which the N + drain region 10 is not formed may be back-grasped and then a drain electrode (not shown) may be formed by a back metal Respectively.

Although the N-type semiconductor layer 20 can be formed by a low concentration ion implantation with an N-type impurity into the semiconductor substrate itself, an N-type impurity is formed on the N + -type drain region 10 in which the N-type impurity is implanted at a relatively high concentration (Epi layer) epitaxially grown in a low concentration state. At this time, the height of the epilayer and the concentration of the impurity may be varied according to Spec .: Specification of the device to be manufactured.

3, a pad oxide layer 30 is formed on the N-semiconductor layer 20, and a mask material layer 35 is formed on the pad oxide layer 30 (second step).

The mask material layer 35 may be directly formed of a nitride such as a silicon nitride film (Si 3 N 4 ) to form a thermal oxidation protection mask. However, as shown in FIG. 3, It is preferable that the polysilicon film 31 is first formed thick and then the silicon nitride film 33 is laminated. With the latter, the thickness of the pad oxide film 30 can be reduced, and bird's beak can be formed short in the local oxidation process. As a result, the length of the gate electrode can be reduced, and the shrinkage of the chip can be achieved, and the switching speed can be rapidly increased.

Next, as shown in FIG. 4, the mask material layer 35 is etched through a photolithography process to form a thermal oxidation protection mask 35a to expose a part of the pad oxide film 30 (third step).

Next, as shown in FIG. 4, the N-type semiconductor layer 20 is subjected to an ion implantation process using the anti-oxidation mask 35a as an anti-doping mask, The process of forming the stop doping layer 40 may be further performed and the next process may be performed.

By doing so, it is possible to form the P-type impurity in the next process as close as possible to each other at the time of forming the P-body region on both sides through the thermal drive-in process after implanting the P-type impurity, thereby reducing the capacitance of the device as much as possible, And at the same time, the on-resistance can be further lowered.

5, a local oxide film 32, which is thick at the exposed portion of the pad oxide film 30 through the thermal oxidation process and tapers down to the bird's beak shape 32a under the thermal oxidation protection mask 35a, (Step 4).

6, the thermal oxidation protection mask 35a, the pad oxide film 30 and the local oxide film 32 are removed to form a recessed groove sloping downward on the upper surface of the N- (Step 5).

Next, as shown in FIG. 6, a gate insulating film 34 is formed on the upper surface of the N-semiconductor layer 20 through a thermal oxidation process (step 6).

Here, the gate insulating film 34 is formed by removing the local oxide film 32, which has already been formed at a high temperature and several micrometers thick, in the previous step by wet etching and forming a remaining smooth downwardly inclined recessed groove, Is superior to the conventional planar type and tinning phenomenon, which was a problem in the conventional trench type structure, can be fundamentally suppressed.

6, a gate material 50 is deposited on the gate insulating layer 34 and etched to form a gate electrode 52 filled with the concave grooves as shown in FIG. 7 (step 7).

Here, the gate material 50 may be a silicon-based material such as polysilicon doped with impurities.

Next, as shown in FIG. 7, the entire surface of the substrate is ion-implanted with an impurity such as a second conductive type (e.g., P type) impurity, that is, boron (B) Body region 60 in the form of a P-well to the bottom of the inclined surface of the concave groove in the step of forming the P-body region 20 (Step 8).

At this time, the gate electrode 52 serves as a doping-preventing mask in the P-type impurity ion implantation process. In the subsequent thermal drive-in process, the P-body region 60 extends from the edge of the gate electrode 52 toward the inside So as to extend to at least the lower part of the inclined surface of the concave groove. The extension of the P-body region 60 may be controlled by an N-type channel stop doping layer 40 formed in the N-semiconductor layer 20.

8, ion implantation is performed with an N-type impurity such as phosphorus (P) or arsenic (As) on the entire surface of the substrate, and the P-type body region 60 is implanted into the P-type body region 60 through a thermal- The N + source region 70 is formed up to the upper side of the inclined plane of the gate electrode (step 9).

Since the N + source region 70 is formed on the inclined surface of the concave groove formed smoothly in the sidewall of the local oxide film 32 by this step, the electric field is concentrated on the N + source region 70 as in the conventional trench type The problem does not occur and the breakdown voltage between the gate and the source can be increased.

8, a sidewall insulating film 82 is formed on the side surface of the gate electrode 52, and a P-type impurity is ion-implanted into the entire surface of the substrate, The P + contact region 62 in contact with the N + source region 70 is formed in the region 60 (Step 10). In this step, the N + source region 70 formed in the previous step of the thermal drive-in process is further diffused out of the sidewall insulation film 82 as shown in FIG. 8, so that the P + Source region 70 and the N + source region 70, as shown in FIG.

8, the interlayer insulating film 80 is formed on the entire surface of the substrate, and after planarization, the contact plug 92 and the source electrode (not shown) are formed through the via hole formation and the metal deposition process for forming the contact plugs 92, 90 are formed. Of course, only the gate electrode 52 may be surrounded by the interlayer insulating film 80, and the source electrode 90 may be directly formed on the junction surface of the P + contact region 62 and the N + source region 70. In any case, the source electrode 90 is brought into electrical contact with the P + contact region 62 and the N + source region 70 simultaneously.

In the above embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[Manufacturing Method Second Embodiment ]

9 to 12, a method of manufacturing a power MOSFET according to another embodiment of the present invention will be described.

The present embodiment differs from the first embodiment only in that the bird's beak is formed in a short time in the local oxidation process. Therefore, the process steps for this process will be mainly described, As described in the first embodiment.

9, a first conductivity type (e.g., N type) N + drain region 10 is formed on a predetermined semiconductor substrate, and an N + semiconductor layer 20 (Step 1).

Next, a pad oxide film 30 is formed on the N-semiconductor layer 20, and a nitride film 33 is formed on the pad oxide film 30 (second step).

10, the nitride layer 33 and the pad oxide layer 30 are etched through a photolithography process to form a thermal oxidation prevention mask 37 (third step).

10, the pad oxide layer 30a exposed between the etched nitride layers 33a is etched to a thickness only, and then the N-type impurity ions are implanted into the pad oxide layer 30a by N-type impurity ion implantation, The N-type channel stop doping layer 40 is formed on the N-type channel stop doping layer 20, and then the remaining thickness is etched as shown in FIG. 11 to improve the top surface state of the N- It is possible to form the layer 40, which is preferable.

12, a thermally oxidized film 36 is formed on the N-semiconductor layer 20 exposed to the inside of the thermal oxidation protection mask 37a to have a thin thickness, Oxidation preventing material is deposited and etched so that the thermal oxidation film 36 is exposed to form a thermal oxidation preventing sidewall 84 inside the thermal oxidation preventing mask 37a (step 4).

5, a local oxide film 32 which is thick at the exposed portion of the thermal oxidation film 36 through the thermal oxidation process and tapers down to the bird's beak shape 32a under the thermal oxidation-inhibited side wall 84 (Step 5).

Next, as shown in FIG. 6, the thermal oxidation preventing mask 37a, the thermal oxidation film 36, the thermal oxidation preventing side wall 84, and the local oxidation film 32 are removed, Thereby forming concave grooves inclined downward on the upper surface (step 6).

Since the subsequent process is the same as that of the first embodiment, repeated description will be omitted.

[Manufacturing Method Third Embodiment ]

13 to 15, a method of manufacturing a power MOSFET according to still another embodiment of the present invention will be described.

The present embodiment differs from the second embodiment only in that the bird's beak is formed in a short time in the local oxidation process. Therefore, the process steps are mainly described, As described in the second embodiment.

13, in the fourth step of the second embodiment, the N-semiconductor layer 20a exposed between the thermal oxidation prevention masks 37a is further etched to a certain depth, and then, as shown in FIG. 14, It is preferable that the oxide film 38 is also formed on the etched side wall.

By doing so, there is an advantage that a local oxide film having a shorter bird's beak than in the second embodiment can be formed.

14, the N-type impurity ion implantation is performed immediately after the thermal oxidation film 38 is formed or immediately after the thermal oxidation preventing sidewall 86 is formed, as shown in FIG. 15, It is preferable to form the N-type channel stop doping layer 40 in the semiconductor layer 20a and proceed to the next step.

Since the subsequent process is the same as that of the second embodiment, repeated description will be omitted.

10: N + drain region
20, 20a: N-
30: pad oxide film
31: Polysilicon film
32: local oxide film
33: nitride film (silicon nitride film)
34: Gate insulating film
35: mask material layer
35a, 37, 37a: a thermal oxidation prevention mask
36, 38: thermal oxide film
40: N-type channel stop doping layer
50; Gate material
52: gate electrode
60: P-body region
62: P + contact area
70: N + source region
80: Interlayer insulating film
82: sidewall insulation film
90: source electrode
92: contact plug

Claims (14)

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  10. A first step of forming a first conductive type drain region on a predetermined semiconductor substrate and a first conductive type semiconductor layer having a predetermined thickness on the first conductive type drain region;
    A second step of forming a pad oxide film on the first conductive type semiconductor layer and forming a nitride film on the pad oxide film;
    A third step of forming a thermal oxidation protection mask by etching the nitride film and the pad oxide film through a photolithography process;
    Forming a thermal oxidation film on the first conductivity type semiconductor layer exposed to the inside of the thermal oxidation prevention mask, depositing a thermal oxidation prevention material on the entire surface of the substrate, and etching the thermal oxidation oxidation film to expose the inner side A fourth step of forming a thermal oxidation-inhibiting sidewall on the substrate;
    A fifth step of forming a local oxide film which is thick at the exposed portion of the thermally oxidized film through the thermal oxidation process and tapers to the bottom of the thermally oxidized sidewall and forms a bird's beak;
    A sixth step of removing the thermal oxidation protection mask, the thermal oxidation film, the thermal oxidation prevention sidewall, and the local oxidation film to form a downwardly sloped concave groove on the upper surface of the first conductivity type semiconductor layer;
    A seventh step of forming a gate insulating film on the upper surface of the first conductive type semiconductor layer through a thermal oxidation process;
    Depositing a gate material on the gate insulating layer and etching the gate electrode to form a gate electrode filled with the concave groove;
    Forming a second conductive type body region in the first conductive type semiconductor layer to a lower side of an inclined surface of the concave groove through ion implantation with ions of a second conductive type impurity on the entire surface of the substrate through a thermal drive-in process;
    Forming a first conductive type source region in the second conductive type body region to the upper side of the inclined surface of the concave groove by ion implantation with a first conductive type impurity on the entire surface of the substrate through a thermal drive-in process; And
    Forming a sidewall insulation film on a side surface of the gate electrode, implanting ions of a second conductivity type impurity into the entire surface of the substrate, and performing a thermal drive-in process on the first conductive type source region and the second conductivity type body region, And forming a second conductive type contact region in contact with the second conductive type contact region.
  11. 11. The method of claim 10,
    In the third step, the pad oxide film exposed between the nitride films etched during the formation of the thermal oxidation protection mask is etched to a thickness only, and then the first conductive type channel stop is doped into the first conductive type semiconductor layer by the first conductive type impurity ion implantation Layer is formed and then the remaining thickness is etched.
  12. 11. The method of claim 10,
    Wherein the fourth conductive type semiconductor layer exposed between the thermal oxidation prevention masks is further etched by a predetermined depth.
  13. 13. The method of claim 12,
    In the fourth step, a first conductivity type channel stop doping layer is formed in the first conductivity type semiconductor layer by implanting ions of a first conductivity type impurity immediately after forming the thermal oxidation layer or the thermal oxidation prevention sidewall, Wherein the power MOSFET has a plurality of power MOSFETs.
  14. 14. The method according to any one of claims 10 to 13,
    Wherein the semiconductor substrate is a silicon substrate,
    Wherein the thermal oxidation-inhibiting material is polysilicon.
KR20130051789A 2013-05-08 2013-05-08 Power mosfet having recessed cell structure and fabrication method thereof KR101483721B1 (en)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH09199722A (en) * 1996-01-22 1997-07-31 Denso Corp Semiconductor device and its manufacture
JP2002076341A (en) 2000-08-23 2002-03-15 Nec Kansai Ltd Semiconductor device and its manufacturing method
JP2003505864A (en) * 1999-07-20 2003-02-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Trench-gate field-effect transistor and method of manufacturing the same
JP3921764B2 (en) * 1997-12-04 2007-05-30 株式会社デンソー Manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199722A (en) * 1996-01-22 1997-07-31 Denso Corp Semiconductor device and its manufacture
JP3921764B2 (en) * 1997-12-04 2007-05-30 株式会社デンソー Manufacturing method of semiconductor device
JP2003505864A (en) * 1999-07-20 2003-02-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Trench-gate field-effect transistor and method of manufacturing the same
JP2002076341A (en) 2000-08-23 2002-03-15 Nec Kansai Ltd Semiconductor device and its manufacturing method

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