CN116722027A - Super-junction IGBT device with carrier storage layer and manufacturing method thereof - Google Patents

Super-junction IGBT device with carrier storage layer and manufacturing method thereof Download PDF

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Publication number
CN116722027A
CN116722027A CN202310045119.XA CN202310045119A CN116722027A CN 116722027 A CN116722027 A CN 116722027A CN 202310045119 A CN202310045119 A CN 202310045119A CN 116722027 A CN116722027 A CN 116722027A
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carrier storage
storage layer
super
forming
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李�昊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

The invention provides a super-junction IGBT device with a carrier storage layer and a manufacturing method thereof, comprising the steps of providing an N-type substrate, and sequentially generating a field stop layer and an N-type epitaxial layer on the N-type substrate; forming an N-type carrier storage layer and a P-type body region on the surface of the N-type epitaxial layer in sequence, wherein an N-type epitaxial layer is arranged between the N-type carrier storage layer and the N-type substrate at intervals; forming a superjunction structure, wherein the superjunction structure is formed by alternately arranging a plurality of N-type columns and P-type columns; forming a trench gate, wherein the bottom of the trench gate is positioned in the N-type carrier storage layer; a source region composed of an N+ region is formed on the surface of the P-type body region; and forming a collector region at the bottom of the N-type substrate. According to the invention, on the basis of the existing super-junction IGBT device, the carrier storage layer (CS) layer is added, and the CS layer thickness which is most suitable for improving the device performance is manufactured, so that the IGBT device performance can be effectively improved.

Description

Super-junction IGBT device with carrier storage layer and manufacturing method thereof
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a super-junction IGBT device with a carrier storage layer and a manufacturing method thereof.
Background
IGBTs (Insulated Gate Bipolar Transistor, insulated gate bipolar transistors) combine the advantages of field effect transistors (MOSFETs) and Bipolar Junction Transistors (BJTs), and are one of the core electronic components in modern power electronic circuits.
IGBTs use drift regions of low doping concentration to achieve high withstand voltages, however there is a limit to the proportional relationship between breakdown voltage and on-resistance, i.e. "silicon limit". To break the "silicon limit", super Junction (SJ) theory has been proposed: the N, P columns are alternately arranged in the drift region, and the transverse depletion of the N, P columns is utilized to improve the electric field distribution, so that higher withstand voltage is obtained. Superjunction devices are widely used in schottky diodes, MOSFETs and IGBTs by virtue of their high withstand voltage, low on-resistance properties. Compared with the traditional silicon-based IGBT device, the SJ-IGBT device has higher withstand voltage under the same drift region length. As shown in fig. 1, a schematic structure diagram of an SJ-IGBT formed by the prior art is shown.
However, through extensive analysis, it was found that SJ-IGBTs are able to enhance the current density not due to the increased concentration of the drift region, but rather due to the Carrier Storage (CS) effect produced by the more concentrated SJ-NEPI regions. As shown in fig. 2, a schematic structure of an IGBT with a CS layer is shown. The SJ-IGBT should be called Super Carrier stored IGBT. The essence of the SJ-IGBT is that the IGBT with the ultra-thick CS layer is used up by utilizing the SJ principle in the forward direction and the reverse direction, so that the influence of the ultra-thick CS layer on the withstand voltage is avoided.
The conventional SJ-IGBT device adopts SJ (superjunction) or Semi-SJ (Semi superjunction) to be responsible for all withstand voltage, and the essence of the SJ-IGBT cannot be understood. Great effort is spent on not greatly improving the forward performance of the device, and even causing the degradation of the device performance. After discovering the essence of SJ-IGBTs, new questions are raised as to whether the CS layer is thicker or not, and better, in order to improve device performance.
Disclosure of Invention
In view of the above, the present invention provides a super-junction IGBT device having a carrier storage layer (CS layer) and a method for manufacturing the same, for effectively improving the performance of the IGBT device.
The invention provides a manufacturing method of a super-junction IGBT device with a carrier storage layer, which comprises the following steps:
providing an N-type substrate, and sequentially generating a field stop layer and an N-type epitaxial layer on the N-type substrate;
sequentially forming an N-type carrier storage layer and a P-type body region in the N-type epitaxial layer, wherein the N-type epitaxial layer is arranged between the N-type carrier storage layer and the N-type substrate at intervals;
forming a super junction structure, wherein the super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns;
forming a trench gate, wherein the bottom of the trench gate is positioned in the N-type carrier storage layer;
forming a source region consisting of an N+ region on the surface of the P-type body region;
and step six, forming a collector region at the bottom of the N-type substrate.
Preferably, the N-type substrate in the first step is an FZ wafer manufactured by an FZ method or an MCZ wafer manufactured by an MCZ method.
Preferably, in the second step, the N-type carrier storage layer may be formed by pattern definition and ion implantation or thermal diffusion process after the doped film deposition.
Preferably, the forming an N-type carrier storage layer in the N-type epitaxial layer in the second step includes: implanting N-type doping ions into the N-type epitaxial layer through an ion implantation process; the implanted N-type dopant ions are diffused within the N-type epitaxial layer by annealing.
Preferably, the thickness of the diffusion is in the range of 10-20 um.
Preferably, the thickness of the N-type carrier storage layer is 10um.
Preferably, forming the superjunction structure in the third step includes:
forming a plurality of superjunction grooves in the N-type carrier storage layer and the P-type body region by adopting a photoetching process;
filling a P-type epitaxial layer in the super junction groove to form the P-type column; the N-type column is composed of the N-type epitaxial layer and the N-type carrier storage layer between the P-type columns.
Preferably, the method further comprises:
step seven, forming an interlayer film, wherein the interlayer film covers the source region, the trench gate and the body region;
step eight, forming contact holes penetrating through the interlayer film on the tops of the source region and the trench gate respectively;
and step nine, forming a front metal layer on the surface of the interlayer film.
Preferably, forming the collector region in the sixth step includes:
thinning the back surface of the semiconductor substrate;
and performing ion implantation on the back surface of the thinned semiconductor substrate to form the collector region.
Preferably, the method further comprises the fabrication of the termination region.
Preferably, the termination region is fabricated by adopting a conventional IGBT structure.
The invention also provides a super-junction IGBT device with the carrier storage layer, which comprises a terminal area and a cell area adopting a traditional IGBT structure, wherein the cell area comprises:
an N-type substrate;
a field stop layer and an N-type epitaxial layer positioned above the N-type substrate;
an N-type carrier storage layer and a P-type body region above the N-type epitaxial layer;
the super junction structure is formed by transversely and alternately arranging a plurality of N-type columns and P-type columns;
the plurality of trench gates penetrate through the P-type body region, and the bottoms of the trench gates enter the N-type carrier storage layer;
a source region formed on the surface of the P-type body region and composed of an n+ region;
an interlayer film covering the source region, the trench gate, and the body region surface;
a contact hole penetrating the interlayer film at the source region and the top of the trench gate;
a front metal layer located on a surface of the interlayer film; and
and the collector region is positioned at the bottom of the N-type substrate.
The N-type carrier storage layer is formed through pattern definition and ion implantation or a thermal diffusion process after the doped film is deposited; the thickness was 10um.
According to the invention, the super CS structure is adopted only in a Cell (Cell) area, the traditional IGBT structure is adopted completely in a terminal area, and the effective improvement of the performance of the IGBT device is realized by adding the N-type carrier storage layer in the Cell area and manufacturing the thickness of the CS layer which is most suitable for the improvement of the performance of the device. Meanwhile, the N-type carrier storage layer is formed by adopting pattern definition and ion implantation or a thermal diffusion process after doped film deposition, and a layout is not required to be changed or an epitaxial layer is not required to be added, so that the N-type carrier storage layer has lower cost.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic structure of an SJ-IGBT formed by the prior art;
fig. 2 shows a schematic structure of an IGBT with a CS layer;
FIG. 3 is a schematic diagram showing the carrier storage layer depths of 5um, 10um, 20um, and 40um, respectively;
fig. 4 shows voltage-current curves of the super-junction IGBT carrier storage layers with thicknesses of 5um, 10um, 20um, and 40 um;
fig. 5 is a flowchart showing a method for manufacturing a super-junction IGBT device having a carrier storage layer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a super-junction IGBT device with a carrier storage layer according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of a cell region of a super-junction IGBT device having a carrier storage layer according to an embodiment of the present invention.
Reference numerals illustrate:
a 1-P column; 2-body region; 3-trench gate; 4-contact holes; 5-interlayer film; 6-a front side metal layer; 7-carrier storage layer.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like throughout the application are to be construed as including but not being exclusive or exhaustive; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
The withstand voltage characteristic is one of the most important parameters of the IGBT device, and insufficient withstand voltage may cause risk of breakdown burnout when the IGBT device is used. In order to improve the withstand voltage characteristics of the IGBT device, the present invention further researches whether the Carrier Storage (CS) layer is thicker or not. The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
As shown in fig. 3, the CS layer thicknesses were set to 5um, 10um, 20um, 40um, respectively. Fig. 4 shows a corresponding voltage-current graph. It can be seen from the figure that not the thicker the CS layer the better the current capability, neither too thin nor too thick is the optimal choice. The super junction NEPI structure of 10umCS has the strongest current density. Therefore, the thickness of the CS layer is not thicker and better, the thickness is not limited by the voltage-resistant condition, the thickness of the CS layer which is most suitable for improving the device performance can be manufactured according to the actual condition, the voltage-resistant of the CS heavily doped part is ensured by using the SJ structure, and the voltage-resistant of other parts is also given to the IGBT device. On the basis of the existing super-junction IGBT device, a carrier storage layer (CS) layer is added, and the thickness of the CS layer which is most suitable for improving the device performance is manufactured, so that the IGBT device performance can be effectively improved.
Fig. 5 is a flowchart illustrating a method of fabricating a superjunction IGBT device having a carrier storage layer according to an embodiment of the present invention. As shown in fig. 5, the method for manufacturing the super-junction IGBT device with the carrier storage layer according to the embodiment of the invention includes the steps of:
providing an N-type substrate, and sequentially generating a field stop layer and an N-type epitaxial layer on the N-type substrate.
As a constituent material of the substrate, undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like can be used. In the embodiment of the invention, the N-type substrate is an FZ wafer manufactured by an FZ method or an MCZ wafer manufactured by an MCZ method.
And step two, an N-type carrier storage layer and a P-type body region are sequentially formed in the N-type epitaxial layer, and an N-type epitaxial layer is arranged between the N-type carrier storage layer and the N-type substrate at intervals.
The N-type carrier storage layer may be formed by pattern definition, ion implantation, or thermal diffusion process after deposition of the doped film. Specifically, forming an N-type carrier storage layer in the N-type epitaxial layer includes: implanting N-type doping ions into the N-type epitaxial layer through an ion implantation process; the implanted N-type dopant ions are diffused within the N-type epitaxial layer by annealing. The thickness of the diffusion is typically in the range of 10-20 um. In the embodiment of the invention, the thickness of the CS layer which is most suitable for improving the performance of the device can be manufactured according to actual conditions. Preferably, the N-type Carrier Storage (CS) layer has a thickness of 10um.
And thirdly, forming a super junction structure, wherein the super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns.
In an embodiment of the present invention, forming the superjunction structure includes:
forming a plurality of superjunction grooves in the N-type carrier storage layer and the P-type body region by adopting a photoetching process;
filling a P-type epitaxial layer in the super junction groove to form the P-type column; the N-type column is composed of an N-type epitaxial layer and an N-type carrier storage layer between the P-type columns.
And step four, forming a trench gate, wherein the bottom of the trench gate is positioned in the N-type carrier storage layer.
And fifthly, forming a source region consisting of an N+ region on the surface of the P-type body region.
And step six, forming a collector region at the bottom of the N-type substrate.
And after the front-side process is finished, continuing to carry out a back-side process, namely thinning the substrate, and carrying out ion implantation on the back side of the N-type substrate to form a P-type collector region. And forming a back metal layer on the bottom surface of the N-type substrate, wherein the back metal layer and the collector region form a collector of the IGBT device.
The manufacturing method of the super-junction IGBT device with the carrier storage layer further comprises the following steps:
and step seven, forming an interlayer film which covers the surfaces of the source region, the trench gate and the body region.
In the embodiment of the invention, the interlayer film is an interlayer dielectric layer.
And eighth, forming contact holes penetrating through the interlayer film on the tops of the source region and the trench gate respectively.
And forming a contact hole in the interlayer dielectric layer through photoetching and etching processes, and leading out the source region and the trench gate through the contact hole.
And step nine, forming a front metal layer on the surface of the interlayer film.
Depositing front metal on the surface of the interlayer dielectric layer, patterning the front metal to form a front metal layer, and connecting a source region with the front metal layer through a contact hole to form an emitter of the IGBT device; the trench gate is connected with the front metal layer through the contact hole to form the gate of the IGBT device.
The embodiment of the invention is inserted into the floating P column to help the pressure resistance of the Super CS layer in the reverse direction through the SJ principle. In addition, the manufacturing method of the super-junction IGBT device with the carrier storage layer further comprises the manufacturing of the terminal area. In the embodiment of the invention, the terminal region is manufactured by adopting a traditional IGBT structure.
Fig. 6 shows a schematic diagram of a superjunction IGBT device with a carrier storage layer according to an embodiment of the invention. As shown in fig. 6, the super-junction IGBT device with a carrier storage layer according to the embodiment of the invention includes a Cell (Cell) region and a termination region. The invention adopts super CS structure only in a Cell (Cell) area, and completely adopts traditional IGBT structure in a terminal area, thereby maximally utilizing the prior IGBT technology. For the effect of the Super CS region, the CS layer preferably needs to diffuse approximately 10um further, although this can be adjusted as the case may be.
Fig. 7 is a schematic structural diagram of a cell region of a super-junction IGBT device having a carrier storage layer according to an embodiment of the present invention. As shown in fig. 7, the cell region of the super-junction IGBT device with a carrier storage layer according to the embodiment of the invention includes an N-type substrate, a field stop layer (FS) and an N-type epitaxial layer (NEPI) located above the N-type substrate, an N-type carrier storage layer 7 and a P-type body region 2 located above the N-type epitaxial layer, a super-junction structure, a plurality of trench gates 3, a source region formed on the 2 surface of the P-type body region and composed of an n+ region, a collector region (P-) formed on the bottom of the N-type substrate, an interlayer film covering the source region, the trench gates and the body region surface, a contact hole at the top of the source region and the trench gates through the interlayer film, and a front metal layer located on the surface of the interlayer film. The super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns, and the bottom of the trench gate is positioned in the N-type carrier storage layer.
The super-junction IGBT device with the carrier storage layer is formed by the following process on the basis of the existing super-junction IGBT device: and forming an N-type carrier storage layer in the N-type epitaxial layer through pattern definition and ion implantation or a thermal diffusion process after the deposition of the doped film. In the embodiment of the invention, the thickness of the N-type carrier storage layer is 10um.
Of course, the following steps also include: forming an interlayer film, and forming an opening of a contact hole penetrating through the interlayer film; filling metal in the opening to form a complete contact hole; forming a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode; and thinning the back surface of the N-type substrate, and forming a back metal layer on the back surface of the thinned N-type substrate, which is not shown in the figure.
According to the super-junction IGBT device with the carrier storage layer, the super CS structure is adopted only in a Cell (Cell) area, the traditional IGBT structure is adopted completely in a terminal area, the N-type carrier storage layer is added in the Cell area, and the CS layer thickness most suitable for improving the device performance is manufactured, so that the effective improvement of the IGBT device performance is realized. Meanwhile, the N-type carrier storage layer is formed by adopting pattern definition and ion implantation or a thermal diffusion process after doped film deposition, and a layout is not required to be changed or an epitaxial layer is not required to be added, so that the N-type carrier storage layer has lower cost.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. The manufacturing method of the super junction IGBT device with the carrier storage layer is characterized by comprising the following steps of:
providing an N-type substrate, and sequentially generating a field stop layer and an N-type epitaxial layer on the N-type substrate;
sequentially forming an N-type carrier storage layer and a P-type body region in the N-type epitaxial layer, wherein the N-type epitaxial layer is arranged between the N-type carrier storage layer and the N-type substrate at intervals;
forming a super junction structure, wherein the super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns;
forming a trench gate, wherein the bottom of the trench gate is positioned in the N-type carrier storage layer;
forming a source region consisting of an N+ region on the surface of the P-type body region;
and step six, forming a collector region at the bottom of the N-type substrate.
2. The method of manufacturing a super-junction IGBT device having a carrier storage layer according to claim 1, wherein the N type substrate in the first step is an FZ wafer manufactured by an FZ method or an MCZ wafer manufactured by an MCZ method.
3. The method of fabricating a super-junction IGBT device with a carrier storage layer according to claim 1, wherein in step two, the N-type carrier storage layer is formed by pattern definition and ion implantation or thermal diffusion after deposition of a doped film.
4. The method of manufacturing a super-junction IGBT device with a carrier storage layer according to claim 3, wherein forming an N-type carrier storage layer in the N-type epitaxial layer in step two comprises: implanting N-type doping ions into the N-type epitaxial layer through an ion implantation process; the implanted N-type dopant ions are diffused within the N-type epitaxial layer by annealing.
5. The method of manufacturing a super-junction IGBT device with a carrier storage layer according to claim 4, wherein the thickness of the diffusion is in the range of 10 to 20 um.
6. The method of manufacturing a super-junction IGBT device with a carrier storage layer according to claim 5, wherein the N type carrier storage layer has a thickness of 10um.
7. The method of manufacturing a superjunction IGBT device with a carrier storage layer according to claim 1, wherein forming the superjunction structure in step three comprises:
forming a plurality of superjunction grooves in the N-type carrier storage layer and the P-type body region by adopting a photoetching process;
filling a P-type epitaxial layer in the super junction groove to form the P-type column; the N-type column is composed of the N-type epitaxial layer and the N-type carrier storage layer between the P-type columns.
8. The method of manufacturing a superjunction IGBT device with a carrier storage layer according to claim 1, characterized in that the method further comprises:
step seven, forming an interlayer film, wherein the interlayer film covers the source region, the trench gate and the body region;
step eight, forming contact holes penetrating through the interlayer film on the tops of the source region and the trench gate respectively;
and step nine, forming a front metal layer on the surface of the interlayer film.
9. The method of manufacturing a super-junction IGBT device with a carrier storage layer according to claim 1, wherein forming the collector region in step six comprises:
thinning the back surface of the semiconductor substrate;
and performing ion implantation on the back surface of the thinned semiconductor substrate to form the collector region.
10. The method of fabricating a superjunction IGBT device with a carrier storage layer of claim 1 further comprising fabrication of termination regions.
11. The method for manufacturing a super-junction IGBT device with a carrier storage layer according to claim 10, wherein the termination region is fabricated using a conventional IGBT structure.
12. A superjunction IGBT device having a carrier storage layer formed by the method of any of claims 1 to 11, comprising termination and cell regions using conventional IGBT structures, the cell region comprising:
an N-type substrate;
a field stop layer and an N-type epitaxial layer positioned above the N-type substrate;
an N-type carrier storage layer and a P-type body region above the N-type epitaxial layer;
the super junction structure is formed by transversely and alternately arranging a plurality of N-type columns and P-type columns;
the plurality of trench gates penetrate through the P-type body region, and the bottoms of the trench gates enter the N-type carrier storage layer;
a source region formed on the surface of the P-type body region and composed of an n+ region;
an interlayer film covering the source region, the trench gate, and the body region surface;
a contact hole penetrating the interlayer film at the source region and the top of the trench gate;
a front metal layer located on a surface of the interlayer film; and
and the collector region is positioned at the bottom of the N-type substrate.
The N-type carrier storage layer is formed through pattern definition and ion implantation or a thermal diffusion process after the doped film is deposited; the thickness was 10um.
CN202310045119.XA 2023-01-30 2023-01-30 Super-junction IGBT device with carrier storage layer and manufacturing method thereof Pending CN116722027A (en)

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CN116722027A true CN116722027A (en) 2023-09-08

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