CN110047831A - A kind of semiconductor power device and preparation method thereof - Google Patents
A kind of semiconductor power device and preparation method thereof Download PDFInfo
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- CN110047831A CN110047831A CN201910379243.3A CN201910379243A CN110047831A CN 110047831 A CN110047831 A CN 110047831A CN 201910379243 A CN201910379243 A CN 201910379243A CN 110047831 A CN110047831 A CN 110047831A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000005192 partition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000001259 photo etching Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The present invention proposes a kind of semiconductor power device and preparation method thereof, it opens up three grooves in the first conductive type epitaxial layer upper surface of semiconductor substrate, is provided with hard mask layer between first groove and second groove, on the first surface of second groove between each other, between second groove and third groove；Three trench walls and its periphery are equipped with gate oxide, and conductive polycrystalline silicon is filled up in three grooves, is all covered with insulating medium layer above three grooves and its periphery, hard mask layer；The periphery of three grooves is equipped with the first conduction type implanted layer and the second conduction type implanted layer from top to bottom；It is covered with metal layer on the insulating medium layer of first groove and its periphery top, is covered with second metal layer on the insulating medium layer above third groove and its periphery.On the basis of guaranteeing the Performance And Reliability of device, the light shield number of plies is reduced to 3 layers the present invention, and manufacturing cost is effectively reduced.
Description
Technical field
The invention belongs to technical field of semiconductors, especially a kind of semiconductor power device and preparation method thereof.
Background technique
High voltage, powerful groove type MOS device products are still using six layers of photoetching even manufacture of eight layers of photoetching
Technology, it is at high cost, the manufacturing cycle is long, competitiveness is low.
" groove type high-power MOS device and its manufacturer are disclosed in existing Chinese patent ZL 201010003953.5
Method ", relate to a kind of groove type MOS device using the manufacture of 6 photoetching techniques；Its basic process steps includes:
(1), field oxide is grown
(2), active area etching (photoetching level 1)
(3), protection ring region etch, ion implanting, heat treatment form terminal protection structure (photoetching level 2)
(4), hard exposure mask growth and selective etch, define the region (photoetching level 3) of etching groove
(5), etching groove using hard mask selectivity is carried out
(6), gate oxide is grown, conductive polycrystalline silicon is deposited
(7), etching conductive polysilicon
(8), Second Type foreign ion is injected, heat treatment forms Second Type well layer
(9), it is lithographically formed first kind foreign ion injection region, injects first kind foreign ion, heat treatment is formed
First kind injection region (photoetching level 4)
(10), insulating medium layer is deposited
(11), lithographic definition lead porose area, etching form fairlead (photoetching level 5)
(12), deposited metal is lithographically formed metal electrode (photoetching level 6)
The groove type MOS device invented in patent ZL 201010003953.5, using the manufacturing technology of six photoetching,
Manufacturing cost is high, the production cycle is long, competitiveness is low.
" a kind of deep groove large power MOS device and its manufacture are disclosed in existing Chinese patent ZL 200710302461.4
Method ", relate to a kind of groove type power MOS device manufactured using four mask technology；For example described patent of its inventive structure
In ZL 200710302461.4 shown in Fig. 4, the basic thought of invention are as follows: a kind of groove type MOS device, in top plan view,
The terminal protection structure of active area comprising center and periphery；The terminal protection structure is by groove-shaped protection ring and one
Groove-shaped cut-off ring composition；The groove of the protection ring is located at the second conduction type implanted layer for being lightly doped, and depth gos deep into the
The first conduction type implanted layer below two conduction type implanted layers.
With the continuous maturation of groove type MOS device design and processes, market competition is increasingly fierce, reduces the system of device
This is caused, performance and the reliability for improving device are increasingly important.Under the premise of not influencing device performance, reduces device and manufacture work
Photoetching number in skill is to reduce one of the important means of device cost.
Summary of the invention
Technical problem solved by the invention is: providing a kind of semiconductor power device and the semiconductor power device
Preparation method reduces the light shield number of plies, uses 3 layers of illumination, manufacturing process is simple, effectively reduces manufacturing cost.
The technical solution for realizing the aim of the invention is as follows:
A kind of semiconductor power device, including semiconductor substrate, the semiconductor substrate include the first conduction of heavy doping
Type substrates and the first conductive type epitaxial layer being lightly doped, first surface are the upper surface of the first conductive type epitaxial layer, the
Two surfaces are the lower surface of the first conductivity type substrate；
First surface is provided with first groove, second groove and third groove in vertical direction, first groove and the second ditch
Hard mask layer is provided between slot, on the first surface of second groove between each other, between second groove and third groove；
Above first groove inner wall and its first surface of periphery, on second groove inner wall and its peripheral first surface
Gate oxide is provided with above the first surface of side, third trench wall and its periphery, first groove is interior, second groove is interior,
Fill up conductive polycrystalline silicon in third groove, above first groove and its above periphery top, second groove and its periphery top,
Insulating medium layer is all covered with above third groove and its above periphery top, hard mask layer；First table of first groove periphery
Below face, the second conduction is provided with below the first surface of second groove periphery, below the first surface of third groove periphery
Type implanted layer, the second conduction type implanted layer is under entire terminal protection area, the gate oxide of first groove periphery
The first conduction type is provided with below square, second groove periphery gate oxide, below the gate oxide of third groove periphery
Implanted layer, the first conduction type implanted layer between the second groove are hindered by hard mask layer and the second conduction type implanted layer
Block is disconnected, forms the terminal structure with pressure-resistant function, and the second conduction type implanted layer is located at the first conduction type extension
The top of layer；It is covered with the first metal layer on the insulating medium layer of first groove and its periphery top, the first metal layer is downward
It extends in first lead hole, insulating medium layer, the gate oxide of first groove periphery, the first ditch are run through in the first lead hole
First conduction type implanted layer of slot periphery is up to the top of the second conduction type implanted layer of first groove periphery；Third groove
And its it is covered with second metal layer on the insulating medium layer of periphery top, which extends downward into the second fairlead
In third fairlead, second fairlead through insulating medium layer until in third groove conductive polycrystalline silicon top, the
Three fairleads are through insulating medium layer, third groove periphery and the non-conterminous hard mask layer of second groove until the second conduction type
The top of implanted layer.
A method of preparing above-mentioned semiconductor power device, comprising the following steps:
Step 1, providing tool, there are two the first conductive type semiconductor substrate of apparent surface, first conduction types half
Conductor substrate includes the first conductivity type substrate of heavy doping and the first conductive type epitaxial layer being lightly doped, and it is conductive to define first
The upper surface of type epitaxial layer is first surface；
Step 2 deposits hard mask layer on the first surface, goes out hard mask etching region by lithographic definition and etches and covers firmly
Film layer forms the hard exposure mask for being used for etching groove；
Step 3, etching first surface form the groove in vertical direction, and the groove includes first groove, second groove
With third groove；Hard mask layer width between the second groove is greater than the hard mask layer width between first groove, described
Hard mask layer thickness of the hard mask layer width less than twice between first groove.
Step 4, using the hard mask layer on wet etching first surface, the hard mask layer of first groove periphery is carved completely
Erosion, the half of hard mask layer width of the etching degree between second groove, second groove periphery and third groove periphery
Hard mask layer partial etching retains the first surface between first groove and second groove, between second groove and third groove
On part hard mask layer, retain the part hard mask layer on the mutual first surface of second groove；
Step 5 grows gate oxide on the first surface, which covers the first groove inner wall and its periphery
First surface, second groove inner wall and its periphery first surface, third trench wall and its periphery first surface；
Step 6, deposit and etching conductive polysilicon, make to fill up conduction in first groove, second groove and third groove
Polysilicon；
Step 7: the second conductive type impurity is injected from gate oxide and is annealed, the first surface in first groove periphery
Lower section, the lower section of first surface of second groove periphery, third groove periphery to form second conductive the lower section of first surface
Type implanted layer, the second conduction type implanted layer are located at the top of the first conductive type epitaxial layer；Second conduction type note
Enter floor through terminal protection area.
Step 8: the first conductive type impurity is injected from gate oxide and is annealed, the gate oxide in first groove periphery
Lower section, the lower section of gate oxide of second groove periphery, third groove periphery to form first conductive the lower section of gate oxide
Type implanted layer, and the first conduction type implanted layer is located on the second conduction type implanted layer；First conduction type implanted layer
Stop to separate by hard mask layer, prevent leak channel, forms the terminal structure with pressure-resistant function.
Step 9: depositing insulating medium layer above gate oxide, above conductive polycrystalline silicon and above hard mask layer, this is absolutely
Edge dielectric layer is covered on above gate oxide, conductive polycrystalline silicon and hard mask layer；
Step 10: through hole lithographic definition goes out the region of fairlead, is sequentially etched and through insulating medium layer, first groove
Second conduction type of the first conduction type implanted layer of peripheral gate oxide, first groove periphery up to first groove periphery
First lead hole in vertical direction is formed at the top of implanted layer, and in first lead hole and its periphery deposits the first metal layer,
The first metal layer is full of first lead hole and is covered on the insulating medium layer of first lead hole periphery；
It etches and runs through insulating medium layer up to the top of the conductive polycrystalline silicon in third groove, formed in vertical direction
Second fairlead is sequentially etched and straight through insulating medium layer, third groove periphery and the non-conterminous hard mask layer of second groove
To the top of the second conduction type implanted layer, form the third fairlead in vertical direction, in the second fairlead and its periphery,
In third fairlead and its periphery deposit second metal layer, the second metal layer is full of the second fairlead, third fairlead and covers
It covers on the insulating medium layer of the second fairlead periphery and third fairlead periphery, and second metal layer and the first metal layer are not
It is connected.
The invention adopts the above technical scheme compared with prior art, and what is had has the technical effect that the present invention is guaranteeing device
On the basis of the Performance And Reliability of part, the light shield number of plies is reduced to 3 layers, and manufacturing process is simple, and manufacturing cost is effectively reduced.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that hard mask layer is deposited on semiconductor substrate first surface；
Fig. 2 is the structural schematic diagram etched after first groove, second groove, third groove；
Fig. 3 is the structural schematic diagram etched after hard mask layer；
Fig. 4 is the structural schematic diagram grown after gate oxide；
Fig. 5 is the structural schematic diagram after deposit and etching conductive polysilicon；
Fig. 6 is the structural schematic diagram after injecting p-type foreign ion；
Fig. 7 is the structural schematic diagram injected after N-type impurity ion；
Fig. 8 is the structural schematic diagram deposited after insulating medium layer；
Fig. 9 is the structural schematic diagram after deposited metal；
Appended drawing reference meaning: 1:N type substrate, 2:N type epitaxial layer, 3: hard mask layer, 4: first groove, 5: second groove,
6: hard mask layer, 7: gate oxide, 8: conductive polycrystalline silicon, 9:P type implanted layer, 10:N type implanted layer, 11: insulating medium layer, 12:
First lead hole, 13: the second fairleads, 14: third fairlead, 15: the first metal layer, 16: second metal layer.
Specific embodiment
Embodiments of the present invention are described below in detail, the example of the embodiment is shown in the accompanying drawings, wherein from beginning
Same or similar element or element with the same or similar functions are indicated to same or similar label eventually.Below by ginseng
The embodiment for examining attached drawing description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
A kind of semiconductor power device provided by the invention, as shown in fig. 9, it includes semiconductor substrate, the semiconductor
Substrate includes the N-type substrate 1 of heavy doping and the N-type epitaxy layer 2 being lightly doped, and first surface is the upper surface of N-type epitaxy layer 2, the
Two surfaces are the lower surface of N-type substrate 1；
First surface is provided with first groove 4, second groove 5 and third groove 6 in vertical direction, first groove 4 and
It is provided between two grooves 5, on the first surface of second groove 5 between each other, between second groove 5 and third groove 6 hard
Mask layer 3；
Above 4 inner wall of first groove and its first surface of periphery, on 5 inner wall of second groove and its peripheral first surface
Gate oxide 7 is provided with above the first surface of side, 6 inner wall of third groove and its periphery, in first groove 4, second groove 5
Fill up conductive polycrystalline silicon 8 in interior, third groove 6,4 top of first groove and its periphery top, 5 top of second groove and its outer
Insulating medium layer 11 is all covered with above the side of placing, 6 top of third groove and its periphery top, hard mask layer 3；First groove 4
It is equal below the peripheral first surface of the first surface lower section of periphery, the first surface lower section of 5 periphery of second groove, third groove 6
It is provided with p-type implanted layer 9, the p-type implanted layer 9 is under entire terminal protection area, the gate oxide 7 of 4 periphery of first groove
N-type implanted layer is provided with below the peripheral gate oxide 7 of side, 7 lower section of gate oxide of 5 periphery of second groove, third groove 6
10, the N-type implanted layer 10 between the second groove 5 stops partition by hard mask layer 3 and p-type implanted layer 9, formed have it is resistance to
The terminal structure of function is pressed, the p-type implanted layer 9 is located at the top of N-type epitaxy layer 2；It is exhausted above first groove 4 and its periphery
The first metal layer 15 is covered on edge dielectric layer 11, which extends downward into first lead hole 12, and described
The one fairlead 12 N-type implanted layer peripheral through insulating medium layer 11, the gate oxide 7 of 4 periphery of first groove, first groove 4
10 up to the top of the p-type implanted layer 9 of 4 periphery of first groove；It is covered on third groove 6 and its insulating medium layer 11 of periphery top
It is stamped second metal layer 16, which extends downward into the second fairlead 13 and in third fairlead 14, described
Through insulating medium layer 11 up to the top of conductive polycrystalline silicon 8 in third groove 6, third fairlead 14 runs through second fairlead 13
Insulating medium layer 11,6 periphery of third groove are with the non-conterminous hard mask layer 3 of second groove 5 until the top of N-type implanted layer.
The present invention also proposes a kind of method for preparing above-mentioned semiconductor power device, comprising the following steps:
Step 1 provides tool there are two the N-type semiconductor substrate of apparent surface, and the N-type semiconductor substrate includes heavy doping
N-type substrate 1 and the N-type epitaxy layer 2 that is lightly doped, the upper surface for defining N-type epitaxy layer 2 is first surface, as shown in Figure 1；
Step 2 deposits hard mask layer 3 on the first surface, as shown in Figure 1, passing through lithographic definition Chu Ying mask etching area
Domain simultaneously etches hard mask layer 3, forms the hard exposure mask for being used for etching groove；
Step 3, etching first surface form the groove in vertical direction, and the groove includes first groove 4, second groove
5 and third groove 6, as shown in Fig. 2, 3 width of hard mask layer between the second groove 5 be greater than it is hard between first groove 4
3 width of mask layer, hard mask layer 3 thickness of 3 width of hard mask layer less than twice between the first groove 4；
Step 4, using the hard mask layer 3 on wet etching first surface, the hard mask layer 3 of 4 periphery of first groove is complete
Etching, the half of hard mask layer 3 width of the etching degree between second groove 5,5 periphery of second groove and third groove 6
3 partial etching of hard mask layer of periphery retains between first groove 4 and second groove 5, between second groove 5 and third groove 6
First surface on part hard mask layer 3, retain the part hard mask layer 3 on the mutual first surface of second groove 5,
As shown in Figure 3；
Step 5, on the first surface grow gate oxide 7, the gate oxide 7 cover 4 inner wall of first groove and its
The first surface of periphery, the first surface of 5 inner wall of second groove and its periphery, 6 inner wall of third groove and its first table of periphery
Face, as shown in Figure 4；
Step 6, deposit and etching conductive polysilicon 8, make to fill up in first groove 4, second groove 5 and third groove 6
Conductive polycrystalline silicon 8, as shown in Figure 5；
Step 7: from injecting p-type impurity on gate oxide 7 and anneal, the first surface of the periphery of first groove 4 lower section,
The lower section of the first surface of 5 periphery of second groove, the lower section of the first surface of 6 periphery of third groove form p-type implanted layer 9, institute
The top that p-type implanted layer 9 is located at N-type epitaxy layer 2 is stated, p-type implanted layer 9 runs through terminal protection area, as shown in Figure 6；
Step 8: injecting N-type impurity from gate oxide 7 and anneal, under the gate oxide 7 of 4 periphery of first groove
The lower section of the gate oxide 7 of side, the lower section of the gate oxide 7 of 5 periphery of second groove, 6 periphery of third groove forms N-type implanted layer
10, and N-type implanted layer 10 is located on p-type implanted layer 9, N-type implanted layer 10 stops partition by hard mask layer 3, prevents from leaking electricity
Channel forms the terminal structure with pressure-resistant function, as shown in Figure 7；
Step 9: above gate oxide 7, insulating medium layer 11 is deposited above conductive polycrystalline silicon 8 and above hard mask layer 3,
The insulating medium layer 11 is covered on 3 top of gate oxide 7, conductive polycrystalline silicon 8 and hard mask layer, as shown in Figure 8；
Step 10: through hole lithographic definition goes out the region of fairlead, is sequentially etched and through insulating medium layer 11, the first ditch
The peripheral N-type implanted layer 10 of the gate oxide 7 of 4 periphery of slot, first groove 4 is up to the peripheral p-type implanted layer 10 of first groove 4
First lead hole 12 in vertical direction is formed at top, and in first lead hole 12 and its periphery deposits the first metal layer 15, should
The first metal layer 15 is full of first lead hole 12 and is covered on the insulating medium layer 11 of 12 periphery of first lead hole；
It etches and runs through insulating medium layer 11 up to the top of the conductive polycrystalline silicon 8 in third groove 6, form vertical direction
On the second fairlead 13, be sequentially etched and non-conterminous with second groove 5 through insulating medium layer 11, the periphery of third groove 6
Hard mask layer 3 until p-type implanted layer 9 top, formed vertical direction on third fairlead 14, in the second fairlead 13 and
Its periphery, in third fairlead 14 and its periphery deposit second metal layer 16, the second metal layer 16 full of the second fairlead 13,
It third fairlead 14 and is covered on the insulating medium layer 11 of 14 periphery of the periphery of the second fairlead 13 and third fairlead, and the
Two metal layers 16 are not attached to the first metal layer 15, as shown in Figure 9.
The above is only some embodiments of the invention, it is noted that for the ordinary skill people of the art
For member, without departing from the principle of the present invention, several improvement can also be made, these improvement should be regarded as guarantor of the invention
Protect range.
Claims (2)
1. a kind of semiconductor power device, which is characterized in that including semiconductor substrate, the semiconductor substrate includes heavy doping
First conductivity type substrate and the first conductive type epitaxial layer being lightly doped, first surface are the upper of the first conductive type epitaxial layer
Surface, second surface are the lower surface of the first conductivity type substrate；
First surface is provided with first groove, second groove and third groove in vertical direction, first groove and second groove it
Between, on the first surface of second groove between each other, between second groove and third groove be provided with hard mask layer；
Above first groove inner wall and its first surface of periphery, above the first surface of second groove inner wall and its periphery, the
Gate oxide is provided with above three trench walls and its first surface of periphery, first groove is interior, second groove is interior, third ditch
Fill up conductive polycrystalline silicon in slot, above first groove and its above periphery top, second groove and its periphery top, third ditch
Insulating medium layer is all covered with above slot and its above periphery top, hard mask layer；Below the first surface of first groove periphery,
The injection of the second conduction type is provided with below the first surface of second groove periphery, below the first surface of third groove periphery
Layer, the second conduction type implanted layer run through entire terminal protection area, the gate oxide lower section of first groove periphery, the second ditch
The first conduction type implanted layer, institute are provided with below the gate oxide of slot periphery, below the gate oxide of third groove periphery
The the first conduction type implanted layer stated between second groove stops partition, shape by hard mask layer and the second conduction type implanted layer
At the terminal structure with pressure-resistant function, the second conduction type implanted layer is located at the top of the first conductive type epitaxial layer；
It is covered with the first metal layer on the insulating medium layer of first groove and its periphery top, which extends downward into first
In fairlead, the first lead hole through insulating medium layer, the gate oxide of first groove periphery, first groove it is peripheral the
One conduction type implanted layer is up to the top of the second conduction type implanted layer of first groove periphery；It third groove and its places outside
It is covered with second metal layer on the insulating medium layer of side, which extends downward into the second fairlead and third lead
In hole, through insulating medium layer up to the top of conductive polycrystalline silicon in third groove, third fairlead passes through second fairlead
Wear insulating medium layer, third groove periphery and the non-conterminous hard mask layer of second groove until the second conduction type implanted layer it is upper
Portion.
2. a kind of method for preparing semiconductor power device described in claim 1, which comprises the following steps:
Step 1, providing tool, there are two the first conductive type semiconductor substrate of apparent surface, first conductive type semiconductors
Substrate includes the first conductivity type substrate of heavy doping and the first conductive type epitaxial layer being lightly doped, and defines the first conduction type
The upper surface of epitaxial layer is first surface；
Step 2 deposits hard mask layer on the first surface, goes out hard mask etching region by lithographic definition and etches hard exposure mask
Layer forms the hard exposure mask for being used for etching groove；
Step 3, etching first surface form the groove in vertical direction, and the groove includes first groove, second groove and the
Three grooves, the hard mask layer width between the second groove are greater than the hard mask layer width between first groove, and described first
Hard mask layer thickness of the hard mask layer width less than twice between groove；
Step 4, using the hard mask layer on wet etching first surface, the hard mask layer of first groove periphery etches completely, carve
The half of hard mask layer width of the erosion degree between second groove, the hard exposure mask of second groove periphery and third groove periphery
Layer partial etching, retains the portion on the first surface between first groove and second groove, between second groove and third groove
Divide hard mask layer, retains the part hard mask layer on the mutual first surface of second groove；
Step 5 grows gate oxide on the first surface, which covers the of the first groove inner wall and its periphery
One surface, the first surface of second groove inner wall and its periphery, third trench wall and its peripheral first surface；
Step 6, deposit and etching conductive polysilicon, make to fill up conductive polycrystalline in first groove, second groove and third groove
Silicon；
Step 7: injecting the second conductive type impurity from gate oxide and anneal, under the first surface of first groove periphery
The lower section of the first surface of side, the lower section of the first surface of second groove periphery, third groove periphery forms the second conduction type
Implanted layer, the second conduction type implanted layer are located at the top of the first conductive type epitaxial layer, the second conduction type implanted layer
Through terminal protection area；
Step 8: injecting the first conductive type impurity from gate oxide and anneal, under the gate oxide of first groove periphery
The lower section of the gate oxide of side, the lower section of the gate oxide of second groove periphery, third groove periphery forms the first conduction type
Implanted layer, and the first conduction type implanted layer is located on the second conduction type implanted layer, the first conduction type implanted layer passes through
Hard mask layer stops partition, prevents leak channel, forms the terminal structure with pressure-resistant function；
Step 9: depositing insulating medium layer above gate oxide, above conductive polycrystalline silicon and above hard mask layer, which is situated between
Matter layer is covered on above gate oxide, conductive polycrystalline silicon and hard mask layer；
Step 10: through hole lithographic definition goes out the region of fairlead, is sequentially etched and through insulating medium layer, first groove periphery
Gate oxide, first groove periphery the first conduction type implanted layer until first groove periphery the second conduction type injection
First lead hole in vertical direction is formed at the top of layer, and in first lead hole and its periphery deposit the first metal layer, this
One metal layer is full of first lead hole and is covered on the insulating medium layer of first lead hole periphery；
It etches and runs through insulating medium layer up to the top of the conductive polycrystalline silicon in third groove, form second in vertical direction
Fairlead is sequentially etched and through insulating medium layer, third groove periphery and the non-conterminous hard mask layer of second groove up to the
The top of two conduction type implanted layers, formed vertical direction on third fairlead, in the second fairlead and its periphery, third
In fairlead and its periphery deposit second metal layer, the second metal layer is full of the second fairlead, third fairlead and is covered on
On the insulating medium layer of second fairlead periphery and third fairlead periphery, and second metal layer and the first metal layer not phase
Even.
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| CN102832234A (en) * | 2012-09-10 | 2012-12-19 | 张家港凯思半导体有限公司 | Groove type semiconductor power device, method for producing same and terminal protection structure |
| CN209626219U (en) * | 2019-05-07 | 2019-11-12 | 张家港凯思半导体有限公司 | A kind of semiconductor power device |
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| CN102832234A (en) * | 2012-09-10 | 2012-12-19 | 张家港凯思半导体有限公司 | Groove type semiconductor power device, method for producing same and terminal protection structure |
| CN209626219U (en) * | 2019-05-07 | 2019-11-12 | 张家港凯思半导体有限公司 | A kind of semiconductor power device |
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| WO2021059046A1 (en) * | 2019-09-24 | 2021-04-01 | International Business Machines Corporation | Self-aligned top via formation at line ends |
| US11404317B2 (en) | 2019-09-24 | 2022-08-02 | International Business Machines Corporation | Method for fabricating a semiconductor device including self-aligned top via formation at line ends |
| GB2603401A (en) * | 2019-09-24 | 2022-08-03 | Ibm | Self-aligned top via formation at line ends |
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