CN110047934A - A kind of semiconductor power device and preparation method thereof for cutting down the light shield number of plies - Google Patents
A kind of semiconductor power device and preparation method thereof for cutting down the light shield number of plies Download PDFInfo
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- CN110047934A CN110047934A CN201910376363.8A CN201910376363A CN110047934A CN 110047934 A CN110047934 A CN 110047934A CN 201910376363 A CN201910376363 A CN 201910376363A CN 110047934 A CN110047934 A CN 110047934A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000005520 cutting process Methods 0.000 title claims abstract description 9
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005192 partition Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000001259 photo etching Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The present invention proposes a kind of semiconductor power device and preparation method thereof for cutting down the light shield number of plies, it opens up first groove and second groove in the first conductive type epitaxial layer upper surface of semiconductor substrate, is provided with hard mask layer between first groove and second groove, on the first surface that second groove is mutual；First groove inner wall and its periphery, second groove inner wall and its periphery are equipped with gate oxide, in first groove, fill up conductive polycrystalline silicon in second groove, are all covered with insulating medium layer above first groove and its periphery, second groove and its periphery, hard mask layer；Between first groove and its periphery, second groove periphery is equipped with the first conduction type implanted layer and the second conduction type implanted layer from top to bottom；Metal layer is covered on the insulating medium layer of first groove and its periphery top.On the basis of guaranteeing the Performance And Reliability of device, the light shield number of plies is reduced to 3 layers the present invention, and manufacturing cost is effectively reduced.
Description
Technical field
The invention belongs to technical field of semiconductors, especially a kind of semiconductor power device and its system for cutting down the light shield number of plies
Preparation Method.
Background technique
High voltage, powerful groove type MOS device products are still using six layers of photoetching even manufacture of eight layers of photoetching
Technology, it is at high cost, the manufacturing cycle is long, competitiveness is low.
" groove type high-power MOS device and its manufacturer are disclosed in existing Chinese patent ZL 201010003953.5
Method ", relate to a kind of groove type MOS device using the manufacture of 6 photoetching techniques；Its basic process steps includes:
(1), field oxide is grown
(2), active area etching (photoetching level 1)
(3), protection ring region etch, ion implanting, heat treatment form terminal protection structure (photoetching level 2)
(4), hard exposure mask growth and selective etch, define the region (photoetching level 3) of etching groove
(5), etching groove using hard mask selectivity is carried out
(6), gate oxide is grown, conductive polycrystalline silicon is deposited
(7), etching conductive polysilicon
(8), Second Type foreign ion is injected, heat treatment forms Second Type well layer
(9), it is lithographically formed first kind foreign ion injection region, injects first kind foreign ion, heat treatment is formed
First kind injection region (photoetching level 4)
(10), insulating medium layer is deposited
(11), lithographic definition lead porose area, etching form fairlead (photoetching level 5)
(12), deposited metal is lithographically formed metal electrode (photoetching level 6)
The groove type MOS device invented in patent ZL 201010003953.5, using the manufacturing technology of six photoetching,
Manufacturing cost is high, the production cycle is long, competitiveness is low.
" a kind of deep groove large power MOS device and its manufacture are disclosed in existing Chinese patent ZL 200710302461.4
Method ", relate to a kind of groove type power MOS device manufactured using four mask technology；For example described patent of its inventive structure
In ZL 200710302461.4 shown in Fig. 4, the basic thought of invention are as follows: a kind of groove type MOS device, in top plan view,
The terminal protection structure of active area comprising center and periphery；The terminal protection structure is by groove-shaped protection ring and one
Groove-shaped cut-off ring composition；The groove of the protection ring is located at the second conduction type implanted layer for being lightly doped, and depth gos deep into the
The first conduction type implanted layer below two conduction type implanted layers.
With the continuous maturation of groove type MOS device design and processes, market competition is increasingly fierce, reduces the system of device
This is caused, performance and the reliability for improving device are increasingly important.Under the premise of not influencing device performance, reduces device and manufacture work
Photoetching number in skill is to reduce one of the important means of device cost.
Summary of the invention
Technical problem solved by the invention is: providing a kind of semiconductor power device for cutting down the light shield number of plies, and should
The preparation method of semiconductor power device, manufacturing process is simple, effectively reduces manufacturing cost.
The technical solution for realizing the aim of the invention is as follows:
A kind of semiconductor power device for cutting down the light shield number of plies, including semiconductor substrate, the semiconductor substrate include weight
First conductivity type substrate of doping and the first conductive type epitaxial layer being lightly doped, first surface are the first conduction type extension
The upper surface of layer；
First surface is provided with first groove and second groove in vertical direction, between first groove and second groove,
Hard mask layer is provided on the mutual first surface of two grooves；
Above first groove inner wall and its first surface of periphery, above second groove inner wall and its peripheral first surface
It is provided with gate oxide, fills up conductive polycrystalline silicon in first groove, in second groove, place above first groove and its outside
Insulating medium layer is all covered with above side, second groove and its above periphery top, hard mask layer；It is between first groove and its outer
The first conduction type note is disposed with below the gate oxide enclosed, below the gate oxide of second groove periphery from top to bottom
Entering layer and the second conduction type implanted layer, the second conduction type implanted layer stops to separate by hard mask layer, and described second
The first conduction type implanted layer between groove stops partition by hard mask layer and the second conduction type implanted layer, and formation has
The terminal structure of pressure-resistant function；First groove and its periphery top insulating medium layer on be covered with metal layer, the metal layer to
Under extend in fairlead, the fairlead is peripheral through insulating medium layer, the gate oxide of first groove periphery, first groove
The first conduction type implanted layer until first groove periphery the second conduction type implanted layer top.
A method of preparing the semiconductor power device of the above-mentioned reduction light shield number of plies, comprising the following steps:
Step 1, providing tool, there are two the first conductive type semiconductor substrate of apparent surface, first conduction types half
Conductor substrate includes the first conductivity type substrate of heavy doping and the first conductive type epitaxial layer being lightly doped, and it is conductive to define first
The upper surface of type epitaxial layer is first surface；
Step 2 deposits hard mask layer on the first surface, goes out hard mask etching region by lithographic definition and etches and covers firmly
Film layer forms the hard exposure mask for being used for etching groove；
Step 3, etching first surface form the groove in vertical direction, and the groove includes first groove and the second ditch
Slot；Hard mask layer width between the second groove is greater than the hard mask layer width between first groove, the first groove
Between hard mask layer thickness of the hard mask layer width less than twice.
Step 4, using the hard mask layer on wet etching first surface, hard mask layer of the etching degree between second groove
The hard mask layer of the half of width, first groove periphery etches completely, the hard mask layer partial etching of second groove periphery,
Retain the part hard mask layer on the first surface between first groove and second groove, retain second groove it is mutual the
Part hard mask layer on one surface；
Step 5 grows gate oxide on the first surface, which covers the first groove inner wall and its periphery
First surface, second groove inner wall and its periphery first surface；
Step 6, deposit and etching conductive polysilicon, make to fill up conductive polycrystalline silicon in first groove and second groove；
Step 7: inject the second conductive type impurity from gate oxide and anneal, between first groove and its periphery
The lower section of gate oxide, the lower section of the gate oxide of second groove periphery form the second conduction type implanted layer, and described second leads
Electric type implanted layer is located at the top of the first conductive type epitaxial layer；Second conduction type implanted layer by hard mask layer stop every
It is disconnected.
Step 8: inject the first conductive type impurity from gate oxide and anneal, between first groove and its periphery
The lower section of gate oxide, the lower section of the gate oxide of second groove periphery form the first conduction type implanted layer, and first is conductive
Type implanted layer is located on the second conduction type implanted layer；First conduction type implanted layer stops to separate by hard mask layer,
Leak channel is prevented, the terminal structure with pressure-resistant function is formed.
Step 9: depositing insulating medium layer above gate oxide, above conductive polycrystalline silicon and above hard mask layer, this is absolutely
Edge dielectric layer covers above gate oxide, conductive polycrystalline silicon and hard mask layer；
Step 10: through hole lithographic definition goes out the region of fairlead, is sequentially etched and through insulating medium layer, first groove
Second conduction type of the first conduction type implanted layer of peripheral gate oxide, first groove periphery up to first groove periphery
Fairlead is formed at the top of implanted layer, and in fairlead and its peripheral deposited metal, the metal layer are full of fairlead and covering
On the insulating medium layer of fairlead periphery.
The invention adopts the above technical scheme compared with prior art, and what is had has the technical effect that the present invention is guaranteeing device
On the basis of the Performance And Reliability of part, the light shield number of plies is reduced to 3 layers, and manufacturing cost is effectively reduced.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that hard mask layer is deposited on semiconductor substrate first surface；
Fig. 2 is the structural schematic diagram etched after first groove and second groove；
Fig. 3 is the structural schematic diagram etched after hard mask layer；
Fig. 4 is the structural schematic diagram grown after gate oxide；
Fig. 5 is the structural schematic diagram after deposit and etching conductive polysilicon；
Fig. 6 is the structural schematic diagram after injecting p-type foreign ion；
Fig. 7 is the structural schematic diagram injected after N-type impurity ion；
Fig. 8 is the structural schematic diagram deposited after insulating medium layer；
Fig. 9 is the structural schematic diagram after deposited metal；
Appended drawing reference meaning: 1:N type substrate, 2:N type epitaxial layer, 3: first groove, 4: second groove, 5: hard mask layer,
6: gate oxide, 7: conductive polycrystalline silicon, 8: insulating medium layer, 9:P type implanted layer, 10:N type implanted layer, 11: metal layer, 12: drawing
String holes.
Specific embodiment
Embodiments of the present invention are described below in detail, the example of the embodiment is shown in the accompanying drawings, wherein from beginning
Same or similar element or element with the same or similar functions are indicated to same or similar label eventually.Below by ginseng
The embodiment for examining attached drawing description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
A kind of semiconductor power device for cutting down the light shield number of plies provided by the invention, as shown in fig. 9, it includes semiconductor-based
Plate, the semiconductor substrate include the N-type substrate 1 of heavy doping and the N-type epitaxy layer 2 being lightly doped, and first surface is N-type epitaxy layer
2 upper surface, second surface are the lower surface of the first conductivity type substrate；
First surface is provided with first groove 3 and second groove 4 in vertical direction, first groove 3 and second groove 4 it
Between, on the mutual first surface of second groove 4 be provided with hard mask layer 5；
Above 3 inner wall of first groove and its first surface of periphery, on 4 inner wall of second groove and its peripheral first surface
Side is provided with gate oxide 6, fills up conductive polycrystalline silicon 7 in first groove 3, in second groove 4,3 top of first groove and
Insulating medium layer 8 is all covered with above its periphery, above 4 top of second groove and its periphery top, hard mask layer 5；First ditch
6 lower section of gate oxide of between slot 3 and its periphery, 6 lower section of gate oxide of 4 periphery of second groove are set gradually from top to bottom
Have a N-type implanted layer 10 and p-type implanted layer 9, the p-type implanted layer 9 stops partition by hard mask layer 5, the second groove 4 it
Between N-type implanted layer 10 partition is stopped by hard mask layer 5 and p-type implanted layer 9, form the terminal structure with pressure-resistant function；
It is covered with metal layer 11 on the insulating medium layer 8 of first groove 3 and its periphery top, which extends downward into fairlead
In 12, the fairlead 12 N-type peripheral through insulating medium layer 8, the gate oxide 6 of 3 periphery of first groove, first groove 3
Implanted layer 10 is up to the top of the p-type implanted layer 9 of 3 periphery of first groove.
A kind of method that the present invention also proposes semiconductor power device for preparing the above-mentioned reduction light shield number of plies, including following step
It is rapid:
Step 1 provides tool there are two the N-type semiconductor substrate of apparent surface, and the N-type semiconductor substrate includes heavy doping
N-type substrate 1 and the N-type epitaxy layer 2 that is lightly doped, the upper surface for defining N-type epitaxy layer 2 is first surface, as shown in Figure 1；
Step 2 deposits hard mask layer 5 on the first surface, as shown in Figure 1, passing through lithographic definition Chu Ying mask etching area
Domain simultaneously etches hard mask layer 5, forms the hard exposure mask for being used for etching groove；
Step 3, etching first surface form the groove in vertical direction, and the groove includes first groove 3 and the second ditch
Slot 4, as shown in Fig. 2, the hard mask layer 5 that 5 width of hard mask layer between the second groove 4 is greater than between first groove 3 is wide
It spends, hard mask layer 5 thickness of 5 width of hard mask layer less than twice between the first groove 3；
Step 4, using the hard mask layer 5 on wet etching first surface, hard exposure mask of the etching degree between second groove 4
The hard mask layer 5 of the half of 5 width of layer, 3 periphery of first groove etches completely, and hard mask layer 5 of 4 periphery of second groove
Divide etching, retain the part hard mask layer 5 on the first surface between first groove 3 and second groove 4, retains second groove 4
Part hard mask layer 5 on mutual first surface, as shown in Figure 3；
Step 5, on the first surface grow gate oxide 6, the gate oxide 6 cover 3 inner wall of first groove and its
First surface, 4 inner wall of second groove and its first surface of periphery of periphery, as shown in Figure 4；
Step 6, deposit and etching conductive polysilicon 7, make to fill up conductive polycrystalline silicon 7 in first groove 3 and second groove 4,
As shown in Figure 5；
Step 7: from injecting p-type impurity on gate oxide 6 and anneal, between first groove 3 and its periphery gate oxidation
The lower section of layer 6, the lower section of the gate oxide 6 of 4 periphery of second groove form p-type implanted layer 9, and the p-type implanted layer 9 is located at N-type
The top of epitaxial layer 2, p-type implanted layer 9 stop partition by hard mask layer 5, as shown in Figure 6；
Step 8: injecting and N-type impurity and anneal from gate oxide 6, between first groove 3 and its gate oxidation of periphery
The lower section of layer 6, the lower section of the gate oxide 6 of 4 periphery of second groove form N-type implanted layer 10, and N-type implanted layer 10 is located at p-type
On implanted layer 9, N-type implanted layer 10 stops partition by hard mask layer 5, prevents leak channel, and being formed has pressure-resistant function
Terminal structure, as shown in Figure 7；
Step 9: above gate oxide 6, insulating medium layer 8 is deposited above conductive polycrystalline silicon 7 and above hard mask layer 5,
The insulating medium layer 8 covers 5 top of gate oxide 6, conductive polycrystalline silicon 7 and hard mask layer, as shown in Figure 8；
Step 10: through hole lithographic definition goes out the region of fairlead 12, is sequentially etched and through insulating medium layer 8, first
P-type implanted layer 10 of the peripheral N-type implanted layer 10 of the gate oxide 6 of 3 periphery of groove, first groove 3 up to 3 periphery of first groove
Top, form fairlead 12, in fairlead 12 and its peripheral deposited metal 11, the metal layer 11 full of fairlead 12 and
It is covered on the insulating medium layer 8 of 12 periphery of fairlead, as shown in Figure 9.
The above is only some embodiments of the invention, it is noted that for the ordinary skill people of the art
For member, without departing from the principle of the present invention, several improvement can also be made, these improvement should be regarded as guarantor of the invention
Protect range.
Claims (2)
1. a kind of semiconductor power device for cutting down the light shield number of plies, which is characterized in that described semiconductor-based including semiconductor substrate
Plate includes the first conductivity type substrate of heavy doping and the first conductive type epitaxial layer being lightly doped, and first surface is first conductive
The upper surface of type epitaxial layer, second surface are the lower surface of the first conductivity type substrate；
First surface is provided with first groove and second groove in vertical direction, between first groove and second groove, the second ditch
Hard mask layer is provided on the mutual first surface of slot；
It is all provided with above first groove inner wall and its first surface of periphery, above second groove inner wall and its peripheral first surface
It is equipped with gate oxide, fills up conductive polycrystalline silicon in first groove, in second groove, above first groove and its periphery top,
Insulating medium layer is all covered with above second groove and its above periphery top, hard mask layer；Between first groove and its periphery
Gate oxide below, be disposed with the first conduction type from top to bottom below the gate oxide of second groove periphery and inject
Layer and the second conduction type implanted layer, the second conduction type implanted layer stop to separate by hard mask layer, second ditch
The first conduction type implanted layer between slot stops partition by hard mask layer and the second conduction type implanted layer, is formed with resistance to
Press the terminal structure of function；It is covered with metal layer on the insulating medium layer of first groove and its periphery top, the metal layer is downward
It extends in fairlead, the fairlead is through insulating medium layer, the gate oxide of first groove periphery, first groove peripheral
First conduction type implanted layer is up to the top of the second conduction type implanted layer of first groove periphery.
2. a kind of method for preparing the semiconductor power device described in claim 1 for cutting down the light shield number of plies, which is characterized in that packet
Include following steps:
Step 1, providing tool, there are two the first conductive type semiconductor substrate of apparent surface, first conductive type semiconductors
Substrate includes the first conductivity type substrate of heavy doping and the first conductive type epitaxial layer being lightly doped, and defines the first conduction type
The upper surface of epitaxial layer is first surface；
Step 2 deposits hard mask layer on the first surface, goes out hard mask etching region by lithographic definition and etches hard exposure mask
Layer forms the hard exposure mask for being used for etching groove；
Step 3, etching first surface form the groove in vertical direction, and the groove includes first groove and second groove, institute
The hard mask layer width that hard mask layer width between second groove is greater than between first groove is stated, between the first groove
Hard mask layer thickness of the hard mask layer width less than twice；
Step 4, using the hard mask layer on wet etching first surface, hard mask layer width of the etching degree between second groove
Half, the hard mask layer of first groove periphery etches completely, the hard mask layer partial etching of second groove periphery, retains
Part hard mask layer on first surface between first groove and second groove retains the first mutual table of second groove
Part hard mask layer on face；
Step 5 grows gate oxide on the first surface, which covers the of the first groove inner wall and its periphery
The first surface on one surface, second groove inner wall and its periphery；
Step 6, deposit and etching conductive polysilicon, make to fill up conductive polycrystalline silicon in first groove and second groove；
Step 7: inject the second conductive type impurity from gate oxide and anneal, between first groove and its periphery grid oxygen
Change the lower section of layer, the lower section of the gate oxide of second groove periphery forms the second conduction type implanted layer, second conductive-type
Type implanted layer is located at the top of the first conductive type epitaxial layer, and the second conduction type implanted layer stops to separate by hard mask layer；
Step 8: inject the first conductive type impurity from gate oxide and anneal, between first groove and its periphery grid oxygen
Change the lower section of layer, the lower section of the gate oxide of second groove periphery forms the first conduction type implanted layer, and the first conduction type
Implanted layer is located on the second conduction type implanted layer, and the first conduction type implanted layer stops to separate by hard mask layer, prevents
Leak channel forms the terminal structure with pressure-resistant function；
Step 9: depositing insulating medium layer above gate oxide, above conductive polycrystalline silicon and above hard mask layer, which is situated between
Matter layer covers above gate oxide, conductive polycrystalline silicon and hard mask layer；
Step 10: through hole lithographic definition goes out the region of fairlead, is sequentially etched and through insulating medium layer, first groove periphery
Gate oxide, first groove periphery the first conduction type implanted layer until first groove periphery the second conduction type injection
Fairlead is formed at the top of layer, and in fairlead and its peripheral deposited metal, which draws full of fairlead and being covered on
On the insulating medium layer of string holes periphery.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832234A (en) * | 2012-09-10 | 2012-12-19 | 张家港凯思半导体有限公司 | Groove type semiconductor power device, method for producing same and terminal protection structure |
| CN103151381A (en) * | 2013-02-02 | 2013-06-12 | 张家港凯思半导体有限公司 | Groove type semiconductor power device and manufacturing method and terminal protection structure thereof |
| CN105826205A (en) * | 2016-05-31 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid power device and structure |
| CN106449753A (en) * | 2016-07-14 | 2017-02-22 | 中航（重庆）微电子有限公司 | Low on-state resistance groove power MOS (Metal Oxide Semiconductor) device structure and fabrication method thereof |
| CN109103238A (en) * | 2018-08-14 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | Groove MOSFET and its manufacturing method |
| CN209626228U (en) * | 2019-05-07 | 2019-11-12 | 张家港凯思半导体有限公司 | A kind of semiconductor power device for cutting down the light shield number of plies |
-
2019
- 2019-05-07 CN CN201910376363.8A patent/CN110047934B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832234A (en) * | 2012-09-10 | 2012-12-19 | 张家港凯思半导体有限公司 | Groove type semiconductor power device, method for producing same and terminal protection structure |
| CN103151381A (en) * | 2013-02-02 | 2013-06-12 | 张家港凯思半导体有限公司 | Groove type semiconductor power device and manufacturing method and terminal protection structure thereof |
| CN105826205A (en) * | 2016-05-31 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid power device and structure |
| CN106449753A (en) * | 2016-07-14 | 2017-02-22 | 中航（重庆）微电子有限公司 | Low on-state resistance groove power MOS (Metal Oxide Semiconductor) device structure and fabrication method thereof |
| CN109103238A (en) * | 2018-08-14 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | Groove MOSFET and its manufacturing method |
| CN209626228U (en) * | 2019-05-07 | 2019-11-12 | 张家港凯思半导体有限公司 | A kind of semiconductor power device for cutting down the light shield number of plies |
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