CN111509035B - Low-cost high-performance groove type power semiconductor device and preparation method thereof - Google Patents

Low-cost high-performance groove type power semiconductor device and preparation method thereof Download PDF

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CN111509035B
CN111509035B CN202010351900.6A CN202010351900A CN111509035B CN 111509035 B CN111509035 B CN 111509035B CN 202010351900 A CN202010351900 A CN 202010351900A CN 111509035 B CN111509035 B CN 111509035B
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substrate
cell
groove
region
terminal
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CN111509035A (en
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杨飞
白玉明
张广银
吴凯
朱阳军
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Jiangsu Chip Long March Microelectronics Group Co ltd
Nanjing Xinchangzheng Technology Co ltd
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Nanjing Xinchangzheng Technology Co ltd
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Abstract

The invention relates to a trench type power semiconductor device and a preparation method thereof, in particular to a low-cost high-performance trench type power semiconductor device and a preparation method thereof, and belongs to the technical field of trench type power semiconductor devices. After at least one substrate second conductive type injection region is arranged between the substrate cell second groove and the terminal region, breakdown at the groove bottom of the substrate cell second groove in the withstand voltage process can be prevented, the withstand voltage of the terminal region is fully increased, the junction depth requirement of the substrate terminal second conductive type body region can be reduced, the design freedom is improved, the power semiconductor device has higher breakdown voltage and reliability, or under the same breakdown voltage, the area of the device can be further reduced, the cost is reduced, and the reliability of the power semiconductor device is improved.

Description

Low-cost high-performance groove type power semiconductor device and preparation method thereof
Technical Field
The invention relates to a trench type power semiconductor device and a preparation method thereof, in particular to a low-cost high-performance trench type power semiconductor device and a preparation method thereof, and belongs to the technical field of trench type power semiconductor devices.
Background
At present, power semiconductor devices are rapidly developed, and on one hand, technologies of an igbt (insulated Gate Bipolar transistor) and a VDMOS are continuously innovated to realize excellent performance; on the other hand, low cost is also a pursuit goal for the development of power semiconductors. In the processing cost of the power semiconductor, the cost of the mask and the corresponding photolithography process are often the main factors, and therefore, reducing the number of masks becomes the key to reducing the cost of the device. In most cases, there is often a trade-off between high performance devices and low cost unless new devices, processes, etc. are present.
Referring to fig. 1 to fig. 9, which are cross-sectional views illustrating specific steps of a manufacturing process of a front structure of a conventional trench type power semiconductor device, taking an N type power semiconductor device as an example, specifically,
as shown in fig. 1, an N-type semiconductor substrate 1 is provided, a first substrate photoresist layer 2 is coated on the front surface of the semiconductor substrate 1, and the first substrate photoresist layer 2 is subjected to photolithography by using a first substrate mask 3 to obtain a first substrate photoresist layer window 6 penetrating through the first substrate photoresist layer 2. And performing groove etching on the semiconductor substrate 1 by using the substrate first photoresist layer 2 and the substrate first photoresist layer window 6 to obtain a substrate cell groove 4 and a substrate terminal groove 5 which are positioned in the semiconductor substrate 1.
As shown in fig. 2, the substrate first photoresist layer 2 is removed by a conventional technique in the art, and thermal oxidation is performed on the front surface of the semiconductor substrate 1 to obtain a substrate cell trench insulating oxide layer 7 covering the sidewalls and bottom walls of the substrate cell trench 4 and a substrate terminal trench insulating oxide layer 9 covering the sidewalls and bottom walls of the substrate terminal trench 5.
After obtaining a substrate cell trench insulating oxide layer 7 and a substrate terminal trench insulating oxide layer 9, conducting polycrystalline silicon deposition is carried out on the front surface of the semiconductor substrate 1 to obtain a substrate cell trench polycrystalline silicon body 8 filled in the substrate cell trench 4 and a substrate terminal trench conducting polycrystalline silicon 10 filled in the substrate terminal trench 5, wherein the substrate cell trench polycrystalline silicon body 8 is insulated and isolated from the side wall and the bottom wall of the substrate cell trench 4 through the substrate cell trench insulating oxide layer 7; the substrate termination trench polysilicon body 10 can be insulated from the sidewalls and bottom wall of the substrate termination trench 5 by a substrate termination trench insulating oxide layer 9.
As shown in fig. 3, P-type impurity ions are implanted into the front surface of the semiconductor substrate 1 to obtain a P-type substrate layer 11 on the upper portion of the semiconductor substrate 1, wherein the P-type substrate layer 11 penetrates through the front surface of the semiconductor substrate 1, the P-type substrate layer 11 extends vertically downward from the front surface of the semiconductor substrate 1, and the P-type substrate layer 11 is located above the bottom of the corresponding substrate cell trench 4 and substrate termination trench 5.
As shown in fig. 4, a second photoresist layer 12 is formed on the front surface of the semiconductor substrate 1, and the second photoresist layer 12 is subjected to photolithography using a second reticle 13.
As shown in fig. 5, by using the substrate second photoresist layer 12 to shield the semiconductor substrate 1, P-type impurity ions, N-type impurity ions are implanted into the front surface of the semiconductor substrate 1 and pushed into the well, so as to obtain a substrate P-type base region 15 and a substrate N + source region 16 located above the substrate P-type base region 15 in the central region of the semiconductor substrate 1, the substrate N + source region 16 is adjacent to the substrate P-type base region 15, and the substrate P-type base region 15 is located above the bottom of the substrate unit cell trench 4. Meanwhile, after the substrate P-type base region 15 is obtained, the substrate P-type body region 14 can be obtained by using the substrate P-type layer 11 of the termination region of the semiconductor substrate 1.
As shown in fig. 6, the substrate second photoresist layer 12 is removed, and an insulating dielectric layer is deposited on the front surface of the semiconductor substrate 1, so as to obtain a substrate insulating dielectric layer 17 covering the front surface of the semiconductor substrate 1. After the substrate insulating medium layer 17 is obtained, a substrate third photoresist layer 18 is obtained by coating on the substrate insulating medium layer 17, and the substrate third photoresist layer 18 can be subjected to photoetching by using a substrate third mask 19 to obtain a plurality of substrate third photoresist layer windows 20 penetrating through the substrate third photoresist layer 18.
As shown in fig. 7, the substrate insulating dielectric layer 17 is etched by using the substrate third photoresist layer 18 and the substrate third photoresist layer window 20, so as to obtain a substrate source contact hole 21 penetrating through the substrate insulating dielectric layer 17, where the substrate source contact hole 21 is directly corresponding to the substrate third photoresist layer window 20, and the substrate source contact hole 21 further penetrates through the substrate N + source region 16 below the substrate insulating dielectric layer 17.
As shown in fig. 8, the third photoresist layer 18 is removed and metal deposition is performed on the front surface of the semiconductor substrate 1 to obtain a front surface metal layer covering the bottom of the substrate insulating dielectric layer 17.
After obtaining the substrate front metal layer, coating the substrate front metal layer to obtain a substrate fourth photoresist layer 21, and performing photolithography on the substrate fourth photoresist layer 21 by using a substrate fourth mask 22 to obtain a substrate fourth photoresist layer window 24 penetrating through the substrate fourth photoresist layer 21.
And etching the substrate front metal layer by using the substrate fourth photoresist layer 21 and the substrate fourth photoresist layer window 24 to obtain a substrate front metal layer window 23 penetrating through the substrate front metal layer, and dividing the substrate front metal layer by using the substrate front metal layer window 23 to obtain a substrate front cellular metal layer 65 and a substrate front terminal metal layer 68, wherein the substrate front cellular metal layer 65 can be in ohmic contact with the substrate N + source region 16 and the substrate P-type base region 15, and the substrate terminal metal layer 20 is positioned at the outer ring of the central region of the semiconductor substrate 1.
As shown in fig. 9, a passivation material is deposited over the front surface of the semiconductor substrate 1 to obtain a substrate passivation layer 25 on the front surface of the semiconductor substrate 1, the substrate passivation layer 25 overlying the substrate front surface cell metal layer 65 and the substrate front surface terminal metal layer 68.
Coating the substrate passivation layer 25 to obtain a substrate fifth photoresist layer 26, photoetching the substrate fifth photoresist layer 26 by using a substrate fifth mask 27 to obtain a substrate fifth photoresist layer window 28 penetrating through the substrate fifth photoresist layer 26, etching the substrate passivation layer 25 by using the substrate fifth photoresist layer 26 and the substrate fifth photoresist layer window 28 to obtain a substrate passivation layer window 29 penetrating through the substrate passivation layer 25, and exposing the cell metal layer 65 on the front surface of the substrate by using the substrate passivation layer window 29.
After the above steps are performed, the substrate fifth photoresist layer 26 needs to be removed, and a required back surface process is performed on the back surface of the semiconductor substrate 1 to obtain a required back surface structure, and an IGBT device or a MOSFET device can be prepared according to the difference of the back surface structures.
As can be seen from the above specific process steps, the substrate P-type layer 11 is prepared on the upper portion of the semiconductor substrate 1, and then the substrate P-type base region 15 and the substrate P-type body region 14 can be formed through the substrate P-type layer 11, and the substrate P-type layer 11 is obtained by implanting P-type impurity ions on the entire front surface of the semiconductor substrate 1. In order to achieve a relatively high breakdown voltage, the junction depth of the substrate P-type layer 11 after being pushed into the well cannot be much different from the depths of the substrate cell trench 4 and the substrate terminal trench 5 in the semiconductor substrate 1, otherwise, the prepared semiconductor device is prone to breakdown at the bottom of the substrate cell trench 4 adjacent to the substrate terminal trench 5, such as the breakdown region 30 in fig. 10.
When the terminal breakdown voltage is improved by increasing the junction depth of the substrate P-type layer 11, the junction depth of the basic P-type base region 15 in the substrate cell region is correspondingly increased, which may result in the increase of the channel length of the cell region of the device and the appearance of the JFET effect, thereby increasing the on-state voltage drop of the device. Therefore, the closest prior art has a trade-off between achieving the minimum on-state voltage drop and the highest BV, and cannot achieve the optimal values at the same time.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a low-cost high-performance groove type power semiconductor device and a preparation method thereof, which can realize higher breakdown voltage, improve the working reliability of the power semiconductor device and are compatible with the prior art.
According to the technical scheme provided by the invention, the low-cost high-performance groove type power semiconductor device comprises a semiconductor substrate with a first conduction type, a cell area arranged in the center area of the semiconductor substrate and a terminal area arranged on the semiconductor substrate and positioned at the outer ring of the cell area; the cells in the cell area adopt a groove structure;
on the top plan of the power semiconductor device, the unit cells of the unit cell area comprise annular substrate unit cell second grooves and a plurality of substrate unit cell first grooves positioned at the inner rings of the annular substrate unit cell second grooves, and the terminal area is positioned at the outer rings of the annular substrate unit cell second grooves;
on the cross section of the power semiconductor device, a substrate second conduction type base region and a substrate first conduction type source region are arranged on two sides of a substrate cell first groove, the substrate second conduction type base region is located above the corresponding groove bottoms of the substrate cell first groove and the substrate cell second groove, and the substrate second conduction type base region and the substrate first conduction type source region are in contact with the corresponding side walls of the adjacent substrate cell first groove;
on the cross section of the power semiconductor device, the outer side wall of a substrate cell second groove adjacent to a substrate cell first groove is contacted with a corresponding substrate second conduction type base region and a substrate first conduction type source region, at least one substrate second conduction type injection region is arranged between the side wall of the substrate cell second groove adjacent to a terminal region and the terminal region, the outer side wall of the substrate cell second groove adjacent to the terminal region is contacted with an adjacent substrate second conduction type injection region, and the depth of the substrate second conduction type injection region in a semiconductor substrate is greater than the depth of the substrate cell first groove and the substrate cell second groove in the semiconductor substrate;
and arranging a substrate front cell metal layer above the front surface of the semiconductor substrate, wherein the substrate front cell metal layer can be in ohmic contact with the substrate second conduction type base region, the substrate first conduction type source region and the substrate second conduction type injection region which is in contact with the side wall of the substrate cell second groove.
Substrate cell insulating oxide layers cover the corresponding inner side walls and the bottom walls of the first substrate cell grooves and the second substrate cell grooves, and substrate cell groove polycrystalline silicon is filled in the first substrate cell grooves and the second substrate cell grooves; the substrate cell groove polysilicon filled in the substrate cell first groove is insulated and isolated from the inner side wall and the bottom wall of the filled substrate cell first groove through a substrate cell insulation oxidation layer in the filled substrate cell first groove, and the substrate cell groove polysilicon filled in the substrate cell second groove is insulated and isolated from the inner side wall and the bottom wall of the filled substrate cell second groove through a substrate cell insulation oxidation layer in the filled substrate cell second groove;
the notches corresponding to the first groove and the second groove of the substrate unit cell are covered by a substrate insulating medium layer covering the front surface of the semiconductor substrate, and the substrate unit cell groove polycrystalline silicon in the first groove of the substrate unit cell and the substrate unit cell groove polycrystalline silicon in the second groove of the substrate unit cell can be insulated and isolated from the cell metal layer on the front surface of the substrate through the substrate insulating medium layer.
The substrate front side cell metal layer is supported on the substrate insulating medium layer, a substrate front side terminal metal layer is further arranged on the substrate insulating medium layer, the substrate front side terminal metal layer and the substrate front side cell metal layer are separated through a substrate metal passivation layer, and the substrate metal passivation layer is supported on the substrate front side terminal metal layer and the substrate front side cell metal layer;
the substrate passivation layer window penetrates through the substrate metal passivation layer, and the substrate front cell metal layer corresponding to the substrate passivation layer window can be exposed through the substrate passivation layer window.
On the cross section of the power semiconductor device, the terminal area comprises at least one substrate terminal groove and substrate terminal second conduction type body areas positioned on two sides of the substrate terminal groove, and the substrate terminal second conduction type body areas are positioned above the groove bottoms corresponding to the substrate terminal groove, the substrate cellular first groove and the substrate cellular second groove;
arranging substrate terminal insulating oxide layers on the side wall and the bottom wall of the substrate terminal groove, filling substrate terminal groove polycrystalline silicon in the substrate terminal groove provided with the substrate terminal insulating oxide layers, and insulating and isolating the substrate terminal groove polycrystalline silicon from the side wall and the bottom wall of the substrate terminal groove through the substrate terminal insulating oxide layers; and the notch of the substrate terminal groove is covered by a substrate insulating medium layer.
On the cross section of the power semiconductor device, a cell edge transition region groove is further included in the cell region, the cell edge transition region groove is located between a substrate cell second groove and a terminal region, the depth of a substrate second conduction type injection region in the semiconductor substrate is larger than that of the cell edge transition region groove in the semiconductor substrate, and the substrate second conduction type injection region in contact with the side wall of the substrate cell second groove wraps the outer side wall of the cell edge transition region groove;
the bottom of the cell edge transition region groove is located below the substrate second conduction type base region, substrate cell insulating oxide layers are arranged on the inner side wall and the bottom wall of the cell edge transition region groove, substrate cell groove polycrystalline silicon is filled in the cell edge transition region groove provided with the substrate cell insulating oxide layers, and the substrate cell groove polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove through the substrate cell insulating oxide layers in the cell edge transition region groove.
A preparation method of a low-cost high-performance groove type power semiconductor device comprises the following steps:
step 1, providing a semiconductor substrate with a first conductive type, and carrying out required groove etching on the front surface of the semiconductor substrate to obtain a first groove of a substrate cellular and a second groove of the substrate cellular in a cellular area of the semiconductor substrate, wherein the second groove of the substrate cellular is adjacent to a terminal area;
step 2, arranging substrate cell insulating oxide layers in the substrate cell first grooves and the substrate cell second grooves, and filling substrate cell groove polycrystalline silicon in the substrate cell first grooves and the substrate cell second grooves; covering the corresponding side walls and bottom walls of the first grooves and the second grooves of the substrate unit cells on the substrate unit cell insulating oxide layer;
the substrate cell groove polysilicon filled in the substrate cell first groove is insulated and isolated from the side wall and the bottom wall of the filled substrate cell first groove through a substrate cell insulation oxidation layer in the filled substrate cell first groove, and the substrate cell groove polysilicon filled in the substrate cell second groove is insulated and isolated from the side wall and the bottom wall of the filled substrate cell second groove through a substrate cell insulation oxidation layer in the filled substrate cell second groove;
step 3, preparing a substrate second conductive type base region, a substrate first conductive type source region and at least one substrate second conductive type injection region in the semiconductor substrate; the substrate second conduction type base region is positioned above the corresponding groove bottoms of the substrate cell first groove and the substrate cell second groove, the substrate first conduction type source region is positioned above the substrate second conduction type base region, the substrate second conduction type injection region is positioned between the substrate cell second groove and the terminal region, and the depth of the substrate second conduction type injection region in the semiconductor substrate is greater than that of the substrate cell first groove and the substrate cell second groove in the semiconductor substrate;
the substrate second conduction type injection region adjacent to the substrate cell second groove is contacted with the outer side wall of the substrate cell second groove adjacent to the terminal region, the outer side wall of the substrate cell second groove adjacent to the substrate cell first groove is contacted with the substrate second conduction type base region and the substrate first conduction type source region, and the outer side wall of the substrate cell first groove is contacted with the corresponding substrate second conduction type base region and the substrate first conduction type source region;
step 4, carrying out dielectric layer deposition on the front surface of the semiconductor substrate to obtain a substrate insulating dielectric layer covering the front surface of the semiconductor substrate; etching a contact hole on the substrate insulating medium layer to obtain a substrate source contact hole penetrating through the substrate insulating medium layer;
step 5, performing metal deposition on the front surface of the semiconductor substrate to obtain a substrate front surface metal layer, wherein the substrate front surface metal layer covers the substrate insulating medium layer, the substrate front surface cellular metal layer and the substrate front surface terminal metal layer can be obtained after etching the substrate front surface metal layer, the substrate front surface cellular metal layer and the substrate front surface terminal metal layer cover the substrate insulating medium layer, and the substrate front surface cellular metal layer is also filled in the substrate source electrode contact hole; the substrate front cell metal layer filled in the substrate source electrode contact hole is in ohmic contact with the substrate second conduction type base region, the substrate first conduction type source region and the substrate second conduction type injection region in contact with the side wall of the substrate cell second groove;
step 6, carrying out passivation layer deposition on the front surface of the semiconductor substrate to obtain a substrate metal passivation layer, wherein the substrate metal passivation layer covers the substrate front surface cellular metal layer and the substrate front surface terminal metal layer, and the substrate front surface cellular metal layer and the substrate front surface terminal metal layer can be separated by the substrate metal passivation layer;
step 7, etching the substrate metal passivation layer to obtain a substrate metal passivation layer window penetrating through the substrate metal passivation layer, wherein the substrate front cellular metal layer corresponding to the substrate metal passivation layer window can be exposed through the substrate metal passivation layer window;
and 8, performing a required back surface process on the back surface of the semiconductor substrate to obtain a required substrate back surface structure on the back surface of the semiconductor substrate.
When the groove etching is carried out on the semiconductor substrate, a substrate terminal groove positioned in a terminal area can be obtained, a substrate terminal insulating oxide layer and substrate terminal groove polycrystalline silicon filled in the substrate terminal groove are prepared in the substrate terminal groove, and the substrate terminal groove polycrystalline silicon is insulated and isolated from the inner side wall and the bottom wall of the substrate terminal groove through the substrate terminal insulating oxide layer;
and 3, when the substrate second conduction type base region is prepared, a substrate terminal second conduction type body region penetrating through the terminal region can be obtained at the same time, the substrate terminal second conduction type body region is positioned above the groove bottom of the substrate terminal groove, and the doping concentration of the substrate terminal second conduction type body region is smaller than that of the substrate second conduction type base region.
The step 3 specifically comprises the following steps:
step 3.1, injecting second conductive type impurity ions above the front surface of the semiconductor substrate to prepare at least one substrate second conductive type injection region between the substrate cellular second groove and the substrate terminal groove adjacent to the cellular region, wherein the substrate second conductive type injection region adjacent to the substrate cellular second groove is in contact with the side wall of the substrate cellular second groove adjacent to the terminal region, and the depth of the substrate second conductive type injection region in the semiconductor substrate is greater than the depth of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove in the semiconductor substrate;
step 3.2, performing second conductive type impurity ion implantation on the front surface of the semiconductor substrate again to obtain a substrate second conductive type layer penetrating through the semiconductor substrate, wherein the substrate second conductive type layer is positioned above the corresponding groove bottoms of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove;
step 3.3, performing first conductive type impurity ion implantation and second conductive type impurity ion implantation above the semiconductor substrate, obtaining a substrate second conductive type base region positioned in the cell region by utilizing the implanted second conductive type impurity ions and the substrate second conductive type layer in the cell region, obtaining a substrate first conductive type source region positioned above the substrate second conductive type base region by utilizing the implanted first conductive type impurity ions, and enabling the substrate first conductive type source region to be adjacent to the substrate second conductive type base region; meanwhile, a substrate terminal second conductive type body region can be obtained by utilizing the substrate second conductive type layer in the terminal region.
The step 3 specifically comprises the following steps:
step 3.a, performing second conductive type impurity ion implantation on the front surface of the semiconductor substrate to obtain a substrate second conductive type layer penetrating through the semiconductor substrate, wherein the substrate second conductive type layer is positioned above the corresponding groove bottoms of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove;
step 3.b, injecting second conductive type impurity ions again above the front surface of the upper semiconductor substrate to prepare at least one substrate second conductive type injection region between the substrate cellular second groove and the substrate terminal groove adjacent to the cellular region, wherein the substrate second conductive type injection region adjacent to the substrate cellular second groove is contacted with the side wall of the substrate cellular second groove adjacent to the terminal region, and the depth of the substrate second conductive type injection region in the semiconductor substrate is greater than the depth of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove in the semiconductor substrate;
step 3, c, performing first conductive type impurity ion implantation and second conductive type impurity ion implantation above the semiconductor substrate, obtaining a substrate second conductive type base region positioned in the cell region by utilizing the implanted second conductive type impurity ions and the substrate second conductive type layer in the cell region, obtaining a substrate first conductive type source region positioned above the substrate second conductive type base region by utilizing the implanted first conductive type impurity ions, and enabling the substrate first conductive type source region to be adjacent to the substrate second conductive type base region; meanwhile, a substrate terminal second conductive type body region can be obtained by utilizing the substrate second conductive type layer in the terminal region.
When the groove etching is carried out on the semiconductor substrate, a cell edge transition region groove positioned in a cell region can be obtained, the cell edge transition region groove is positioned between a second groove of a substrate cell and a terminal region, the depth of a second conductive type injection region of the substrate in the semiconductor substrate is greater than that of the cell edge transition region groove in the semiconductor substrate, and the second conductive type injection region of the substrate, which is in contact with the side wall of the second groove of the substrate cell, covers the outer side wall of the cell edge transition region groove;
the bottom of the cell edge transition region groove is located below the substrate second conduction type base region, substrate cell insulating oxide layers are arranged on the inner side wall and the bottom wall of the cell edge transition region groove, substrate cell groove polycrystalline silicon is filled in the cell edge transition region groove provided with the substrate cell insulating oxide layers, and the substrate cell groove polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove through the substrate cell insulating oxide layers in the cell edge transition region groove.
In both the "first conductivity type" and the "second conductivity type", for an N-type power semiconductor device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power semiconductor device, the first conductivity type and the second conductivity type are opposite to the N-type power semiconductor device.
The invention has the advantages that: after at least one substrate second conductive type injection region is arranged between a substrate cell second groove and a terminal region, the substrate second conductive type injection region adjacent to the substrate cell second groove is contacted with the outer side wall of the substrate cell second groove adjacent to a terminal region, the increase of the substrate second conductive type injection region can relieve the electric field concentration at the bottom of the substrate cell second groove and the cell edge transition region groove, reduce the electric field intensity at the bottom of the substrate cell second groove and the cell edge transition region groove, prevent premature breakdown at the bottom of the substrate cell second groove and the cell edge transition region groove, fully increase the withstand voltage of the terminal region, reduce the junction depth requirement of the substrate terminal second conductive type region, improve the design freedom, enable the power semiconductor device to have higher breakdown voltage and reliability, or further reduce the area of the device under the same breakdown voltage, the cost is reduced, and the reliability of the power semiconductor device is improved.
Drawings
FIGS. 1 to 9 are diagrams illustrating the detailed manufacturing process steps of a conventional power semiconductor device, in which
Fig. 1 is a cross-sectional view of a substrate cell trench and a substrate termination trench after fabrication.
Fig. 2 is a cross-sectional view of the substrate cell trench polysilicon and the substrate termination trench polysilicon after fabrication.
Fig. 3 is a cross-sectional view after a P-type layer of the substrate is prepared.
FIG. 4 is a cross-sectional view after a second photoresist layer is prepared for lithography on a substrate.
Fig. 5 is a cross-sectional view of the substrate P-base region, the substrate N + source region, and the substrate P-body region after fabrication.
FIG. 6 is a cross-sectional view after a third photoresist layer window of the substrate has been obtained.
Fig. 7 is a cross-sectional view after obtaining a substrate source contact hole.
Fig. 8 is a cross-sectional view after obtaining a metal layer window on the front surface of the substrate.
Fig. 9 is a cross-sectional view after a window of a passivation layer of a substrate is obtained.
Fig. 10 is a schematic diagram of a breakdown position of a conventional power semiconductor device.
FIGS. 11-21 are cross-sectional views of specific process steps for fabricating a power semiconductor device according to the present invention, wherein
FIG. 11 is a cross-sectional view of a substrate cell first trench, a substrate cell second trench, and a substrate termination trench made in accordance with the present invention.
Fig. 12 is a cross-sectional view of the substrate cell trench polysilicon and substrate termination trench polysilicon obtained in accordance with the present invention.
Fig. 13 is a cross-sectional view of the present invention after a P + implant region of the substrate has been obtained.
Fig. 14 is a cross-sectional view of the invention after a P-type layer of the substrate has been obtained.
FIG. 15 is a cross-sectional view of the invention after a second photoresist layer has been patterned onto a substrate.
FIG. 16 is a cross-sectional view of a substrate P-type base region, a substrate N + source region, and a substrate P-type body region according to the present invention.
FIG. 17 is a cross-sectional view of the invention after a third photoresist layer window has been formed on the substrate.
Fig. 18 is a cross-sectional view of the present invention after a substrate source contact hole is formed.
Fig. 19 is a cross-sectional view of the invention after obtaining a metal layer window on the front side of the substrate.
Fig. 20 is a cross-sectional view of the invention after a substrate passivation layer window has been obtained.
FIG. 21 is a cross-sectional view of the invention after removal of the sixth photoresist layer from the substrate.
Fig. 22 is a cross-sectional view illustrating the arrangement of a cell edge transition region groove in a cell region according to the present invention.
Description of reference numerals: 1-semiconductor substrate, 2-substrate first photoresist layer, 3-substrate first mask, 4-substrate cell trench, 5-substrate terminal trench, 6-substrate first photoresist layer window, 7-substrate cell trench insulating oxide layer, 8-substrate cell trench polysilicon body, 9-substrate terminal trench insulating oxide layer, 10-substrate terminal trench conductive polysilicon, 11-substrate P type layer, 12-substrate second photoresist layer, 13-substrate second mask, 14-substrate P type body region, 15-substrate P type base region, 16-substrate N + source region, 17-substrate insulating dielectric layer, 18-substrate third mask, 20-substrate third photoresist layer window, 21-substrate fourth photoresist layer, 22-substrate fourth mask, 23-substrate front metal layer window, 24-substrate fourth photoresist layer window, 25-substrate passivation layer, 26-substrate fifth photoresist layer, 27-substrate fifth mask, 28-substrate fifth photoresist layer window, 29-substrate passivation layer window, 30-breakdown region, 31-semiconductor substrate, 32-substrate first photoresist layer, 33-substrate cell first trench, 34-substrate terminal trench, 35-substrate first photoresist layer window, 36-substrate cell trench polysilicon, 37-substrate cell insulating oxide layer, 38-substrate terminal trench polysilicon, 39-substrate terminal insulating oxide layer, 40-substrate second photoresist layer, 41-substrate second photoresist layer window, 42-substrate P + injection region, 25-substrate passivation layer, 43-substrate P type layer, 44-substrate third photoresist layer, 45-substrate third mask, 46-substrate third photoresist layer window, 47-substrate P type base region, 48-substrate N + source region, 49-substrate terminal P type body region, 50-substrate insulating medium layer, 51-substrate fourth photoresist layer, 52-substrate fourth mask, 53-substrate fourth photoresist layer window, 54-substrate source contact hole, 55-substrate front side terminal metal layer, 56-substrate fifth photoresist layer, 57-substrate fifth mask, 58-substrate fifth photoresist layer window, 59-substrate front side metal layer window, 60-substrate metal passivation layer, 61-substrate sixth photoresist layer, 62-substrate sixth mask, 63-substrate sixth photoresist layer window, 64-substrate passivation layer window, 65-substrate front side cellular metal layer, 66-substrate front side cellular metal layer, 67-substrate cellular second groove, 68-substrate front side terminal metal layer, 69-substrate first mask and 70-cellular edge transition region groove.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 21: in order to realize higher breakdown voltage and improve the working reliability of the power semiconductor device, taking an N-type groove type power semiconductor device as an example, the invention comprises a semiconductor substrate 31 with an N conduction type, a cellular region arranged in the central region of the semiconductor substrate 31 and a terminal region arranged on the semiconductor substrate 31 and positioned at the outer ring of the cellular region; the cells in the cell area adopt a groove structure;
on the top plan of the power semiconductor device, the unit cells of the unit cell area comprise annular substrate unit cell second grooves 67 and a plurality of substrate unit cell first grooves 33 positioned at the inner ring of the annular substrate unit cell second grooves 67, and the terminal area is positioned at the outer ring of the annular substrate unit cell second grooves 67;
on the cross section of the power semiconductor device, a substrate P-type base region 47 and a substrate N + source region 48 which is positioned above the substrate P-type base region 47 are arranged on two sides of the substrate cell first groove 33, the substrate P-type base region 47 is positioned above the corresponding groove bottoms of the substrate cell first groove 33 and the substrate cell second groove 67, and the substrate P-type base region 47 and the substrate N + source region 48 are both contacted with the corresponding side walls of the adjacent substrate cell first groove 33;
on the cross section of the power semiconductor device, the outer side wall of the substrate cell second groove 67 adjacent to the substrate cell first groove 33 is in contact with the corresponding substrate P-type base region 47 and the substrate N + source region 48, at least one substrate P + injection region 42 is arranged between the side wall of the substrate cell second groove 67 adjacent to the terminal region and the terminal region, the outer side wall of the substrate cell second groove 67 adjacent to the terminal region is in contact with the adjacent substrate P + injection region 42, and the depth of the substrate P + injection region 42 in the semiconductor substrate 31 is greater than the depth of the substrate cell first groove 33 and the substrate cell second groove 67 in the semiconductor substrate 31;
a substrate front side cell metal layer 66 is disposed over the front side of the semiconductor substrate 31, the substrate front side cell metal layer 66 being in ohmic contact with the substrate P-type base region 47, the substrate N + source region 48, and the substrate P + implant region 42 contacting the sidewalls of the substrate cell second trench 67.
Specifically, the semiconductor substrate 1 may be made of a semiconductor material commonly used in the art, such as silicon, and the specific material type may be selected according to actual needs, which is not described herein again. Generally, a cell region can be formed in the central region of the semiconductor substrate 1, and a terminal region can be formed at the outer periphery of the cell region, and the specific functions of the cell region and the terminal region in the power semiconductor and the specific matching between the cell region and the terminal region are the same as those in the prior art, which are well known in the art and will not be described herein again.
In the embodiment of the present invention, the cells in the cell area adopt a trench structure, and specifically, the cells in the cell area include a first substrate cell trench 33 and a second substrate cell trench 67, where, in the cross section of the power semiconductor device, the second substrate cell trench 67 is adjacent to a terminal area, that is, the first substrate cell trench 33 is located in a central area of the cell area, the second substrate cell trench 67 is located between the first substrate cell trench 33 and the terminal area, and the second substrate cell trench 67 is adjacent to the terminal area. In a top view of the power semiconductor device, the terminal region surrounds the cell region, and in the cell region, the annular substrate cell second trench 67 is adjacent to the terminal region, the substrate cell first trench 33 is located at an inner ring of the annular substrate cell second trench 67, and the number of the substrate cell first trenches 33 at the inner ring of the substrate cell second trench 67 is selected according to actual needs, and is specifically consistent with the existing trench type power semiconductor device, and is not repeated here.
On the cross section of the power semiconductor device, a substrate P-type base region 47 and a substrate N + source region 48 are arranged on two sides of the substrate cell first groove 33, the substrate N + source region 48 is located above the substrate P-type base region 47, the substrate N + source region 48 is adjacent to the substrate P-type base region 47, the substrate N + source region 48 and the substrate P-type base region 47 are in contact with the outer side wall of the substrate first cell groove 33, namely the substrate P-type base region 47 and the substrate N + source region 48 are in contact with the outer side wall of the substrate cell first groove 33. The substrate P-type base region 47 is located above the bottom of the substrate cell first trench 33 and above the bottom of the substrate cell second trench 67.
In the cross section of the power semiconductor device, the outer sidewall of the substrate cell second trench 67 adjacent to the side of the substrate cell first trench 33 contacts the substrate P-type base region 47 and the substrate N + source region 48, while at least one substrate P + implant region 42 is disposed between the side of the substrate cell second trench 67 adjacent to the terminal region and the terminal region, and the substrate P + implant region 42 adjacent to the substrate cell second trench 67 contacts the outer sidewall of the substrate cell second trench 67 adjacent to the terminal region. The depth of the substrate P + implantation region 42 in the semiconductor substrate 31 is greater than the depths of the substrate cell first trench 33 and the substrate cell second trench 67 in the semiconductor substrate 31, that is, the bottom of the substrate P + implantation region 42 is located below the bottoms of the substrate cell first trench 33 and the substrate cell second trench 67. When there are a plurality of substrate P + implant regions 42, only the substrate P + implant regions 42 adjacent to the substrate cell second trenches 67 are in contact with the outer sidewalls of the substrate cell second trenches 67 adjacent to the termination region.
In specific implementation, a substrate P-type base region 47 and a substrate N + source region 48 may be further disposed on one side of the substrate cell second trench 67 adjacent to the terminal region, of course, the substrate P-type base region 47 on one side of the substrate cell second trench 67 adjacent to the terminal region and the substrate P-type base regions 47 on two sides of the substrate cell first trench 33 are formed by using the same process step, and the substrate N + source region 48 on one side of the substrate cell second trench 67 adjacent to the terminal region and the substrate N + source region 48 on two sides of the substrate cell first trench 33 are obtained by using the same process step. After the substrate P-type base region 47 and the substrate N + source region 48 are arranged on the side, adjacent to the terminal region, of the substrate cell second trench 67, the substrate P-type base region 47 and the substrate N + source region 48 are both in contact with the outer side wall, adjacent to the terminal region, of the substrate cell second trench 67. In addition, after the substrate P-type base region 47 and the substrate N + source region 48 are arranged on the side of the substrate unit cell second trench 67 adjacent to the terminal region, the corresponding substrate P-type base region 47 and the corresponding substrate N + source region 48 cover the upper portion of the substrate P + injection region 42, and the substrate P-type base region 47 and the substrate N + source region 48 are in contact with the substrate P + injection region 42. In the top view of the power semiconductor device, the substrate P + implantation region 42 is annular, and the substrate P + implantation region 42 surrounds the substrate cell second trench 67. When a plurality of substrate P + implant regions 42 having a ring shape are present, adjacent substrate P + implant regions 42 are spaced apart from each other.
In order to form the source electrode of the power semiconductor device, a substrate front cell metal layer 66 is provided over the front surface of the semiconductor substrate 31, the substrate cell metal layer 66 being in ohmic contact with the substrate P-type base region 47, the substrate N +48 and the substrate P + implant region 42 contacting the outer sidewall of the substrate cell second trench 67. When there are a plurality of substrate P + implant regions 42, the remaining substrate P + implant regions 42 need to be isolated from the substrate front cell metal layer 66 except for the substrate P + implant regions 42 that are in contact with the outer sidewalls of the substrate cell second trenches 67 and are in ohmic contact with the substrate front cell metal layer 66.
Further, the substrate cell insulating oxide layer 37 covers the corresponding inner side walls and bottom walls of the substrate cell first trench 33 and the substrate cell second trench 67, and the substrate cell trench polysilicon 36 is filled in the substrate cell first trench 33 and the substrate cell second trench 67; the substrate cell trench polysilicon 36 filled in the substrate cell first trench 33 is insulated and isolated from the inner sidewall and the bottom wall of the filled substrate cell first trench 33 by the substrate cell insulation oxide layer 37 in the filled substrate cell first trench 33, and the substrate cell trench polysilicon 36 filled in the substrate cell second trench 67 is insulated and isolated from the inner sidewall and the bottom wall of the filled substrate cell second trench 67 by the substrate cell insulation oxide layer 37 in the filled substrate cell second trench 67;
the corresponding notches of the first substrate cell groove 33 and the second substrate cell groove 67 are covered by the substrate insulating medium layer 50 covering the front surface of the semiconductor substrate 31, and the substrate cell groove polysilicon 36 in the first substrate cell groove 33 and the substrate cell groove polysilicon 36 in the second substrate cell groove 67 can be insulated and isolated from the front substrate cell metal layer 66 through the substrate insulating medium layer 50.
In the embodiment of the present invention, the substrate cell insulating oxide layer 37 is disposed on the inner sidewall and the bottom wall of the substrate cell first trench 33, and meanwhile, the substrate cell insulating oxide layer 37 is also disposed on the inner sidewall and the bottom wall of the substrate cell second trench 67, the substrate cell insulating oxide layer 37 is a silicon dioxide layer, and the substrate cell insulating oxide layer 37 can be simultaneously grown in the substrate cell first trench 33 and in the substrate cell second trench 67 by using a thermal oxidation method.
The substrate cell trench polysilicon 36 is filled in both the substrate cell first trench 33 and the substrate cell second trench 67, the substrate cell trench polysilicon 36 is a conventional conductive polysilicon, wherein the substrate cell trench polysilicon 36 filled in the substrate cell first trench 33 is insulated and isolated from the inner sidewall and the bottom wall of the filled substrate cell first trench 33 by the substrate cell insulating oxide layer 37 filled in the substrate cell first trench 33, and the substrate cell trench polysilicon 36 filled in the substrate cell second trench 67 is insulated and isolated from the inner sidewall and the bottom wall of the filled substrate cell second trench 67 by the substrate cell insulating oxide layer 37 filled in the substrate cell second trench 67.
In specific implementation, the substrate cell trench polysilicon 36 in the substrate cell first trench 33 and the substrate cell second trench 67 is led out and then ohmic-contacted with the gate metal to obtain a gate electrode of the power semiconductor device, and the specific form of forming the gate electrode by matching the substrate cell trench polysilicon 36 with the gate metal is the same as that in the prior art, and is not repeated here. The gate metal and the front cell metal layer 66 of the substrate are insulated and isolated from each other, and the specific positional relationship between the gate metal and the front cell metal layer 66 of the substrate is the same as that in the prior art, which is well known to those skilled in the art and will not be described herein again.
In the embodiment of the present invention, the cells in the cell region are connected into a whole through the substrate front cell metal layer 66, in order to realize the insulation and isolation between the substrate front cell metal layer 66 and the substrate cell trench polysilicon 36, the front surface of the semiconductor substrate 31 is provided with the substrate insulating dielectric layer 50, the substrate insulating dielectric layer 50 is a silicon dioxide layer, the substrate insulating dielectric layer 50 covers the front surface of the semiconductor substrate 31, so that the substrate insulating dielectric layer 50 can cover the notches corresponding to the substrate cell first trench 33 and the substrate cell second trench 67, the substrate front cell metal layer 66 is supported on the substrate insulating dielectric layer 50, and the substrate front cell metal layer 66 utilizes the insulation and isolation between the substrate insulating dielectric layer 50 and the substrate cell trench polysilicon 36.
Further, the substrate front side cell metal layer 66 is supported on the substrate insulating dielectric layer 50, and a substrate front side terminal metal layer 55 is further disposed on the substrate insulating dielectric layer 50, the substrate front side terminal metal layer 66 and the substrate front side cell metal layer 55 are separated by a substrate metal passivation layer 60, and the substrate metal passivation layer 60 is supported on the substrate front side terminal metal layer 55 and the substrate front side cell metal layer 66;
and a substrate passivation layer window 64 penetrating through the substrate metal passivation layer 60, wherein the substrate front cell metal layer 66 corresponding to the substrate passivation layer window 64 can be exposed through the substrate passivation layer window 64.
In the embodiment of the present invention, a substrate front side terminal metal layer 55 is further disposed on the substrate insulating dielectric layer 50, the substrate front side terminal metal layer 55 and the substrate front side cell metal layer 66 are the same process step layer, the substrate front side terminal metal layer 55 corresponds to a terminal region of the semiconductor substrate 31, the substrate front side terminal metal layer 55 and the substrate front side cell metal layer 66 are separated by a substrate metal passivation layer 60, and the substrate metal passivation layer 60 is supported on the substrate front side terminal metal layer 55 and the substrate front side cell metal layer 66. The substrate metal passivation layer 60 may be made of a conventional material, such as silicon nitride, and the specific material type may be selected according to actual needs, which is not described herein again.
In order to lead out the substrate front cell metal layer 66 conveniently, the substrate metal passivation layer 60 is etched to obtain a substrate passivation layer window 64 penetrating through the substrate metal passivation layer 60, the substrate front cell metal layer 66 corresponding to the substrate passivation layer window 64 can be exposed through the substrate passivation layer window 64, and therefore the source electrode of the power semiconductor device can be formed after the substrate front cell metal layer 66 is led out conveniently.
Further, in the cross section of the power semiconductor device, the termination region includes at least one substrate termination trench 34 and substrate termination P-type body regions 49 located at two sides of the substrate termination trench 34, and the substrate termination P-type body regions 49 are located above the bottom of the corresponding trench of the substrate termination trench 34, the substrate cell first trench 33 and the substrate cell second trench 67;
a substrate terminal insulating oxide layer 39 is arranged on the inner side wall and the bottom wall of the substrate terminal groove 34, substrate terminal groove polycrystalline silicon 38 is filled in the substrate terminal groove 34 provided with the substrate terminal insulating oxide layer 39, and the substrate terminal groove polycrystalline silicon 38 is insulated and isolated from the inner side wall and the bottom wall of the substrate terminal groove 34 through the substrate terminal insulating oxide layer 39; the notches of the substrate termination trench 34 are covered by a substrate insulating dielectric layer 50.
In the embodiment of the present invention, at least one substrate termination trench 34 is provided in the termination region in the cross section of the power semiconductor device, and fig. 21 shows a case where two substrate termination trenches 34 are provided in the termination region; then both substrate termination trenches 34 are annular in the termination region in a top plan view of the power semiconductor device. A substrate termination P-type body region 49 extends through the termination region such that there is a substrate P-type body region 49 on both sides of substrate termination trench 34, substrate P-type body region 49 being located above the bottom of substrate termination trench 34. In general, the depth of substrate termination P-type body region 49 in semiconductor substrate 31 corresponds to the depth of substrate P-type base region 47 in semiconductor substrate 31.
A substrate termination insulating oxide layer 39 is disposed on the inner sidewalls and bottom wall of the substrate termination trench 34 and the substrate termination trench 34 is filled with a substrate termination trench polysilicon 38. the substrate termination trench polysilicon 38 filled in the substrate termination trench 34 is insulated from the inner sidewalls and bottom wall of the filled substrate termination trench 34 by the substrate termination insulating oxide layer 39 in the filled substrate termination trench 34. After the substrate insulating dielectric layer 50 is disposed on the front side of the semiconductor substrate 31, the substrate insulating dielectric layer 50 can simultaneously cover the notches of the substrate termination trenches 34, while the substrate termination trench polysilicon 38 can be insulated from the substrate front side termination metal layer 55 in the termination region by the substrate insulating dielectric layer 50.
In specific implementation, the substrate termination trench 34, the substrate cell first trench 33, and the substrate cell second trench 67 are obtained by using the same process step, so that the substrate termination trench 34, the substrate cell first trench 33, and the substrate cell second trench 67 have the same depth in the semiconductor substrate 31. The substrate cell insulating oxide layer 37 and the substrate terminal insulating oxide layer 39 are obtained by the same process step, and the substrate cell trench polysilicon 36 and the substrate terminal trench polysilicon 38 are obtained by the same process step.
In the embodiment of the present invention, after at least one substrate P + injection region 42 is disposed between the substrate cell second trench 67 and the terminal region, the substrate P + injection region 42 adjacent to the substrate cell second trench 67 is in contact with the outer sidewall of the substrate cell second trench 67 adjacent to the terminal region, increasing the substrate P + injection region 42 can relieve the electric field concentration at the bottom of the substrate cell second trench 67 and the electric field concentration at the bottom of the cell edge transition region trench 70, reduce the electric field strength at the bottom of the substrate cell second trench 67 and the electric field strength at the bottom of the cell edge transition region trench 70, prevent premature breakdown at the bottom of the substrate cell second trench 67 and the bottom of the cell edge transition region trench 70, fully increase the withstand voltage of the terminal region, reduce the requirement of the junction depth of the substrate terminal P-type body region 49, increase the degree of freedom of design, and enable the power semiconductor device to have higher breakdown voltage and reliability, or under the same breakdown voltage, the area of the device can be further reduced, the cost is reduced, and meanwhile, the reliability of the power semiconductor device is improved.
In addition, a substrate back structure is provided on the back of the semiconductor substrate 31, and the power semiconductor device can be an IGBT device or a power MOSFET device through the substrate back structure.
In the embodiment of the present invention, the IGBT device and the power MOSFET device may adopt the same front cell structure, and only by providing the required substrate back structure on the back of the semiconductor substrate 31, the power semiconductor device may be the IGBT device or the power MOSFET device, and the form of forming the IGBT device or the power MOSFET device by using the substrate back structure is the same as that in the prior art, which is known to those skilled in the art specifically, and is not described here again.
As shown in fig. 22, in the cross section of the power semiconductor device, a cell edge transition region trench 70 is further included in the cell region, the cell edge transition region trench 70 is located between the substrate cell second trench 67 and the terminal region, the depth of the substrate P + implantation region 42 in the semiconductor substrate 31 is greater than the depth of the cell edge transition region trench 70 in the semiconductor substrate 31, and the substrate P + implantation region 42 in contact with the sidewall of the substrate cell second trench 67 wraps the outer sidewall of the cell edge transition region trench 70.
The groove bottom of the cell edge transition region groove 70 is positioned below the substrate P-type base region 47, the substrate cell insulating oxide layer 37 is arranged on the inner side wall and the bottom wall of the cell edge transition region groove 70, the substrate cell groove polysilicon 36 is filled in the cell edge transition region groove 70 provided with the substrate cell insulating oxide layer 37, and the substrate cell groove polysilicon 36 is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove 70 through the substrate cell insulating oxide layer 37 in the cell edge transition region groove 70.
In the embodiment of the present invention, the cell edge transition region trench 70, the substrate cell first trench 33, the substrate cell second trench 67, and the substrate terminal trench 34 are formed in the same process step, and the cell edge transition region trench 70 has the same depth as the substrate cell first trench 33, the substrate cell second trench 67, and the substrate terminal trench 34. The cell edge transition region trench 70 is closer to the termination region than the substrate cell second trench 67. In a cross section of the power semiconductor device, a cell edge transition region trench 70 is located between the substrate cell second trench 67 and the substrate terminal trench 34 of the adjacent cell region.
As can be seen from the above description, the bottom of cell-edge transition region trench 70 is located below substrate P-type base region 47 and substrate termination P-type body region 49, but the bottom of cell-edge transition region trench 70 is located above the bottom of substrate P + implant region 42. In the embodiment of the present invention, the cell edge transition region trench 70 is located in the substrate P + implantation region 42 contacting with the sidewall of the substrate cell second trench 67, i.e. the outer sidewall of the cell edge transition region trench 70 is covered by the substrate P + implantation region 42 contacting with the sidewall of the substrate cell second trench 67. When at least one substrate P + implant region 42 is disposed between the substrate cell second trench 67 and the terminal region, then the cell edge transition region trench 70 will only be within the substrate P + implant region 42 that is in contact with the sidewalls of the substrate cell second trench 67. In the case where there are multiple substrate P + implant regions 42, adjacent substrate P + implant regions 42 are separated by a substrate terminal P type body region 49.
In fig. 22, the substrate P + implant region 42, which contacts the sidewalls of the substrate cell second trench 67, also wraps the bottom wall of the cell edge transition region trench 70. In specific implementation, when the substrate P + implantation region 42 is prepared, the substrate P + implantation region 42 can cover the outer sidewall of the cell edge transition region trench 70 or can cover the bottom wall of the cell edge transition region trench 70 at the same time according to the implantation energy and the annealing temperature of the P-type impurity ions. Whether the substrate P + implantation region 42 covers the bottom wall of the cell edge transition region trench 70 or not, the junction depth of the substrate P + implantation region 42 in the semiconductor substrate 31 is greater than the depths of the substrate cell first trench 33, the substrate cell second trench 67, and the cell edge transition region trench 70, that is, the substrate P + implantation region 42 is located below the bottoms of the substrate cell first trench 33, the substrate cell second trench 67, and the cell edge transition region trench 70 at the bottom of the semiconductor substrate 31.
When there are a plurality of substrate P + implant regions 42, the cell edge transition region trench 70 is only within the substrate P + implant region 42 that is in contact with the outer sidewalls of the substrate cell second trench 67. In addition, a plurality of cell edge transition region trenches 70 may be further formed in the substrate P + implant region 42 contacting the outer sidewalls of the substrate cell second trenches 67, and the substrate P + implant region 42 separates adjacent cell edge transition region trenches 70.
As can be seen from the above description, the cell edge transition region trench 70 cannot form a conductive channel, and does not affect the specific functions of the substrate cell first trench 33 and the substrate cell second trench 67.
As shown in fig. 11 to 21, the power semiconductor device can be prepared by the following process steps, specifically, the preparation method comprises the following steps:
step 1, providing a semiconductor substrate 31 with an N conductive type, and performing required groove etching on the front surface of the semiconductor substrate 31 to obtain a first substrate cell groove 33 and a second substrate cell groove 67 in a cell area of the semiconductor substrate 31, wherein the second substrate cell groove 67 is adjacent to a terminal area in the cell area;
as shown in fig. 11, the semiconductor substrate 31 may be made of a conventional semiconductor material, such as silicon, and for an N-type power semiconductor device, the conductivity type of the semiconductor substrate 31 is N-type. When the trench etching is performed on the semiconductor substrate 31, the front surface of the semiconductor substrate 31 needs to be coated to obtain the substrate first photoresist layer 32, and then the substrate first mask 69 is used to perform the photolithography on the substrate first photoresist layer 32 so as to pattern the substrate first photoresist layer 32, thereby obtaining the substrate first photoresist layer window 36 penetrating through the substrate first photoresist layer 32.
After the substrate first photoresist layer window 36 is obtained, the semiconductor substrate 31 is etched by using the substrate first photoresist layer 32 and the substrate first photoresist layer window 36 to obtain a substrate cell first trench 33 and a substrate cell second trench 67, wherein the substrate cell first trench 33, the substrate cell second trench 67 and the substrate first photoresist layer window 36 correspond to each other.
In addition, when the termination region also adopts the trench structure, the substrate termination trench 34 can be obtained at the same time, and the substrate termination trench 34 has the same depth as the substrate cell first trench 33 and the substrate cell second trench 67. The number of substrate termination trenches 34 in the termination region can be selected as desired, and the cross-sectional view of fig. 11 shows two substrate termination trenches 34 in the mid-termination region. Similarly, the number of the first trenches 33 of the bottom cells in the cell region can be selected according to actual requirements, but in the cross-sectional view, there is only one second trench 67 of the bottom cell between the first trench 33 of the bottom cell adjacent to the terminal region and the terminal trench 34 of the bottom cell adjacent to the cell region.
Specifically, the process and process conditions for etching the semiconductor substrate 31 to obtain the first substrate cell trench 33, the second substrate cell trench 67, and the substrate terminal trench 34 can be implemented by conventional techniques, which are well known to those skilled in the art. The substrate cell first trench 33, the substrate cell second trench 67, and the substrate terminal trench 34 are all located on the front surface of the semiconductor substrate 34, and after the substrate cell first trench 33, the substrate cell second trench 67, and the substrate terminal trench 34 are all located on the semiconductor substrate 34, the substrate first photoresist layer 32 needs to be removed by a conventional technical means in the art.
In order to obtain the structure shown in fig. 22, when the trench etching is performed, the cell edge transition region trench 70 can also be obtained, that is, the cell edge transition region trench 70, the substrate cell first trench 33, the substrate cell second trench 67, and the substrate terminal trench 34 are prepared in the same process step and have the same depth.
Step 2, arranging a substrate cell insulating oxide layer 37 in the substrate cell first groove 33 and the substrate cell second groove 67, and filling substrate cell groove polysilicon 36 in the substrate cell first groove 33 and the substrate cell second groove 67; covering the corresponding side walls and bottom walls of the first substrate cell groove 33 and the second substrate cell groove 67 on the substrate cell insulating oxide layer 37;
the substrate cell trench polysilicon 36 filled in the substrate cell first trench 33 is insulated and isolated from the sidewall and the bottom wall of the filled substrate cell first trench 33 by the substrate cell insulation oxide layer 37 in the filled substrate cell first trench 33, and the substrate cell trench polysilicon 36 filled in the substrate cell second trench 67 is insulated and isolated from the sidewall and the bottom wall of the filled substrate cell second trench 67 by the substrate cell insulation oxide layer 37 in the filled substrate cell second trench 67;
as shown in fig. 12, a thermal oxidation process is used to grow a substrate cell insulating oxide layer 37 in the substrate cell first trench 33 and the substrate cell second trench 67, and a substrate terminal insulating oxide layer 39 in the substrate terminal trench 34.
After obtaining the substrate cell insulating oxide layer 37 and the substrate terminal insulating oxide layer 39, depositing a polysilicon material to obtain a substrate cell trench polysilicon 36 filled in the substrate cell first trench 33 and the substrate cell second trench 67; at the same time, substrate termination trench polysilicon 38 can be obtained that fills in substrate termination trench 34.
After the cell edge transition region trench 70 is obtained, a substrate cell insulating oxide layer 37 can be grown on the inner side wall and the bottom wall of the cell edge transition region trench 70, and substrate cell trench polysilicon 36 can be filled in the cell edge transition region trench 70, wherein the substrate cell trench polysilicon 36 in the cell edge transition region trench 70 is insulated and isolated from the inner side wall and the bottom wall of the cell edge transition region trench 70 through the substrate cell insulating oxide layer 37 in the cell edge transition region trench 70.
Step 3, preparing a substrate P-type base region 47, a substrate N + source region 48 and at least one substrate P + injection region 42 in the semiconductor substrate 31; the substrate P-type base region 47 is positioned above the groove bottoms of the substrate cell first groove 33 and the substrate cell second groove 67, the substrate N + source region 48 is positioned above the substrate P-type base region 47, the substrate P + injection region 42 is positioned between the substrate cell second groove 67 and the terminal region, and the depth of the substrate P + injection region 42 in the semiconductor substrate 31 is greater than the depth of the substrate cell first groove 33 and the substrate cell second groove 67 in the semiconductor substrate 31;
the substrate P + injection region 42 adjacent to the substrate cell second groove 67 is contacted with the side wall of the substrate cell second groove 67 adjacent to the terminal region, the side wall of the substrate cell second groove 67 adjacent to the substrate cell first groove 33 is contacted with the substrate P-type base region 47 and the substrate N + source region 48, and the two side walls of the substrate cell first groove 33 are respectively contacted with the corresponding substrate P-type base region 47 and the substrate N + source region 48;
in the embodiment of the present invention, the specific process implementation of the substrate P-type base region 47, the substrate N + source region 48, the substrate P + injection region 42, and the substrate terminal P-type body region 49 can be realized by different processes, and can be specifically selected according to actual requirements. The following is a description of a specific process.
As shown in fig. 13, 14, 15, and 16, the step 3 specifically includes the following steps:
step 3.1, injecting P-type impurity ions above the front surface of the semiconductor substrate 31 to prepare at least one substrate P + injection region 42 between the substrate cell second trench 67 and the substrate terminal trench 34 adjacent to the cell region, wherein the substrate P + injection region 42 adjacent to the substrate cell second trench 67 is in contact with the sidewall of the substrate cell second trench 67 adjacent to the terminal region, and the depth of the substrate P + injection region 42 in the semiconductor substrate 31 is greater than the depths of the substrate cell first trench 33, the substrate cell second trench 67 and the substrate terminal trench 34 in the semiconductor substrate 31;
as shown in fig. 13, a substrate second photoresist layer 40 is coated on the front surface of the semiconductor substrate 31, and the substrate second photoresist layer 40 is subjected to photolithography by using a substrate second mask to obtain a substrate second photoresist layer window 41 penetrating through the substrate second photoresist layer 40. Specifically, the substrate second photoresist layer window 41 is between the substrate cell second trench 67 and the substrate terminal trench 34 adjacent to the cell region.
After obtaining the substrate second photoresist layer window 41, the substrate second photoresist layer 40 is used to shield the semiconductor substrate 31, and P-type impurity ions are implanted above the semiconductor substrate 31, where the type of the P-type impurity ions can be selected according to the requirement, which is known to those skilled in the art. After the P-type impurity ions are implanted, the drive-in process is carried out to obtain a substrate P + implantation region 42, and the substrate P + implantation region 42 is in positive correspondence with the substrate second photoresist layer window 41. On the top plan after the process, the obtained substrate P + implantation regions 42 are annular, and the number of the substrate P + implantation regions 42 can be selected according to actual needs.
Specifically, the substrate P + implant region 42 adjacent to the substrate cell second trench 67 is in contact with the sidewall of the substrate cell second trench 67 adjacent to the termination region, the depth of the substrate P + implant region 42 within the semiconductor substrate 31 being greater than the depth of the substrate cell first trench 33, the substrate cell second trench 67, and the substrate termination trench 34 within the semiconductor substrate 31; i.e., the bottom of the substrate P + implant region 42 is located below the substrate cell second trench 67. After the substrate P + implant region 42 is prepared, the substrate second photoresist layer 40 is removed from the front side of the semiconductor substrate 31 using techniques commonly used in the art.
In the embodiment of the present invention, after the substrate P + implantation region 42 is prepared, the substrate P + implantation region 42 in contact with the sidewall of the substrate cell second trench 67 adjacent to the terminal region can cover the cell edge transition region trench 70, that is, the substrate P + implantation region 42 can cover the outer sidewall and the bottom wall of the cell edge transition region trench 70, as shown in fig. 22.
Step 3.2, performing P-type impurity ion implantation again on the front surface of the semiconductor substrate 31 to obtain a substrate P-type layer 43 penetrating through the semiconductor substrate 31, wherein the substrate P-type layer 43 is located above the groove bottoms of the substrate cell first groove 33, the substrate cell second groove 67 and the substrate terminal groove 34;
as shown in fig. 14, P-type impurity ion implantation is performed again on the front surface of the semiconductor substrate 31 to obtain a substrate P-type layer 43 penetrating through the semiconductor substrate 31, wherein the substrate P-type layer 43 extends vertically downward from the front surface of the semiconductor substrate 31, and the bottom of the substrate P-type layer 43 is located above the respective groove bottoms of the substrate cell first trench 33, the substrate cell second trench 67, and the substrate termination trench 34. The doping concentration of the substrate P-type layer 43 is less than the doping concentration of the substrate P + implant region 42.
Step 3.3, performing N-type impurity ion implantation and P-type impurity ion implantation above the semiconductor substrate 31, obtaining a substrate P-type base region 47 located in the cell region by using the implanted P-type impurity ions and the substrate P-type layer 43 in the cell region, obtaining a substrate N + source region 48 located above the substrate P-type base region 47 by using the implanted N-type impurity ions, wherein the substrate N + source region 48 is adjacent to the substrate P-type base region 47; at the same time, a substrate termination P-type body region 49 can be obtained with the substrate P-type layer 43 in the termination region.
As shown in fig. 15, a substrate third photoresist layer 44 is first coated on the front surface of the semiconductor substrate 31, and then the substrate third photoresist layer 44 is subjected to photolithography by using a substrate third mask 45 to obtain a substrate third photoresist layer window 46 penetrating through the substrate third photoresist layer 44, and a corresponding region in the cell region can be exposed through the substrate third photoresist layer window 46. In fig. 15, the substrate P + implantation region 42 contacting the sidewall of the substrate cell second trench 67 is partially exposed, but in the specific implementation, the substrate cell second trench 67 and all the substrate P + implantation regions 42 may be shielded by the substrate third photoresist layer 44.
After a third photoresist layer window 46 of the substrate is obtained, injecting N-type impurity ions and P-type impurity ions above the front surface of the semiconductor substrate 31 by using the third photoresist layer 44 of the substrate and the third photoresist layer window 46 of the substrate, and performing a drive-in after the injection, so that a substrate P-type base region 47 positioned in a cellular region can be obtained by using the injected P-type impurity ions and a substrate P-type layer 43 in the cellular region, a substrate N + source region 48 positioned above the substrate P-type base region 47 can be obtained by using the injected N-type impurity ions, and the substrate N + source region 48 is adjacent to the substrate P-type base region 47; at the same time, a substrate termination P-type body region 49 can be obtained with the substrate P-type layer 43 in the termination region. In the embodiment of the present invention, the doping concentration of the substrate P-type base region 47 is greater than that of the terminal P-type body region 49, i.e. the region of the substrate P-type layer 43 not implanted with P-type impurity ions and N-type impurity ions can form the substrate terminal P-type body region 49. The depth of substrate P-type base region 47 in semiconductor substrate 31 corresponds to the depth of substrate terminal P-type body region 49.
When the substrate P + implantation region 42 in contact with the sidewall of the substrate cell second trench 67 has a portion not blocked by the substrate third photoresist layer 44, the substrate P-type base region 47 and the substrate N + source region 48 in contact with the substrate P + implantation region 42 can be obtained after implantation of the N-type impurity ions and the P-type impurity ions. For the substrate P + implantation region 42 contacting with the sidewall of the substrate cell second trench 67, the substrate P-type base region 47 and the substrate N + source region 48 contacting with the substrate P + implantation region 42 also contact with the outer wall of the substrate cell second trench 67 adjacent to the termination region. When the substrate P + implantation region 42 is completely covered by the substrate third photoresist layer 44, the substrate P + implantation region 42 is not affected when the N-type impurity ions and the P-type impurity ions are implanted. In fig. 16, a case is shown where substrate P-type base region 47 and substrate N + source region 48 are formed on substrate P + implant region 42. As can be seen from the above description, when a plurality of substrate P + implant regions 42 are present between the substrate cell second trench 67 and the substrate termination trench 34 adjacent to the cell region, the adjacent substrate P + implant regions 42 are separated by the substrate termination P-type body region 49, and the substrate P + implant region 42 is in contact with the substrate termination P-type body region 49 passing through the separation. In fig. 16, substrate P + implant region 42 is in contact with substrate termination P-type body region 49 for the case where there is only one substrate P + implant region 42. In fig. 22, the cell edge transition region trench 70 is located in the substrate P + implant region 42 in contact with the substrate cell second trench 67, and also in contact with the substrate P-type base region 47 and the substrate N + source region 48 at the outer sidewall of the substrate cell second trench 67 adjacent the termination region.
In the above process, after the N-type impurity ions and the P-type impurity ions are performed, the substrate P-type base region 47 and the substrate N + source region 48 can be formed at the same time through a required annealing process, and the specific processes of performing the ion implantation and the annealing are the same as those in the prior art, and are well known to those skilled in the art and will not be described herein again. In addition, since the annealing temperature of N + cannot be too high, the drive well depth of the substrate P-type base region 47 is limited during annealing.
In order to improve the depth of the well-pushing of the substrate P-type base region 47, a substrate transition medium layer can be deposited on the front surface of the semiconductor substrate 31, a transition medium layer photoresist layer is coated on the substrate transition medium layer, and the transition medium layer photoresist layer is subjected to photoetching by using a transition medium layer mask to obtain a patterned transition medium layer photoresist layer. And etching the substrate transition medium layer by using the patterned transition medium layer photoresist layer to obtain a substrate transition medium layer window penetrating through the substrate transition medium layer. After obtaining the substrate transition dielectric layer window, performing P-type impurity ion implantation above the front surface of the semiconductor substrate 31, after the P-type impurity ion implantation, removing the transition dielectric layer photoresist layer and performing thermal drive-in to obtain the substrate P-type base region 47, wherein the junction depth of the obtained substrate P-type base region 47 is greater than that obtained by the above process. After obtaining the substrate P-type base region 47, performing N-type impurity ion implantation on the front surface of the semiconductor substrate 31 by using the substrate transition dielectric layer, and performing hot drive-in after the N-type impurity ion implantation to obtain the substrate N + source region 48. After obtaining the substrate N + source region 48, removing the substrate transition dielectric layer from the semiconductor substrate 31; of course, the substrate transition dielectric layer may also be reserved according to actual needs, as long as the substrate transition dielectric layer does not affect the preparation of the power semiconductor device, which is specifically familiar to those skilled in the art, and is not described herein again.
In specific implementation, the P-type impurity ion implantation condition, the N-type impurity ion implantation condition, the hot-trap process after the P-type impurity ion implantation, and the hot-trap process after the N-type impurity ion implantation are all the same as those of the prior art, and for example, the technical scheme disclosed in the publication number CN110047757A can be referred to, and the specific process conditions and processes are well known to those skilled in the art, and are not described herein again.
In addition, other processes can be adopted to prepare a substrate P-type base region 47, a substrate N + source region 48, a substrate P + injection region 42 and a substrate terminal P-type body region 49; thus, the step 3 specifically comprises the following steps:
step 3.a, performing P-type impurity ion implantation on the front surface of the semiconductor substrate 31 to obtain a substrate P-type layer 43 penetrating through the semiconductor substrate 31, wherein the substrate P-type layer 43 is positioned above the groove bottoms of the substrate cell first groove 33, the substrate cell second groove 67 and the substrate terminal groove 34;
in the embodiment of the present invention, a P-type impurity ion is implanted by a conventional technique in the art to obtain a P-type substrate layer 43 penetrating through the semiconductor substrate 31, and the P-type substrate layer 43 extends vertically downward from the front surface of the semiconductor substrate 31. The substrate P-type layer 43 is located over the respective bottoms of the substrate cell first trench 33, the substrate cell second trench 67, and the substrate termination trench 34.
Step 3.b, implanting P-type impurity ions again above the front surface of the upper semiconductor substrate 31 to prepare at least one substrate P + implantation region 42 between the substrate cell second trench 67 and the substrate terminal trench 34 adjacent to the cell region, wherein the substrate P + implantation region 42 adjacent to the substrate cell second trench 67 is in contact with the sidewall of the substrate cell second trench 67 adjacent to the terminal region, and the depth of the substrate P + implantation region 42 in the semiconductor substrate 31 is greater than the depths of the substrate cell first trench 33, the substrate cell second trench 67 and the substrate terminal trench 34 in the semiconductor substrate;
in the embodiment of the present invention, after the substrate P-type layer 43 is obtained, a substrate implantation photoresist layer is coated on the front surface of the semiconductor substrate 31, and the substrate implantation photoresist layer is subjected to photolithography by using a substrate implantation photoresist layer mask to obtain a patterned substrate implantation photoresist layer. And injecting P-type impurity ions by utilizing the substrate injection photoresist layer to prepare and obtain a substrate P + injection region 42, wherein the doping concentration of the substrate P + injection region 42 is greater than that of the substrate P-type layer 43. After the substrate P + implant region 42 is obtained, a form consistent with fig. 14 can be obtained.
Step 3, c, performing N-type impurity ion implantation and P-type impurity ion implantation above the semiconductor substrate 31, obtaining a substrate P-type base region 47 positioned in the cell region by utilizing the implanted P-type impurity ions and the substrate P-type layer 43 in the cell region, obtaining a substrate N + source region 48 positioned above the substrate P-type base region 47 by utilizing the implanted N-type impurity ions, wherein the substrate N + source region 48 is adjacent to the substrate P-type base region 47; at the same time, a substrate termination P-type body region 49 can be obtained with the substrate P-type layer 43 in the termination region.
Specifically, the substrate P-type base region 47, the substrate N + source region 48 and the substrate terminal P-type body region 49 can be prepared by the processes shown in fig. 15 and fig. 16, and specific reference can be made to the above description, which is not repeated herein.
In contrast to the processes of fig. 13 to 16, the processes of step 3.a to step 3.c are only to prepare the substrate P type layer 43 first, then prepare the substrate P + implantation region 42, and the rest of the processes are consistent with those of step 3.1 to step 3.3, and the above description is specifically referred to, and will not be described in detail herein. In addition, in the process from step 3.a to step 3.c, the condition of the cell edge transition region trench 70 may refer to the corresponding description in step 3.1 to step 3.3, and will not be described herein again.
Step 4, performing dielectric layer deposition on the front surface of the semiconductor substrate 31 to obtain a substrate insulating dielectric layer 50 covering the front surface of the semiconductor substrate 31; performing contact hole etching on the substrate insulating dielectric layer 50 to obtain a substrate source contact hole 54 penetrating through the substrate insulating dielectric layer 50;
specifically, the substrate insulating dielectric layer 50 is a silicon dioxide layer, and the substrate insulating dielectric layer 50 can be obtained by deposition by a conventional technical means in the technical field, and the substrate insulating dielectric layer 50 covers the front surface of the semiconductor substrate 31.
In order to obtain the substrate source contact hole 54, a substrate fourth photoresist layer 51 is coated on the substrate insulating medium layer 50, and the substrate fourth photoresist layer 51 is subjected to photolithography by using a substrate fourth mask to obtain a substrate fourth photoresist layer window 53 penetrating through the substrate fourth photoresist layer 51, so as to implement the required patterning of the substrate fourth photoresist layer 51, as shown in fig. 17.
And etching the substrate insulating medium layer 50 by using the substrate fourth photoresist layer 51 and the substrate fourth photoresist layer window 53 to obtain a substrate source contact hole 54. In fig. 18, the substrate source contact holes 54 are located on both sides of the substrate cell first trench 33, and the substrate cell second trench 67 is located on a side adjacent to the terminal region. The substrate source contact hole 54 penetrates through the substrate insulating dielectric layer 50; substrate source contact holes 54 at two sides of the first trench 33 of the substrate unit cell, wherein the bottoms of the substrate source contact holes 54 correspond to the substrate P-type base region 47; the substrate source contact hole 54 outside the second trench 67 for the substrate unit cell corresponds to the substrate P + implant region 42. When the outer sidewall of the substrate cell second trench 67 adjacent to the termination region contacts the substrate P-type base region 47 and the substrate N + source region 48, the substrate source contact hole 54 outside the substrate cell second trench 67 needs to correspond to the substrate P-type base region 47 and the substrate N + source region 48.
Step 5, performing metal deposition on the front surface of the semiconductor substrate 31 to obtain a substrate front surface metal layer, wherein the substrate front surface metal layer covers the substrate insulating dielectric layer 50, the substrate front surface cell metal layer 66 and the substrate front surface terminal metal layer 55 can be obtained after etching the substrate front surface metal layer, the substrate front surface cell metal layer 66 and the substrate front surface terminal metal layer 55 cover the substrate insulating dielectric layer 50, and the substrate front surface cell metal layer 66 is further filled in the substrate source contact hole 54; the substrate front cell metal layer 66 filled in the substrate source contact hole 54 is in ohmic contact with the substrate P-type base region 47, the substrate N + source region 48 and the substrate P + injection region 42 in contact with the side wall of the substrate cell second groove 67;
specifically, a substrate front metal layer is obtained by deposition by a technical means commonly used in the technical field, and covers the substrate insulating dielectric layer 50 and is filled in the substrate source contact hole for 54 years. And coating the metal layer on the front surface of the substrate to obtain a fifth photoresist layer 56 of the substrate, and photoetching the fifth photoresist layer 56 of the substrate by using a fifth mask 57 of the substrate to obtain a fifth photoresist layer window 58 of the substrate penetrating through the fifth photoresist layer 56 of the substrate, so as to realize the patterning of the fifth photoresist layer 56 of the substrate.
Etching the metal layer on the front surface of the substrate by using the fifth photoresist layer 56 of the substrate and the fifth photoresist layer window 58 of the substrate to obtain a metal layer window 59 on the front surface of the substrate, and dividing the metal layer on the front surface of the substrate by using the metal layer window 59 on the front surface of the substrate to obtain a cell metal layer 66 on the front surface of the substrate and a terminal metal layer 55 on the front surface of the substrate; wherein, the substrate front cell metal layer 66 is also filled in the substrate source contact hole 54; the substrate front cell metal layer 66 filled in the substrate source contact hole 54 is in ohmic contact with the substrate P-type base region 47, the substrate N + source region 48 and the substrate P + implantation region 42 in contact with the sidewall of the substrate cell second trench 67.
For the substrate cell second trench 67, when the sidewall of the substrate cell second trench 67 adjacent to the terminal region contacts the substrate P-type base region 47, the substrate N + source region 48 and the substrate P + implantation region 42, the substrate front cell metal layer 66 needs to make ohmic contact with the substrate P-type base region 47, the substrate N + source region 48 and the substrate P + implantation region 42 of the substrate cell second trench 67 adjacent to the terminal region sidewall, as shown in fig. 19. When the sidewall of the substrate cell second trench 67 adjacent to the termination region is in contact with only the substrate P + implant region 42, then the substrate front side cell metal layer 66 is in ohmic contact with the substrate P + implant region 42 in direct contact with the sidewall of the substrate cell second trench 67.
After the substrate front surface cell metal layer 66 and the substrate front surface terminal metal layer 65 are obtained, the substrate fifth photoresist layer 56 is removed, and the substrate front surface terminal metal layer 65 is located above the terminal region.
In addition, when the metal layer on the front surface of the substrate is etched, gate metal can be obtained, the gate metal is in ohmic contact with the substrate cell groove polysilicon 36, and a gate electrode of the power semiconductor device can be formed by using the gate metal.
Step 6, performing passivation layer deposition on the front surface of the semiconductor substrate 31 to obtain a substrate metal passivation layer 60, wherein the substrate metal passivation layer 60 covers the substrate front surface cell metal layer 66 and the substrate front surface terminal metal layer 55, and the substrate front surface cell metal layer 66 and the substrate front surface terminal metal layer 55 can be separated by using the substrate metal passivation layer 60;
specifically, the passivation layer deposition is performed by a conventional technique in the art to obtain the substrate metal passivation layer 60, and the substrate metal passivation layer 60 can be filled in the substrate front side metal layer window 59, so that the separation of the substrate front side cell metal layer 66 and the substrate front side terminal metal layer 55 can be realized.
Step 7, etching the substrate metal passivation layer 60 to obtain a substrate metal passivation layer window 64 penetrating through the substrate metal passivation layer, wherein the substrate front cell metal layer 66 corresponding to the substrate metal passivation layer window 64 can be exposed through the substrate metal passivation layer window 64;
specifically, a substrate sixth photoresist layer 61 is obtained by coating on the substrate metal passivation layer 60, and the substrate sixth photoresist layer 61 is subjected to photolithography by using a substrate sixth mask 62, so as to obtain a substrate sixth photoresist layer window 63 penetrating through the substrate sixth photoresist layer 61. Etching the substrate metal passivation layer 60 by using the substrate sixth photoresist layer 61 and the substrate sixth photoresist layer window 63 to obtain a substrate metal passivation layer window 64, where the substrate metal passivation layer window 64 is located in the cell region, and the substrate front cell metal layer 66 corresponding to the substrate metal passivation layer window 64 can be exposed through the substrate metal passivation layer window 64, as shown in fig. 20; the cell metal layer 66 on the front side of the substrate can be conveniently led out through the substrate metal passivation layer window 64.
After obtaining the substrate metal passivation layer window 64, the substrate sixth photoresist layer 61 needs to be removed from the substrate metal passivation layer 60, so as to complete the front surface process of the power semiconductor device, as shown in fig. 21.
And 8, performing a required back surface process on the back surface of the semiconductor substrate 31 to obtain a required substrate back surface structure on the back surface of the semiconductor substrate.
In the embodiment of the present invention, a required backside process is performed according to a type of a power semiconductor device to be manufactured, so as to obtain a substrate backside structure, and a specific backside process and a specific form of the substrate backside structure may be selected according to needs, which are well known to those skilled in the art, and are not described herein again.

Claims (10)

1. A low-cost high-performance groove type power semiconductor device comprises a semiconductor substrate with a first conduction type, a cellular region arranged in the central region of the semiconductor substrate, and a terminal region arranged on the semiconductor substrate and positioned at the outer ring of the cellular region; the cells in the cell area adopt a groove structure; the method is characterized in that:
on the top plan of the power semiconductor device, the unit cells of the unit cell area comprise annular substrate unit cell second grooves and a plurality of substrate unit cell first grooves positioned at the inner rings of the annular substrate unit cell second grooves, and the terminal area is positioned at the outer rings of the annular substrate unit cell second grooves;
on the cross section of the power semiconductor device, a substrate second conduction type base region and a substrate first conduction type source region are arranged on two sides of a substrate cell first groove, the substrate second conduction type base region is located above the corresponding groove bottoms of the substrate cell first groove and the substrate cell second groove, and the substrate second conduction type base region and the substrate first conduction type source region are in contact with the corresponding side walls of the adjacent substrate cell first groove;
on the cross section of the power semiconductor device, the outer side wall of a substrate cell second groove adjacent to a substrate cell first groove is contacted with a corresponding substrate second conduction type base region and a substrate first conduction type source region, at least one substrate second conduction type injection region is arranged between the side wall of the substrate cell second groove adjacent to a terminal region and the terminal region, the outer side wall of the substrate cell second groove adjacent to the terminal region is contacted with an adjacent substrate second conduction type injection region, and the depth of the substrate second conduction type injection region in a semiconductor substrate is greater than the depth of the substrate cell first groove and the substrate cell second groove in the semiconductor substrate;
a substrate front cell metal layer is arranged above the front surface of the semiconductor substrate, and can be in ohmic contact with the substrate second conductive type base region, the substrate first conductive type source region and the substrate second conductive type injection region which is in contact with the side wall of the substrate cell second groove;
the substrate second conduction type injection region contacted with the side wall of the substrate cell second groove is contacted with the substrate first conduction type source region and the substrate second conduction type base region which are contacted with the side wall of the substrate cell second groove adjacent to the terminal region.
2. The low-cost high-performance trench power semiconductor device according to claim 1, wherein: substrate cell insulating oxide layers cover the corresponding inner side walls and the bottom walls of the first substrate cell grooves and the second substrate cell grooves, and substrate cell groove polycrystalline silicon is filled in the first substrate cell grooves and the second substrate cell grooves; the substrate cell groove polysilicon filled in the substrate cell first groove is insulated and isolated from the inner side wall and the bottom wall of the filled substrate cell first groove through a substrate cell insulation oxidation layer in the filled substrate cell first groove, and the substrate cell groove polysilicon filled in the substrate cell second groove is insulated and isolated from the inner side wall and the bottom wall of the filled substrate cell second groove through a substrate cell insulation oxidation layer in the filled substrate cell second groove;
the notches corresponding to the first groove and the second groove of the substrate unit cell are covered by a substrate insulating medium layer covering the front surface of the semiconductor substrate, and the substrate unit cell groove polycrystalline silicon in the first groove of the substrate unit cell and the substrate unit cell groove polycrystalline silicon in the second groove of the substrate unit cell can be insulated and isolated from the cell metal layer on the front surface of the substrate through the substrate insulating medium layer.
3. The low-cost high-performance trench power semiconductor device according to claim 2, wherein: the substrate front side cell metal layer is supported on the substrate insulating medium layer, a substrate front side terminal metal layer is further arranged on the substrate insulating medium layer, the substrate front side terminal metal layer and the substrate front side cell metal layer are separated through a substrate metal passivation layer, and the substrate metal passivation layer is supported on the substrate front side terminal metal layer and the substrate front side cell metal layer;
the substrate passivation layer window penetrates through the substrate metal passivation layer, and the substrate front cell metal layer corresponding to the substrate passivation layer window can be exposed through the substrate passivation layer window.
4. The low-cost high-performance trench power semiconductor device according to claim 1, wherein: on the cross section of the power semiconductor device, the terminal area comprises at least one substrate terminal groove and substrate terminal second conduction type body areas positioned on two sides of the substrate terminal groove, and the substrate terminal second conduction type body areas are positioned above the groove bottoms corresponding to the substrate terminal groove, the substrate cellular first groove and the substrate cellular second groove;
arranging substrate terminal insulating oxide layers on the side wall and the bottom wall of the substrate terminal groove, filling substrate terminal groove polycrystalline silicon in the substrate terminal groove provided with the substrate terminal insulating oxide layers, and insulating and isolating the substrate terminal groove polycrystalline silicon from the side wall and the bottom wall of the substrate terminal groove through the substrate terminal insulating oxide layers; and the notch of the substrate terminal groove is covered by a substrate insulating medium layer.
5. The low-cost high-performance trench power semiconductor device according to claim 1, wherein: on the cross section of the power semiconductor device, a cell edge transition region groove is further included in the cell region, the cell edge transition region groove is located between a substrate cell second groove and a terminal region, the depth of a substrate second conduction type injection region in the semiconductor substrate is larger than that of the cell edge transition region groove in the semiconductor substrate, and the substrate second conduction type injection region in contact with the side wall of the substrate cell second groove wraps the outer side wall of the cell edge transition region groove;
the bottom of the cell edge transition region groove is located below the substrate second conduction type base region, substrate cell insulating oxide layers are arranged on the inner side wall and the bottom wall of the cell edge transition region groove, substrate cell groove polycrystalline silicon is filled in the cell edge transition region groove provided with the substrate cell insulating oxide layers, and the substrate cell groove polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove through the substrate cell insulating oxide layers in the cell edge transition region groove.
6. A preparation method of a low-cost high-performance groove type power semiconductor device is characterized by comprising the following steps:
step 1, providing a semiconductor substrate with a first conductive type, and carrying out required groove etching on the front surface of the semiconductor substrate to obtain a first groove of a substrate cellular and a second groove of the substrate cellular in a cellular area of the semiconductor substrate, wherein the second groove of the substrate cellular is adjacent to a terminal area;
step 2, arranging substrate cell insulating oxide layers in the substrate cell first grooves and the substrate cell second grooves, and filling substrate cell groove polycrystalline silicon in the substrate cell first grooves and the substrate cell second grooves; covering the corresponding side walls and bottom walls of the first grooves and the second grooves of the substrate unit cells on the substrate unit cell insulating oxide layer;
the substrate cell groove polysilicon filled in the substrate cell first groove is insulated and isolated from the side wall and the bottom wall of the filled substrate cell first groove through a substrate cell insulation oxidation layer in the filled substrate cell first groove, and the substrate cell groove polysilicon filled in the substrate cell second groove is insulated and isolated from the side wall and the bottom wall of the filled substrate cell second groove through a substrate cell insulation oxidation layer in the filled substrate cell second groove;
step 3, preparing a substrate second conductive type base region, a substrate first conductive type source region and at least one substrate second conductive type injection region in the semiconductor substrate; the substrate second conduction type base region is positioned above the corresponding groove bottoms of the substrate cell first groove and the substrate cell second groove, the substrate first conduction type source region is positioned above the substrate second conduction type base region, the substrate second conduction type injection region is positioned between the substrate cell second groove and the terminal region, and the depth of the substrate second conduction type injection region in the semiconductor substrate is greater than that of the substrate cell first groove and the substrate cell second groove in the semiconductor substrate;
the substrate second conduction type injection region adjacent to the substrate cell second groove is contacted with the outer side wall of the substrate cell second groove adjacent to the terminal region, the outer side wall of the substrate cell second groove adjacent to the substrate cell first groove is contacted with the substrate second conduction type base region and the substrate first conduction type source region, and the outer side wall of the substrate cell first groove is contacted with the corresponding substrate second conduction type base region and the substrate first conduction type source region;
step 4, carrying out dielectric layer deposition on the front surface of the semiconductor substrate to obtain a substrate insulating dielectric layer covering the front surface of the semiconductor substrate; etching a contact hole on the substrate insulating medium layer to obtain a substrate source contact hole penetrating through the substrate insulating medium layer;
step 5, performing metal deposition on the front surface of the semiconductor substrate to obtain a substrate front surface metal layer, wherein the substrate front surface metal layer covers the substrate insulating medium layer, the substrate front surface cellular metal layer and the substrate front surface terminal metal layer can be obtained after etching the substrate front surface metal layer, the substrate front surface cellular metal layer and the substrate front surface terminal metal layer cover the substrate insulating medium layer, and the substrate front surface cellular metal layer is also filled in the substrate source electrode contact hole; the substrate front cell metal layer filled in the substrate source electrode contact hole is in ohmic contact with the substrate second conduction type base region, the substrate first conduction type source region and the substrate second conduction type injection region in contact with the side wall of the substrate cell second groove;
step 6, carrying out passivation layer deposition on the front surface of the semiconductor substrate to obtain a substrate metal passivation layer, wherein the substrate metal passivation layer covers the substrate front surface cellular metal layer and the substrate front surface terminal metal layer, and the substrate front surface cellular metal layer and the substrate front surface terminal metal layer can be separated by the substrate metal passivation layer;
step 7, etching the substrate metal passivation layer to obtain a substrate metal passivation layer window penetrating through the substrate metal passivation layer, wherein the substrate front cellular metal layer corresponding to the substrate metal passivation layer window can be exposed through the substrate metal passivation layer window;
step 8, carrying out a required back surface process on the back surface of the semiconductor substrate to obtain a required substrate back surface structure on the back surface of the semiconductor substrate;
the substrate second conduction type injection region contacted with the side wall of the substrate cell second groove is contacted with the substrate first conduction type source region and the substrate second conduction type base region which are contacted with the side wall of the substrate cell second groove adjacent to the terminal region.
7. The method of claim 6, wherein a substrate termination trench is formed in the termination region during trench etching of the semiconductor substrate, and a substrate termination insulating oxide layer and a substrate termination trench polysilicon layer filled in the substrate termination trench are formed in the substrate termination trench, wherein the substrate termination trench polysilicon layer is insulated and isolated from the inner sidewall and bottom wall of the substrate termination trench by the substrate termination insulating oxide layer;
and 3, when the substrate second conduction type base region is prepared, a substrate terminal second conduction type body region penetrating through the terminal region can be obtained at the same time, the substrate terminal second conduction type body region is positioned above the groove bottom of the substrate terminal groove, and the doping concentration of the substrate terminal second conduction type body region is smaller than that of the substrate second conduction type base region.
8. The method for manufacturing a low-cost high-performance trench power semiconductor device according to claim 7, wherein the step 3 specifically comprises the following steps:
step 3.1, injecting second conductive type impurity ions above the front surface of the semiconductor substrate to prepare at least one substrate second conductive type injection region between the substrate cellular second groove and the substrate terminal groove adjacent to the cellular region, wherein the substrate second conductive type injection region adjacent to the substrate cellular second groove is in contact with the side wall of the substrate cellular second groove adjacent to the terminal region, and the depth of the substrate second conductive type injection region in the semiconductor substrate is greater than the depth of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove in the semiconductor substrate;
step 3.2, performing second conductive type impurity ion implantation on the front surface of the semiconductor substrate again to obtain a substrate second conductive type layer penetrating through the semiconductor substrate, wherein the substrate second conductive type layer is positioned above the corresponding groove bottoms of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove;
step 3.3, performing first conductive type impurity ion implantation and second conductive type impurity ion implantation above the semiconductor substrate, obtaining a substrate second conductive type base region positioned in the cell region by utilizing the implanted second conductive type impurity ions and the substrate second conductive type layer in the cell region, obtaining a substrate first conductive type source region positioned above the substrate second conductive type base region by utilizing the implanted first conductive type impurity ions, and enabling the substrate first conductive type source region to be adjacent to the substrate second conductive type base region; meanwhile, a substrate terminal second conductive type body region can be obtained by utilizing the substrate second conductive type layer in the terminal region.
9. The method for manufacturing a low-cost high-performance trench power semiconductor device according to claim 7, wherein the step 3 specifically comprises the following steps:
step 3.a, performing second conductive type impurity ion implantation on the front surface of the semiconductor substrate to obtain a substrate second conductive type layer penetrating through the semiconductor substrate, wherein the substrate second conductive type layer is positioned above the corresponding groove bottoms of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove;
step 3.b, injecting second conductive type impurity ions again above the front surface of the upper semiconductor substrate to prepare at least one substrate second conductive type injection region between the substrate cellular second groove and the substrate terminal groove adjacent to the cellular region, wherein the substrate second conductive type injection region adjacent to the substrate cellular second groove is contacted with the side wall of the substrate cellular second groove adjacent to the terminal region, and the depth of the substrate second conductive type injection region in the semiconductor substrate is greater than the depth of the substrate cellular first groove, the substrate cellular second groove and the substrate terminal groove in the semiconductor substrate;
step 3, c, performing first conductive type impurity ion implantation and second conductive type impurity ion implantation above the semiconductor substrate, obtaining a substrate second conductive type base region positioned in the cell region by utilizing the implanted second conductive type impurity ions and the substrate second conductive type layer in the cell region, obtaining a substrate first conductive type source region positioned above the substrate second conductive type base region by utilizing the implanted first conductive type impurity ions, and enabling the substrate first conductive type source region to be adjacent to the substrate second conductive type base region; meanwhile, a substrate terminal second conductive type body region can be obtained by utilizing the substrate second conductive type layer in the terminal region.
10. The method for manufacturing a low-cost high-performance trench power semiconductor device according to claim 6, wherein when a semiconductor substrate is subjected to trench etching, a cell edge transition region trench located in a cell region can be obtained, the cell edge transition region trench is located between a substrate cell second trench and a termination region, a depth of the substrate second conductivity type implantation region in the semiconductor substrate is greater than a depth of the cell edge transition region trench in the semiconductor substrate, and the substrate second conductivity type implantation region in contact with a sidewall of the substrate cell second trench covers an outer sidewall of the cell edge transition region trench;
the bottom of the cell edge transition region groove is located below the substrate second conduction type base region, substrate cell insulating oxide layers are arranged on the inner side wall and the bottom wall of the cell edge transition region groove, substrate cell groove polycrystalline silicon is filled in the cell edge transition region groove provided with the substrate cell insulating oxide layers, and the substrate cell groove polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell edge transition region groove through the substrate cell insulating oxide layers in the cell edge transition region groove.
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