CN114937596A - Manufacturing method and structure of IGBT device - Google Patents

Manufacturing method and structure of IGBT device Download PDF

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Publication number
CN114937596A
CN114937596A CN202210475742.4A CN202210475742A CN114937596A CN 114937596 A CN114937596 A CN 114937596A CN 202210475742 A CN202210475742 A CN 202210475742A CN 114937596 A CN114937596 A CN 114937596A
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region
main surface
doped
terminal
layer
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曹功勋
郎金荣
刘建华
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GTA Semiconductor Co Ltd
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GTA Semiconductor Co Ltd
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Priority to CN202210475742.4A priority Critical patent/CN114937596A/en
Priority to PCT/CN2022/102329 priority patent/WO2023206794A1/en
Publication of CN114937596A publication Critical patent/CN114937596A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a manufacturing method and a structure of an IGBT device, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises an active region, a transition region and a terminal region, and comprises a first main surface and a second main surface which are opposite; performing first ion implantation on the first main surfaces of the transition region and the terminal region to form a doped terminal layer crossing the transition region and the terminal region, performing second ion implantation on the edge of the terminal region to form a stop ring, and performing thermal process propulsion treatment; etching the first main surface of the terminal area to form a groove for communicating the doped terminal layer and the stop ring, and forming a field oxide layer in the groove; carrying out second ion general injection on the first main surface to form a carrier storage doped region, and then carrying out thermal process propulsion treatment; a front structure and a back structure are formed. The invention can perform general injection when the current carrier storage doped region in the active region is manufactured, and does not need a mask, thereby saving the manufacturing cost and simultaneously avoiding the current carrier storage layer from causing great influence on the withstand voltage of the IGBT.

Description

Manufacturing method and structure of IGBT device
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a manufacturing method and a structure of an IGBT device.
Background
The IGBT as a hybrid power device has the characteristics of MOS structure input and bipolar structure output, so that the IGBT has the advantages of high input impedance of the MOSFET, small power of a driving circuit, simplicity in driving, high switching speed and small switching loss, and has the advantages of large current density, strong current processing capacity and low conduction saturation voltage drop of a bipolar power transistor. After the development of the last forty years, the IGBT has become the mainstream power device in the power electronic system, and with the continuous development of the IGBT technology, higher requirements are undoubtedly put forward on the performance and cost of the IGBT.
The terminal adopted by the IGBT at present is mainly a field ring field plate terminal, the terminal is simple in process, high in reliability and widely used, but the terminal is low in utilization rate which can only reach 70% -80% at most. As the IGBT market becomes more competitive, higher utilization terminals are increasingly being used, such as Junction Termination Extension (JTE) terminals and lateral variable doping (VLD) terminals, which can reach over 90% utilization. Compared with a field ring field plate terminal, the same voltage resistance can adopt a smaller-sized terminal, namely the total size of the IGBT Die is reduced, and the manufacturing cost of the IGBT is further reduced.
By adding a carrier storage layer (CS) on the front side of the IGBT, it has become a common method to reduce the turn-on voltage drop of the IGBT, such as the csbt from Mitsubishi corporation. The carrier storage layer is generally realized by injecting phosphorus into the front surface of the IGBT, and the injection dosage is generally 1e12-2e13cm -2 The implantation dose at the end of the field plate of the field ring is generally 1e14-2e15cm -2 The difference between the injection dosage of the CS layer and the injection dosage of the terminal is 2 orders of magnitude, so that the injection dosage of the CS layer hardly influences the doping concentration of an IGBT transition region, and the terminal region is shielded by a thick oxide layer, so that the field ring field plate terminal structure IGBT and the CS layer can be directly and commonly injected without a mask. However, the implantation dose for JTE or VLD termination is typically 1e12-2e13cm -2 The dosage of the transition region is equivalent to that of CS implantation, although the terminal region is also shielded by a thick oxide layer, the doping concentration of the transition region is obviously influenced by the dosage of the CS implantation, and even the transition region of the IGBT can be inverted into an N type. To avoid overdosing the IGBT with the CS implant doseThe doping concentration of the transition region is affected, and a CS mask is generally added for CS implantation of the JTE or VLD terminal structure IGBT to cover the transition region and the terminal region, so that CS is only implanted in the active region. Therefore, an additional CS mask is needed during CS implantation, which increases the IGBT manufacturing cost.
Therefore, how to implant phosphorus into the CS layer without using a CS mask for IGBTs having JTE or VLD termination structures without affecting the breakdown voltage of the IGBTs is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method and a structure for manufacturing an IGBT device, which are used to solve the problem that in the IGBT process of the JTE or VLD termination structure in the prior art, an additional mask is required to be added when injecting a carrier storage doped region, so that the IGBT manufacturing cost is increased.
To achieve the above and other related objects, the present invention provides a method for manufacturing an IGBT device, the method at least comprising:
1) providing a substrate, wherein the substrate comprises an active region, a transition region and a terminal region, and the active region, the transition region and the terminal region respectively comprise a first main surface and a second main surface which are opposite;
2) performing a first ion implantation on the first main faces of the transition region and the termination region to form a doped termination layer spanning the transition region and the termination region, and performing a second ion implantation on the edge of the termination region to form a cut-off ring, followed by a thermal process drive-in process;
3) etching the first main surface of the terminal area to form a groove communicating the doped terminal layer and the stop ring on the first main surface, and forming a field oxide layer in the groove;
4) carrying out second ion implantation on the first main surface to form a carrier storage doped region on the first main surface, and then carrying out thermal process advancing treatment;
5) and performing a front surface process on the first main surface, and performing a back surface process on the second main surface to respectively form a front surface structure and a back surface structure, thereby completing the manufacturing of the IGBT device.
Optionally, in the step 2), the first ion implantation dose is between 1e14cm -2 ～2e15cm -2 The implantation energy is between 60keV and 200 keV; the second ion implantation dosage is between 1e15cm -2 ～5e15cm -2 And the implantation energy is between 60keV and 200 keV.
Optionally, in the step 2), the temperature of the thermal process advancing treatment is between 1100 ℃ and 1200 ℃, and the time is between 10min and 60 min.
Optionally, in the step 3), the etching depth of the trench is between 0.5 μm and 1 μm.
Optionally, in the step 3), etching is performed on the first main surface of the termination region by using a dry etching process, so as to form a trench communicating the doped termination layer and the stop ring, where depths of the trench are uniform.
Optionally, in the step 3), etching is performed on the first main surface of the termination region by using a dry etching process and then by using a wet etching process, so as to form a trench communicating the doped termination layer and the stop ring, where a depth of the trench gradually becomes deeper from the doped termination layer toward the stop ring.
Optionally, in the step 3), a thickness of the field oxide layer is between 1.5 μm and 2.5 μm.
Optionally, in the step 4), the implantation dose of the second ion implantation is between 1e12cm -2 ～2e13cm -2 And the implantation energy is between 60keV and 200 keV.
Optionally, in the step 4), the temperature of the thermal process advancing treatment is 1100-1250 ℃, and the time is 200-400 min.
The present invention also provides an IGBT device structure, which at least includes: the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises an active region, a transition region and a terminal region, and the active region, the transition region and the terminal region respectively comprise a first main surface and a second main surface which are opposite; the doped terminal layer crosses over the transition region and the terminal region, and the stop ring is formed at the edge of the terminal region; a trench communicating between the doped termination layer and the stop ring; a field oxide layer formed in the trench; the carrier storage doping region is formed in the first main surface of the active region and the transition region; a front structure formed on the first main surface; and a back structure formed on the second main surface.
Optionally, the doping terminal layer of the transition region comprises a first ion doping concentration between 1e13cm -2 -1e16cm -2 In the meantime.
Optionally, the depth of the trench is between 0.5 μm and 1 μm.
Optionally, the depth of the trench is uniform or gradually becomes deeper from the doped termination layer toward the stop ring.
Optionally, the thickness of the field oxide layer is between 1.5 μm and 2.5 μm.
As described above, the method and structure for manufacturing an IGBT device according to the present invention have the following advantageous effects:
by controlling the ion implantation dosage of doping terminal layers (JTE or VLD terminals) of the transition region and the terminal region, the time of thermal process propulsion treatment before trench etching and the trench etching depth, the doping concentration of the doping terminal layers in the terminal region is adjusted, so that the IGBT of the JTE or VLD terminal structure can directly perform common injection of a carrier storage doping region in an active region without a mask when performing ion implantation of the carrier storage doping region in the active region, the doping concentration of the transition region is not influenced, and the influence on the withstand voltage value of the IGBT is avoided. Meanwhile, the height difference of the surface of the chip caused by the thick oxide layer of the terminal area is reduced, and the subsequent photoetching process for manufacturing the IGBT is facilitated.
The manufacturing method of the IGBT device can perform common injection of the carrier storage doping region for the IGBT with the JTE or VLD terminal structure, a mask is not needed in the step, so that a mask can be omitted, the manufacturing cost is saved, and in addition, the manufacturing method of the IGBT device is compatible with the existing IGBT process.
Drawings
Fig. 1 to fig. 5c show schematic structural diagrams presented by steps of a method for manufacturing an IGBT device according to an embodiment of the present invention, wherein fig. 5a, fig. 5b, and fig. 5c show schematic structural diagrams of the IGBT device according to an embodiment of the present invention.
Description of the element reference numerals
101 substrate
102 doped termination layer
103 stop ring
104 groove
105 field oxide layer
106 carrier storage doped region
107 gate dielectric layer
108 polysilicon layer
109 source doped region
110 body doped region
111 insulating layer
112 front metal layer
113 collector region
114 hydrogen ion doped region
115 back side metal
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example 1
The present embodiment provides a manufacturing method of an IGBT device, the manufacturing method at least including the steps of:
as shown in fig. 1, step 1) is performed first, a substrate 101 is provided, where the substrate 101 includes an active region, a transition region, and a termination region, and the active region, the transition region, and the termination region all include a first main surface and a second main surface opposite to each other.
The substrate 101 may be a monocrystalline silicon substrate. The substrate 101 may also be made of other materials in some embodiments, such as but not limited to silicon germanium or germanium. In other embodiments, the substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The doping concentration and thickness of the substrate 101 can be set according to the performance of the IGBT device, such as withstand voltage.
As shown in fig. 1, step 2) is then carried out, a first ion implantation is carried out on the first main faces of the transition region and the termination region to form a doped termination layer 102 spanning the transition region and the termination region, and a second ion implantation is carried out on the edge of the termination region to form a stop ring 103, followed by a thermal process drive-in process.
As an example, a pattern mask is first formed on the first main surface of the substrate 101, the pattern mask exposing the transition region and the region of the termination region where the doped termination layer 102(JTE or VLD termination) is to be formed, and then a first ion implantation is performed on the first main surface, the first ion implantation dosage being between 1e14cm -2 ～2e15cm -2 The implantation energy is between 60keV and 200keV, and in one embodiment, the first ion implantation dose is 1e14cm -2 The implantation energy is 100 keV. In yet another specific embodiment, the first ion implantation dose is 2e15cm -2 The implantation energy is 150 keV.
As an example, the second ion implantation dose is between 1e15cm -2 ～5e15cm -2 And the implantation energy is between 60keV and 200 keV. In one embodiment, the second ion implantation dose is 2e15cm -2 The second ion implantation energy is 100 keV. In yet another specific embodiment, the second ion implantation dose is 4e15cm -2 And the second ion implantation energy is 150 keV.
It should be noted that the first ion implantation may be P-type boron implantation, and the corresponding second ion implantation is N-type phosphorus implantation, but of course, the first ion implantation may also be N-type phosphorus implantation, and the corresponding second ion implantation is P-type boron implantation. In this embodiment, the IGBT device is implemented based on an N-type doped silicon wafer substrate, and the first ion implantation is P-type boron implantation, and the corresponding second ion implantation is N-type phosphorus implantation.
As an example, the temperature of the thermal process advancing treatment is between 1100 ℃ and 1200 ℃, and the time is between 10min and 60 min. In a specific embodiment, the temperature of the thermal process advancement process is 1150 ℃ for 30 min. In yet another specific embodiment, the thermal process advancing treatment is at 1180 ℃ for 50 min.
The doped termination layer 102 in fig. 1 is formed after a first ion implantation and thermal process drive-in process. The doping concentration of the doping termination layer 102 may be controlled by the first ion implantation and the thermal process advancing process.
As shown in fig. 2a and 3, step 3) is then performed, in which the first main surface of the termination region is subjected to an etching process, so as to form a trench 104 in the first main surface, which communicates the doped termination layer 102 and the stop collar 103, and to form a field oxide layer 105 in the trench 104.
By way of example, the etching depth of the trench 104 is 0.5 μm to 1 μm. In a specific embodiment, the etching depth of the trench 104 is 0.6 μm. In a further specific embodiment, the etching depth of the trench 104 is 0.8 μm.
As an example, as shown in fig. 2a, a dry etching process may be used to etch the first main surface of the termination region to form a trench 104 communicating the doped termination layer 102 and the stop collar 103, wherein the depth of the trench 104 is uniform.
In another specific embodiment, as shown in fig. 2b and 2c, a dry etching process may be first used, and then a wet etching process is used to etch the first main surface of the termination region to form a trench 104 communicating the doped termination layer 102 and the stop ring 103, where a depth of the trench 104 gradually becomes deeper from the doped termination layer toward the stop ring. Specifically, as shown in fig. 2b, a plurality of trenches 104 are formed by etching using a dry etching process, the width of each trench 104 gradually widens from the doped termination layer 102 toward the stop ring 103, the wider the trench 104 is and the deeper the trench 104 is due to the loading effect of the dry etching, and then the individual trenches 104 are connected into one trench by wet isotropic etching, as shown in fig. 2 c.
By partially etching the doped terminal layer 102 in the terminal region, the doping concentration requirement of the terminal region can be met after the residual doping ions in the doped terminal layer 102 are advanced in the subsequent thermal process, and meanwhile, the high concentration of the doped terminal layer 102 in the transition region can ensure that the transition region is not inverted when the carrier storage doping region 106 is subsequently subjected to common injection, the voltage resistance of the IGBT device is hardly influenced, a mask can be omitted when the common injection is directly performed, and the manufacturing cost is greatly reduced.
As an example, as shown in fig. 3, the field oxide layer 105 may be formed by a furnace tube, and the thickness of the field oxide layer 105 is between 1.5 μm and 2.5 μm. In a specific embodiment, the thickness of the field oxide layer 105 is 2 μm. In yet another specific embodiment, the thickness of the field oxide layer 105 is 2.3 μm. The field oxide layer 105 may be used to block the termination region when the subsequent carrier storage doping region 106 is commonly implanted.
As shown in fig. 4, step 4) is followed by performing second ion implantation on the first main surface to form a carrier storage doped region 106 on the first main surface, and then performing a thermal process advancing process.
Since the field oxide layer 105 is formed on the first main surface of the termination region, and has a blocking effect during normal injection, the carrier storage doped region 106 is formed only in the first main surfaces of the active region and the transition region.
As an example, the implantation dose of the second ion implantation is between 1e12cm -2 ～2e13cm -2 And the implantation energy is between 60keV and 200 keV. In a specific embodiment, the implantation dose of the second ion implantation is 1e12cm -2 The implantation energy is 100 keV. In yet another specific embodiment, the implantation dose of the second ion implantation is 2e12cm -2 The implantation energy is 150 keV. In this embodiment, the second ion implantation is N-type phosphorous ion implantation. The carrier storing doped region 106 is mainly formed in the active region, and the carrier storing doped region 106 formed in the transition region does not cause a large doping concentration in the entire transition regionThe influence of (c).
As an example, the temperature of the thermal process advancing treatment is between 1100 ℃ and 1250 ℃, and the time is between 200min and 400 min. In a specific embodiment, the temperature of the thermal process advancement process is 1150 ℃ for 250 min. In yet another specific embodiment, the thermal process advancing treatment is at a temperature of 1200 ℃ for a time of 300 min. The thermal process advancing treatment makes the depth of the doped termination layer 102 in the termination region deeper, which can meet the doping concentration and depth requirements of the termination region.
In view of the above, it can be seen that, through etching and thermal process advancing treatment, the doping concentrations of the doped termination layer 102 in the transition region and the termination region can be different, so that the concentration requirement of the termination region can be ensured, and the influence on the concentration of the transition region when the active region carrier storage doped region 106 is in a normal injection state can be greatly reduced.
The thermal process advancement process may optionally be followed by a planarization process, such as chemical mechanical polishing, to bring the top of the field oxide layer flush with the first major surface of the substrate, which is shown in fig. 3 and 4 for ease of illustration.
As shown in fig. 5a, step 5) is finally performed, a front surface process is performed on the first main surface, and a back surface process is performed on the second main surface, so as to form a front surface structure and a back surface structure respectively, thereby completing the manufacture of the IGBT device.
Specifically, the front surface structure includes a trench gate structure disposed on the first main surface of the active region, a source doped region 109, a body doped region 110 disposed on the first main surface of the active region and the transition region, and an insulating layer 111 and a front surface metal layer 112 disposed on the first main surface, the trench gate structure penetrates through the body doped region 110 to the substrate 101, the trench gate structure includes a trench extending to a position below the body doped region 110, a gate dielectric layer 107 located on a sidewall of the trench, and a polysilicon layer 108 filled in the trench, the source doped region 109 is disposed in the body doped region 110 and located on a side surface of the trench gate structure, the body doped region 110 is disposed above the carrier storage doped region 106, and the front surface metal layer 112 is connected to the source doped region 109 and the body doped region 110.
In the present embodiment, the body doping region 110 is doped P-type, and the source doping region 109 is doped N-type.
The front metal layer 112 includes an emitter metal layer and a gate metal layer, the emitter metal passes through a connecting hole and is connected with the source doping region 109 and the body doping region 110 of the active region, and simultaneously passes through a connecting hole and is connected with the body doping region 110 of the transition region, the gate metal layer is connected with the polysilicon layer 108 in the trench gate structure, in this embodiment, the gate metal layer is arranged above the field oxide layer 105 of the terminal region to save the area of the active region, and simultaneously, the electricity of the trench gate structure is conveniently led out.
As an example, the front metal layer 112 may be AlCu or AlSiCu.
The back surface structure includes a collector region 113, a hydrogen ion doped region 114, and a back surface metal 115 formed on the second main surface. The collector region 113 can be a conductive dopant ion such as boron or a compound of boron.
For example, the hydrogen ion doped region 114 has a plurality of hydrogen ion doped layers having different hydrogen ion doping concentrations, and the hydrogen ion doping concentrations of the plurality of hydrogen ion doped layers are gradually decreased from the second main surface toward the first main surface. The hydrogen ion doping region 114 contains hydrogen ion implantation dosage of 5e 11-5 e16cm -2 The hydrogen ion implantation energy is between 200KeV and 1.5 MeV. Specifically, the hydrogen ion doped region 114 has 1 to 4 hydrogen ion doped layers with different hydrogen ion doping concentrations, and in this embodiment, by adjusting the dose and energy of each hydrogen ion implantation, a hydrogen ion doped layer with a plurality of different doping peaks can be formed in the substrate 101 after annealing, for example, in this embodiment, the hydrogen ion doped region 114 has four different doping peaks 141, 142, 143, and 144.
By way of example, the back metal 115 may be an Al/Ti/Ni/Ag metal stack.
It should be noted that fig. 5a shows the IGBT device structure in which the field oxide layer 105 is subjected to the planarization process. Fig. 5b shows the IGBT device structure with different thicknesses at various places of the field oxide layer. Fig. 5c shows the IGBT device structure with the field oxide layer 105 not subjected to the planarization process.
Example 2
As shown in fig. 5a, the present invention also provides an IGBT device that can be manufactured by the manufacturing method described in embodiment 1, the device including at least: the semiconductor device comprises a substrate 101, wherein the substrate 101 comprises an active region, a transition region and a terminal region, and the active region, the transition region and the terminal region respectively comprise a first main surface and a second main surface which are opposite; a doped termination layer 102 and a stop ring 103, wherein the doped termination layer 102 spans the transition region and the termination region, and the stop ring 103 is formed at the edge of the termination region; a trench 104 communicating between the doped termination layer 102 and the stop ring 103; a field oxide layer 105 formed in the trench 104; a carrier storage doped region 106 formed in a first major surface of the active region and the transition region; a front surface structure formed on the first main surface; and a back structure formed on the second main surface.
For example, the substrate 101 may be a single crystalline silicon substrate. The substrate may also be made of other materials in some embodiments, such as but not limited to silicon germanium or germanium. In other embodiments, the substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The doping concentration and thickness of the substrate 101 can be set according to the performance of the IGBT device, such as withstand voltage.
As an example, the doping termination layer of the transition region comprises a first ion doping concentration of between 1e13cm -2 -1e16cm -2 In between.
Illustratively, the depth of the trench 104 is between 0.5 μm and 1 μm. In a specific embodiment, the etching depth of the trench 104 is 0.6 μm. In yet another specific embodiment, the trench 104 is etched to a depth of 0.8 μm.
As an example, the depth of the trench 104 is uniform throughout or gradually becomes deeper from the doped termination layer 102 toward the stopper ring 103. FIG. 5a is a view showing the structure of the grooves 04 having the same depth; fig. 5b shows a structure in which the groove 104 becomes deeper gradually.
As an example, the thickness of the field oxide layer 105 is between 1.5 μm and 2.5 μm. In a specific embodiment, the thickness of the field oxide layer 105 is 2 μm. In yet another specific embodiment, the thickness of the field oxide layer 105 is 2.3 μm. The field oxide layer 105 may be used to block the termination region when the carrier storing doped region 106 is commonly implanted. Fig. 5c is a schematic structural diagram illustrating that the field oxide layer 105 is not planarized.
Specifically, the front structure includes a trench gate structure disposed on the first main surface of the active region, a source doped region 109, a body doped region 110 disposed on the first main surface of the active region and the transition region, and an insulating layer 111 and a front metal layer 112 disposed on the first main surface, the trench gate structure penetrates through the body doped region 110 into the substrate 101, the trench gate structure includes a trench extending to the lower side of the body doped region 110, a gate dielectric layer 107 located on the sidewall of the trench, and a polysilicon layer 108 filled in the trench, the source doped region 109 is disposed in the body doped region 110 and located on the side surface of the trench gate structure, the body doped region 110 is disposed above the carrier storage doped region 106, and the front metal layer 112 is connected to the source doped region 109 and the body doped region 110.
In the present embodiment, the body doping region 110 is doped P-type, and the source doping region 109 is doped N-type.
The front metal layer 112 includes an emitter metal layer and a gate metal layer, the emitter metal passes through a connecting hole and is connected with the source doping region 109 and the body doping region 110 of the active region, and simultaneously passes through a connecting hole and is connected with the body doping region 110 of the transition region, the gate metal layer is connected with the polysilicon layer 108 in the trench gate structure, in this embodiment, the gate metal layer is arranged above the field oxide layer 105 of the terminal region to save the area of the active region, and simultaneously, the electricity of the trench gate structure is conveniently led out.
As an example, the front metal layer 112 may be AlCu or AlSiCu.
The back surface structure includes a collector region 113, a hydrogen ion doped region 114, and a back surface metal 115 formed on the second main surface. The collector region 113 can be a conductive dopant ion such as boron or a compound of boron.
For example, the hydrogen ion doped region 114 has a plurality of hydrogen ion doped layers having different hydrogen ion doping concentrations, and the hydrogen ion doping concentrations of the plurality of hydrogen ion doped layers are gradually decreased from the second main surface toward the first main surface. The hydrogen ion doping region 114 contains hydrogen ion implantation dosage of 5e 11-5 e16cm -2 The hydrogen ion implantation energy is between 200KeV and 1.5 MeV. Specifically, the hydrogen ion doped region 114 has 1 to 4 hydrogen ion doped layers with different hydrogen ion doping concentrations, and in this embodiment, by adjusting the dose and energy of each hydrogen ion implantation, a hydrogen ion doped layer with a plurality of different doping peaks can be formed in the substrate 101 after annealing, for example, in this embodiment, the hydrogen ion doped region 114 has four different doping peaks 141, 142, 143, and 144.
As an example, the back metal 115 may be a metal stack of Al/Ti/Ni/Ag.
In summary, the present invention provides a method and a structure for manufacturing an IGBT device, by controlling the ion implantation dose of the doping terminal layers (JTE or VLD terminal) of the transition region and the terminal region, the time of thermal process advancement processing before trench etching, and the trench etching depth, the doping concentration of the doping terminal layers in the terminal region is adjusted, so that the IGBT with the JTE or VLD terminal structure can directly perform common injection of the carrier storage doping region without a mask when performing ion implantation of the carrier storage doping region in the active region, and the doping concentration in the transition region is not significantly affected, thereby avoiding affecting the voltage withstanding value of the IGBT.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (14)

1. A method of manufacturing an IGBT device, characterized in that the method of manufacturing at least comprises:
1) providing a substrate, wherein the substrate comprises an active region, a transition region and a terminal region, and the active region, the transition region and the terminal region respectively comprise a first main surface and a second main surface which are opposite;
2) performing a first ion implantation on the first main faces of the transition region and the termination region to form a doped termination layer spanning the transition region and the termination region, and performing a second ion implantation on the edge of the termination region to form a stop ring, followed by a thermal process drive-in process;
3) etching the first main surface of the terminal area to form a groove communicating the doped terminal layer and the stop ring on the first main surface, and forming a field oxide layer in the groove;
4) carrying out second ion implantation on the first main surface to form a carrier storage doped region on the first main surface, and then carrying out thermal process advancing treatment;
5) and performing a front surface process on the first main surface, and performing a back surface process on the second main surface to respectively form a front surface structure and a back surface structure, thereby completing the manufacture of the IGBT device.
2. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 2), the first ion implantation dose is between 1e14cm -2 ～2e15cm -2 The implantation energy is between 60keV and 200 keV; the second ion implantation dosage is between 1e15cm -2 ～5e15cm -2 Between 60keV and 200keV。
3. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 2), the temperature of the thermal process propulsion treatment is between 1100 and 1200 ℃, and the time is between 10 and 60 min.
4. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 3), the etching depth of the groove is between 0.5 and 1 μm.
5. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 3), etching is performed on the first main surface of the termination region by using a dry etching process to form a trench communicating the doped termination layer and the stop ring, wherein the depth of each trench is consistent.
6. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 3), etching is performed on the first main surface of the terminal region by using a dry etching process and then by using a wet etching process to form a trench communicating the doped terminal layer and the stop ring, wherein the depth of the trench gradually becomes deeper from the doped terminal layer to the stop ring.
7. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 3), the thickness of the field oxide layer is between 1.5 μm and 2.5 μm.
8. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 4), the implantation dose of the second ion implantation is between 1e12cm -2 ～2e13cm -2 And the implantation energy is between 60keV and 200 keV.
9. The method of manufacturing an IGBT device according to claim 1, characterized in that: in the step 4), the temperature of the thermal process propulsion treatment is 1100-1250 ℃, and the time is 200-400 min.
10. An IGBT device structure, characterized in that the IGBT device structure comprises at least:
the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises an active region, a transition region and a terminal region, and the active region, the transition region and the terminal region respectively comprise a first main surface and a second main surface which are opposite;
the doped terminal layer crosses over the transition region and the terminal region, and the stop ring is formed at the edge of the terminal region;
a trench communicating between the doped termination layer and the stop ring;
a field oxide layer formed in the trench;
the carrier storage doped region is formed in the first main surfaces of the active region and the transition region;
a front structure formed on the first main surface;
and a back surface structure formed on the second main surface.
11. The IGBT device structure of claim 10, wherein: the doped termination layer of the termination region comprises a first ion doping concentration of 1e13cm -2 -1e16cm -2 In the meantime.
12. The IGBT device structure of claim 10, wherein: the depth of the groove is between 0.5 and 1 mu m.
13. The IGBT device structure of claim 10, wherein: the depth of the groove is consistent or gradually deepens from the doped terminal layer to the stop ring direction.
14. The IGBT device structure of claim 10, wherein: the thickness of the field oxide layer is between 1.5 mu m and 2.5 mu m.
CN202210475742.4A 2022-04-29 2022-04-29 Manufacturing method and structure of IGBT device Pending CN114937596A (en)

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