CN110047934B - Semiconductor power device capable of reducing number of photomask layers and preparation method thereof - Google Patents
Semiconductor power device capable of reducing number of photomask layers and preparation method thereof Download PDFInfo
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- CN110047934B CN110047934B CN201910376363.8A CN201910376363A CN110047934B CN 110047934 B CN110047934 B CN 110047934B CN 201910376363 A CN201910376363 A CN 201910376363A CN 110047934 B CN110047934 B CN 110047934B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 44
- 239000007924 injection Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 33
- 238000000151 deposition Methods 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000001459 lithography Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The invention provides a semiconductor power device for reducing the number of photomask layers and a preparation method thereof, wherein a first groove and a second groove are arranged on the upper surface of a first conductive epitaxial layer of a semiconductor substrate, and hard mask layers are arranged between the first groove and the second groove and on the first surfaces of the second groove; the first groove and the periphery thereof, the second groove and the periphery thereof are provided with gate oxide layers, the first groove and the second groove are filled with conductive polysilicon, and insulating medium layers are covered on the first groove and the periphery thereof, the second groove and the periphery thereof and the upper part of the hard mask layer; a first conductive type injection layer and a second conductive type injection layer are arranged between the first grooves and the periphery of the second grooves from top to bottom; the first trench and the insulating dielectric layer over the periphery thereof are covered with a metal layer. On the basis of ensuring the performance and the reliability of the device, the number of photomask layers is reduced to 3, and the manufacturing cost is effectively reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor power device capable of reducing the number of photomask layers and a preparation method thereof.
Background
The high-voltage and high-power trench type MOS device product still uses a six-layer photoetching and even eight-layer photoetching manufacturing technology, and has the advantages of high cost, long manufacturing period and low competitiveness.
The prior Chinese patent ZL 201010003953.5 discloses a groove type high-power MOS device and a manufacturing method thereof, and relates to a groove type MOS device manufactured by utilizing a 6-time photoetching technology; the basic process steps comprise:
(1) Growth of field oxide layer
(2) Active area etching (lithography level 1)
(3) Etching the protection ring region, implanting ions, and performing heat treatment to form a terminal protection structure (lithography level 2)
(4) Hard mask growth and selective etching, defining the region of trench etching (lithography level 3)
(5) Selective trench etching using a hard mask
(6) Growing gate oxide layer, depositing conductive polysilicon
(7) Etching conductive polysilicon
(8) Implanting second type impurity ions, and performing heat treatment to form a second type well layer
(9) Forming a first type impurity ion implantation region by lithography, implanting first type impurity ions, and forming a first type implantation region by heat treatment (lithography level 4)
(10) Depositing an insulating dielectric layer
(11) Defining lead hole region by photoetching, etching to form lead hole (photoetching level 5)
(12) Depositing a metal layer, and forming a metal electrode by photolithography (photolithography level 6)
The trench type MOS device disclosed in the patent ZL 201010003953.5 adopts a manufacturing technology of six times of photoetching, and has the advantages of high manufacturing cost, long production period and low competitiveness.
The prior Chinese patent ZL 200710302461.4 discloses a deep groove high-power MOS device and a manufacturing method thereof, and relates to a groove type power MOS device manufactured by four times of photoetching technology; the structure of the invention is shown in figure 4 of the patent ZL 200710302461.4, and the basic idea of the invention is as follows: a trench MOS device comprises an active region of a central region and a peripheral terminal protection structure in a top plan; the terminal protection structure consists of a groove-type protection ring and a groove-type stop ring; the groove of the protection ring is positioned on the lightly doped second conduction type injection layer, and the groove is deep into the first conduction type injection layer below the second conduction type injection layer.
With the continuous maturity of the design and the process of the trench type MOS device, the market competition is increasingly strong, the manufacturing cost of the device is reduced, and the performance and the reliability of the device are increasingly important. On the premise of not influencing the performance of the device, reducing the photoetching times in the manufacturing process of the device is one of important means for reducing the cost of the device.
Disclosure of Invention
The technical problems solved by the invention are as follows: the semiconductor power device capable of reducing the number of photomask layers and the preparation method of the semiconductor power device are provided, the manufacturing process is simple, and the manufacturing cost is effectively reduced.
The technical solution for realizing the purpose of the invention is as follows:
the semiconductor power device comprises a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped first conductive type substrate and a lightly doped first conductive type epitaxial layer, and the first surface is the upper surface of the first conductive type epitaxial layer;
a first groove and a second groove in the vertical direction are formed in the first surface, and hard mask layers are arranged between the first groove and the second groove and on the first surfaces of the second grooves;
a gate oxide layer is arranged above the first surface of the inner wall of the first groove and the periphery of the first groove, above the first surface of the inner wall of the second groove and the periphery of the second groove, conductive polysilicon is filled in the first groove and the second groove, and insulating medium layers are covered above the first groove, above the periphery of the second groove and above the hard mask layer; a first conductive type injection layer and a second conductive type injection layer are sequentially arranged between the first trenches and below the peripheral gate oxide layer of the second trench from top to bottom, the second conductive type injection layer is blocked and separated through a hard mask layer, and the first conductive type injection layer between the second trenches is blocked and separated through the hard mask layer and the second conductive type injection layer to form a terminal structure with a voltage-resistant function; the first trench and the insulating dielectric layer above the periphery thereof are covered with a metal layer which extends downwards into the lead hole, and the lead hole penetrates through the insulating dielectric layer, the gate oxide layer at the periphery of the first trench and the first conductive type injection layer at the periphery of the first trench to the upper part of the second conductive type injection layer at the periphery of the first trench.
The method for preparing the semiconductor power device for reducing the photomask layer number comprises the following steps:
step 1, providing a first conductive type semiconductor substrate with two opposite surfaces, wherein the first conductive type semiconductor substrate comprises a heavily doped first conductive type substrate and a lightly doped first conductive type epitaxial layer, and the upper surface of the first conductive type epitaxial layer is defined as a first surface;
step 2, depositing a hard mask layer on the first surface, defining a hard mask etching area through photoetching and etching the hard mask layer to form a hard mask for trench etching;
step 3, etching the first surface to form a groove in the vertical direction, wherein the groove comprises a first groove and a second groove; the width of the hard mask layer between the second trenches is larger than that between the first trenches, and the width of the hard mask layer between the first trenches is smaller than twice the thickness of the hard mask layer.
Step 4, etching the hard mask layer on the first surface by adopting a wet method, wherein the etching degree is one half of the width of the hard mask layer between the second grooves, the hard mask layer on the periphery of the first grooves is completely etched, the hard mask layer on the periphery of the second grooves is partially etched, part of the hard mask layer on the first surface between the first grooves and the second grooves is reserved, and part of the hard mask layer on the first surface between the second grooves is reserved;
step 5, growing a gate oxide layer on the first surface, wherein the gate oxide layer covers the first surface of the inner wall and the periphery of the first groove, and the first surface of the inner wall and the periphery of the second groove;
step 6, depositing and etching conductive polysilicon to fill the first groove and the second groove with the conductive polysilicon;
step 7: implanting second conductivity type impurities from the gate oxide layer and annealing, and forming a second conductivity type implantation layer between the first trenches and below the gate oxide layer at the periphery of the first trenches, wherein the second conductivity type implantation layer is positioned at the upper part of the first conductivity type epitaxial layer; the second conductivity type implant layer is blocked from isolation by the hard mask layer.
Step 8: implanting first conductivity type impurities from the gate oxide layer and annealing, forming a first conductivity type implantation layer between the first trenches and below the gate oxide layer at the periphery of the second trenches, wherein the first conductivity type implantation layer is positioned above the second conductivity type implantation layer; the first conductive type injection layer is blocked and separated through the hard mask layer to prevent leakage channels, and a terminal structure with a voltage withstanding function is formed.
Step 9: depositing an insulating dielectric layer above the gate oxide layer, above the conductive polysilicon and above the hard mask layer, wherein the insulating dielectric layer covers the gate oxide layer, the conductive polysilicon and above the hard mask layer;
step 10: and defining a region of the lead hole through hole photoetching, sequentially etching and penetrating the insulating dielectric layer, the gate oxide layer at the periphery of the first groove and the first conductive type injection layer at the periphery of the first groove to the upper part of the second conductive type injection layer at the periphery of the first groove to form the lead hole, and depositing a metal layer in the lead hole and the periphery thereof, wherein the metal layer fills the lead hole and covers the insulating dielectric layer at the periphery of the lead hole.
Compared with the prior art, the invention has the technical effects that: on the basis of ensuring the performance and the reliability of the device, the number of photomask layers is reduced to 3, and the manufacturing cost is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a structure for depositing a hard mask layer on a first surface of a semiconductor substrate;
FIG. 2 is a schematic diagram of the structure after etching the first trench and the second trench;
FIG. 3 is a schematic diagram of the structure after etching the hard mask layer;
FIG. 4 is a schematic diagram of the structure after the gate oxide layer is grown;
FIG. 5 is a schematic diagram of the structure after deposition and etching of conductive polysilicon;
fig. 6 is a schematic structural view after implanting P-type impurity ions;
fig. 7 is a schematic structural diagram after implanting N-type impurity ions;
FIG. 8 is a schematic diagram of the structure after deposition of an insulating dielectric layer;
FIG. 9 is a schematic diagram of the structure after deposition of a metal layer;
reference numerals meaning: 1: n-type substrate, 2: n-type epitaxial layer, 3: first groove, 4: second groove, 5: hard mask layer, 6: gate oxide, 7: conductive polysilicon, 8: insulating medium layer, 9: p-type implant layer, 10: n-type implanted layer, 11: metal layer, 12: and (5) a lead hole.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
The invention provides a semiconductor power device for reducing the number of photomask layers, as shown in fig. 9, which comprises a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped N-type substrate 1 and a lightly doped N-type epitaxial layer 2, a first surface is the upper surface of the N-type epitaxial layer 2, and a second surface is the lower surface of a first conductive type substrate;
the first surface is provided with a first groove 3 and a second groove 4 in the vertical direction, and a hard mask layer 5 is arranged on the first surface between the first groove 3 and the second groove 4 and between the second grooves 4;
a gate oxide layer 6 is arranged above the first surface of the inner wall of the first groove 3 and the periphery thereof, above the first surface of the inner wall of the second groove 4 and the periphery thereof, conductive polysilicon 7 is filled in the first groove 3 and the second groove 4, and an insulating medium layer 8 is covered above the first groove 3 and the periphery thereof, above the second groove 4 and the periphery thereof and above the hard mask layer 5; an N-type injection layer 10 and a P-type injection layer 9 are sequentially arranged below the gate oxide layer 6 between the first grooves 3 and the periphery thereof and below the gate oxide layer 6 at the periphery of the second grooves 4 from top to bottom, the P-type injection layer 9 is blocked and separated through the hard mask layer 5, and the N-type injection layer 10 between the second grooves 4 is blocked and separated through the hard mask layer 5 and the P-type injection layer 9 to form a terminal structure with a voltage withstanding function; the first trench 3 and the insulating dielectric layer 8 above the periphery thereof are covered with a metal layer 11, the metal layer 11 extends downwards into a lead hole 12, and the lead hole 12 penetrates through the insulating dielectric layer 8, the gate oxide layer 6 at the periphery of the first trench 3, the N-type injection layer 10 at the periphery of the first trench 3 and reaches the upper part of the P-type injection layer 9 at the periphery of the first trench 3.
The invention also provides a method for preparing the semiconductor power device for reducing the number of layers of the photomask, which comprises the following steps:
step 1, providing an N-type semiconductor substrate with two opposite surfaces, wherein the N-type semiconductor substrate comprises a heavily doped N-type substrate 1 and a lightly doped N-type epitaxial layer 2, and the upper surface of the N-type epitaxial layer 2 is defined as a first surface, as shown in fig. 1;
step 2, depositing a hard mask layer 5 on the first surface, defining a hard mask etching area through photoetching and etching the hard mask layer 5 as shown in fig. 1, so as to form a hard mask for trench etching;
step 3, etching the first surface to form a trench in the vertical direction, wherein the trench comprises a first trench 3 and a second trench 4, as shown in fig. 2, the width of a hard mask layer 5 between the second trenches 4 is larger than the width of the hard mask layer 5 between the first trenches 3, and the width of the hard mask layer 5 between the first trenches 3 is smaller than twice the thickness of the hard mask layer 5;
step 4, etching the hard mask layer 5 on the first surface by adopting a wet method, wherein the etching degree is one half of the width of the hard mask layer 5 between the second grooves 4, the hard mask layer 5 at the periphery of the first grooves 3 is completely etched, the hard mask layer 5 at the periphery of the second grooves 4 is partially etched, part of the hard mask layer 5 on the first surface between the first grooves 3 and the second grooves 4 is reserved, and part of the hard mask layer 5 on the first surface between the second grooves 4 is reserved, as shown in fig. 3;
step 5, growing a gate oxide layer 6 on the first surface, wherein the gate oxide layer 6 covers the first surface of the inner wall and the periphery of the first trench 3, the first surface of the inner wall and the periphery of the second trench 4, as shown in fig. 4;
step 6, depositing and etching the conductive polysilicon 7 to fill the conductive polysilicon 7 in the first groove 3 and the second groove 4, as shown in fig. 5;
step 7: p-type impurities are injected from the gate oxide layer 6 and annealed, a P-type injection layer 9 is formed between the first trenches 3 and below the gate oxide layer 6 at the periphery of the first trenches and below the gate oxide layer 6 at the periphery of the second trenches 4, the P-type injection layer 9 is positioned at the upper part of the N-type epitaxial layer 2, and the P-type injection layer 9 is blocked and separated by the hard mask layer 5, as shown in fig. 6;
step 8: n-type impurities are injected from the gate oxide layer 6 and annealed, an N-type injection layer 10 is formed between the first trenches 3 and below the gate oxide layer 6 at the periphery of the first trenches and below the gate oxide layer 6 at the periphery of the second trenches 4, the N-type injection layer 10 is positioned above the P-type injection layer 9, the N-type injection layer 10 is blocked and separated by the hard mask layer 5, leakage channels are prevented, and a terminal structure with a voltage withstanding function is formed, as shown in fig. 7;
step 9: depositing an insulating dielectric layer 8 above the gate oxide layer 6, above the conductive polysilicon 7 and above the hard mask layer 5, the insulating dielectric layer 8 covering the gate oxide layer 6, the conductive polysilicon 7 and the hard mask layer 5, as shown in fig. 8;
step 10: the region of the lead hole 12 is defined by hole lithography, the insulating dielectric layer 8, the gate oxide layer 6 at the periphery of the first trench 3, the N-type injection layer 10 at the periphery of the first trench 3 are sequentially etched and penetrated to the upper part of the P-type injection layer 10 at the periphery of the first trench 3, the lead hole 12 is formed, a metal layer 11 is deposited in the lead hole 12 and at the periphery thereof, and the metal layer 11 fills the lead hole 12 and covers the insulating dielectric layer 8 at the periphery of the lead hole 12, as shown in fig. 9.
While only a few embodiments of the present invention have been described, it should be noted that modifications could be made by those skilled in the art without departing from the principles of the present invention, which modifications are to be regarded as being within the scope of the invention.
Claims (2)
1. The semiconductor power device is characterized by comprising a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped first conductive type substrate and a lightly doped first conductive type epitaxial layer, the first surface is the upper surface of the first conductive type epitaxial layer, and the second surface is the lower surface of the first conductive type substrate;
a first groove and a second groove in the vertical direction are formed in the first surface, and hard mask layers are arranged between the first groove and the second groove and on the first surfaces of the second grooves;
a gate oxide layer is arranged above the first surface of the inner wall of the first groove and the periphery of the first groove, above the first surface of the inner wall of the second groove and the periphery of the second groove, conductive polysilicon is filled in the first groove and the second groove, and insulating medium layers are covered above the first groove, above the periphery of the second groove and above the hard mask layer; a first conductive type injection layer and a second conductive type injection layer are sequentially arranged between the first trenches and below the peripheral gate oxide layer of the second trench from top to bottom, the second conductive type injection layer is blocked and separated through a hard mask layer, and the first conductive type injection layer between the second trenches is blocked and separated through the hard mask layer and the second conductive type injection layer to form a terminal structure with a voltage-resistant function; the first trench and the insulating dielectric layer above the periphery thereof are covered with a metal layer which extends downwards into the lead hole, and the lead hole penetrates through the insulating dielectric layer, the gate oxide layer at the periphery of the first trench and the first conductive type injection layer at the periphery of the first trench to the upper part of the second conductive type injection layer at the periphery of the first trench.
2. A method of making the semiconductor power device of claim 1, comprising the steps of:
step 1, providing a first conductive type semiconductor substrate with two opposite surfaces, wherein the first conductive type semiconductor substrate comprises a heavily doped first conductive type substrate and a lightly doped first conductive type epitaxial layer, and the upper surface of the first conductive type epitaxial layer is defined as a first surface;
step 2, depositing a hard mask layer on the first surface, defining a hard mask etching area through photoetching and etching the hard mask layer to form a hard mask for trench etching;
step 3, etching the first surface to form grooves in the vertical direction, wherein the grooves comprise first grooves and second grooves, the width of a hard mask layer between the second grooves is larger than that between the first grooves, and the width of the hard mask layer between the first grooves is smaller than twice the thickness of the hard mask layer;
step 4, etching the hard mask layer on the first surface by adopting a wet method, wherein the etching degree is one half of the width of the hard mask layer between the second grooves, the hard mask layer on the periphery of the first grooves is completely etched, the hard mask layer on the periphery of the second grooves is partially etched, part of the hard mask layer on the first surface between the first grooves and the second grooves is reserved, and part of the hard mask layer on the first surface between the second grooves is reserved;
step 5, growing a gate oxide layer on the first surface, wherein the gate oxide layer covers the first surface of the inner wall and the periphery of the first groove, and the first surface of the inner wall and the periphery of the second groove;
step 6, depositing and etching conductive polysilicon to fill the first groove and the second groove with the conductive polysilicon;
step 7: implanting second conductivity type impurities from the gate oxide layer and annealing, forming a second conductivity type implantation layer between the first trenches and below the gate oxide layer at the periphery of the first trenches, wherein the second conductivity type implantation layer is positioned at the upper part of the first conductivity type epitaxial layer, and the second conductivity type implantation layer is blocked and separated through the hard mask layer;
step 8: injecting first conductivity type impurities from the gate oxide layer and annealing, forming a first conductivity type injection layer below the gate oxide layer between and around the first trenches and below the gate oxide layer around the second trenches, wherein the first conductivity type injection layer is positioned above the second conductivity type injection layer, and the first conductivity type injection layer is blocked and blocked by the hard mask layer to prevent leakage channels, so that a terminal structure with a voltage withstanding function is formed;
step 9: depositing an insulating dielectric layer above the gate oxide layer, above the conductive polysilicon and above the hard mask layer, wherein the insulating dielectric layer covers the gate oxide layer, the conductive polysilicon and above the hard mask layer;
step 10: and defining a region of the lead hole through hole photoetching, sequentially etching and penetrating the insulating dielectric layer, the gate oxide layer at the periphery of the first groove and the first conductive type injection layer at the periphery of the first groove to the upper part of the second conductive type injection layer at the periphery of the first groove to form the lead hole, and depositing a metal layer in the lead hole and the periphery thereof, wherein the metal layer fills the lead hole and covers the insulating dielectric layer at the periphery of the lead hole.
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| CN105826205A (en) * | 2016-05-31 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid power device and structure |
| CN106449753A (en) * | 2016-07-14 | 2017-02-22 | 中航（重庆）微电子有限公司 | Low on-state resistance groove power MOS (Metal Oxide Semiconductor) device structure and fabrication method thereof |
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2019
- 2019-05-07 CN CN201910376363.8A patent/CN110047934B/en active Active
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| CN105826205A (en) * | 2016-05-31 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for groove grid power device and structure |
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| CN110047934A (en) | 2019-07-23 |
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