JP4970660B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an insulated gate power MOSFET in which a large number of transistor cells having a so-called trench structure, in which a gate electrode is formed in a concave groove formed from the surface of a semiconductor layer, and a method for manufacturing the same. More specifically, the present invention relates to a gate drive semiconductor device for power and a method for manufacturing the same that can increase the number of transistor cells per unit area, reduce the on-resistance, obtain a large current, and can be manufactured by a simple manufacturing process. .
[0002]
[Prior art]
A conventional trench-structured high-power gate-driven power MOS transistor employs a structure in which a large number of transistor cells are formed in parallel in a matrix to increase the current. For example, as shown in FIG. ⁺ An n-type semiconductor layer (epitaxial growth layer) 21 serving as a drain region is epitaxially grown on a semiconductor substrate 21a, and concave grooves are formed in the semiconductor layer 21 in a lattice shape, and a gate oxide film 24 is formed on the inner surface thereof. At the same time, polysilicon serving as the gate electrode 25 is buried. Then, a p-type channel diffusion region 22 is formed in the surrounding semiconductor layer 21, and n is formed on the periphery of the gate electrode 25 on the surface. ⁺ By forming the shaped source region 23, the channel region 22a is formed in the vertical direction in contact with the gate oxide film 24. Furthermore, SiO formed on the surface ₂ A contact hole is formed in the insulating film 26 made of, for example, a source electrode 27 is formed so as to be in ohmic contact with the exposed source region 23 and the channel diffusion region 22, and a drain electrode 28 is formed on the back surface of the semiconductor substrate 21a. .
[0003]
The planar structure of the gate electrode in this transistor cell is formed in an arbitrary shape such as a square, a pentagon, or a hexagon. Also, these transistors are often connected to an inductive load such as a motor. In that case, when the operation is turned off, an electromotive force in the reverse direction may be applied, and the transistor is destroyed. In order to prevent this, as described above, a method of forming a protective diode in the reverse direction between the source and the drain by connecting the source electrode 27 to the channel diffusion region 22 is employed.
[0004]
[Problems to be solved by the invention]
In the transistor for large current as described above, it is important to make as many transistor cells as possible in a chip of a predetermined size and to lower the on-resistance. In order to reduce the on-resistance, it is effective to increase the channel width as much as possible. In the transistor having the structure described above, the width of the channel region 22a formed around the gate electrode (the length around the gate electrode) It is preferable to make the total as much as possible. However, in this type of conventional transistor, since the source electrode is in ohmic contact with the channel diffusion region on the surface of the semiconductor layer, both the source region and the channel diffusion region need to be exposed on the surface of the semiconductor layer, and the source Since a mask overlay margin for diffusing the region and a mask overlay margin between the contact hole and the source region are required, for example, in the structure shown in FIG. 5, the contact hole size C is 2 to 2.5 μm. The cell interval (pitch between the gate electrodes) A is about 4.5 to 5 μm. In this case, the width B of the source region is about 0.8 to 1 μm. Therefore, there is a problem that the cell cannot be sufficiently miniaturized and the on-resistance cannot be sufficiently reduced.
[0005]
The present invention has been made to solve such a problem, and has the same size chip area, the gate width is increased, the on-resistance is reduced, and the trench structure is insulated. It is an object of the present invention to provide a semiconductor device having a gate drive type element.
[0006]
Another object of the present invention is to provide a source in both the channel diffusion region and the source region while making the pitch of the transistor cell very small by making the source electrode contact in a self-aligning manner without requiring a mask alignment margin. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be brought into contact with an electrode, has a very small area, and can be obtained by a simple process.
[0007]
[Means for Solving the Problems]
As a result of intensive investigations to obtain a semiconductor device capable of obtaining a large current with a small chip size by reducing the on-resistance of the insulated gate semiconductor device, the present inventor usually has Al on the surface of the semiconductor layer. If the metal film is provided as an electrode directly, it spikes into the semiconductor layer and causes problems such as short circuits. Therefore, it is common knowledge to intervene a barrier metal layer. It has been found that the thickness of the metal film to be deposited and the conditions such as heat treatment can be controlled, and that the spiked alloy layer can sufficiently provide ohmic contact with the semiconductor layer. In addition, by thickly oxidizing the surface of the gate electrode of the trench structure, the gate electrode can be formed even if the source electrode metal provided directly on the surface is spiked without providing an insulating film on the surface and forming a contact hole. It was found that ohmic contact can be made in both the source region and the channel diffusion region formed in the vertical direction without short-circuiting the source electrode.
[0008]
As a result, it is necessary to form a mask when forming the groove to form the gate electrode, but after forming the groove, the mask can be manufactured in a self-aligned manner, and the margin for mask alignment is This eliminates the need for a very small semiconductor device and makes the manufacturing process very simple.
[0009]
A semiconductor device according to the present invention includes a concave groove formed in a lattice shape in a semiconductor layer of the first conductivity type, a gate oxide film formed on the inner surface of the concave groove, and embedded in the concave groove. The surface is dug deeper than the surface of the semiconductor layer And the semiconductor layer around the gate electrode of surface ~ side A channel diffusion region of the second conductivity type formed on the surface, and a surface of the channel diffusion region ~ side And a source region of the first conductivity type further formed on the surface side of the gate electrode, and deeper than the surface of the source region by oxidation of the gate electrode And shallower than the bottom surface of the source region From the position To the surface of the source region The source electrode made of a metal film directly formed on the insulating film surface and the surface of the source region, and the source region exposed between the adjacent insulating films, the metal of the source electrode Has an alloy layer formed by spikes in the source region and the channel diffusion region, and a drain electrode provided in electrical connection with the semiconductor layer.
[0010]
With this structure, since the insulating film is thickly formed on the surface side of the gate electrode by oxidation of the gate electrode, the insulating film is not formed on the surface and the contact hole that exposes the source region is not formed. Even if the source electrode is formed directly on the surface of the semiconductor layer and spiked by heat treatment, there is no possibility of short circuit with the gate electrode. That is, since it is not necessary to form an insulating film on the surface of the semiconductor layer and provide a contact hole, the source region and the source electrode can be formed by self-alignment only by forming the gate electrode. As a result, there is no need for a mask alignment margin, the distance between transistor cells can be made very narrow, and the number of transistor cells per unit area can be increased, so that the on-resistance can be reduced. A high current MOSFET with a large current can be obtained.
[0011]
The surface side of the gate electrode is dug deeper than the surface of the semiconductor layer, an insulating film is formed on the surface of the gate electrode by oxidation of the gate electrode, and the surface of the insulating film is a surface substantially close to the surface of the source region By forming the gate electrode and the insulating film so that the surface becomes flat, the surface becomes flat, the source electrode (source wiring) also becomes flat, and the source electrode (Al) can be flattened and made uniform and stable. There is an advantage that can be spiked.
[0012]
A method of manufacturing a semiconductor device according to the present invention includes: (a) forming a groove in a lattice shape in a semiconductor layer of the first conductivity type serving as a drain region; and (b) inside the groove. Surface of To gate oxide film And in the groove Gate electrode Digging so that the surface is deeper than the surface of the semiconductor layer Forming a channel diffusion region and a source region in the vertical direction around the gate electrode by sequentially diffusing a second conductivity type impurity and a first conductivity type impurity in the semiconductor layer in any step; And (d) oxidizing the surface of the gate electrode to form a depth deeper than the surface of the source region. And shallower than the bottom surface of the source region From the position To the surface of the source region Forming an insulating film and exposing the source region; and (e) forming a source electrode made of a metal film on the surface of the exposed source region and the insulating film formed on the gate electrode; (F) Heat treatment is performed to spike the source electrode metal film into the source region and the channel diffusion region in the entire source region exposed between the adjacent insulating films, so that the source electrode A step of forming an alloy layer in ohmic contact with each of the region and the channel diffusion region; and (g) a step of forming a drain electrode by being electrically connected to the semiconductor layer.
[0013]
By performing this method, it is not necessary to provide an insulating film on the surface of the semiconductor layer to form a contact hole, and the source electrode can be formed by self-alignment, so that the cell interval can be extremely narrowed. Not only can the on-resistance be reduced, but also the manufacturing process becomes very simple and can be manufactured at low cost.
[0014]
Before forming the insulating film on the surface side of the gate electrode, the surface of the gate electrode is etched deeper than the surface of the semiconductor layer by etching, and the surface of the insulating film formed by the step (d) and exposed by the step (d). By forming the insulating film so that the source region is substantially flush with the source region, the surface can be flattened while being a trench structure type, and a semiconductor device having a power MOSFET with a flat surface can be obtained. .
[0015]
As another method, before forming an insulating film on the surface side of the gate electrode, an antioxidant film is formed on the surface of the semiconductor layer around the gate electrode, and only the surface of the gate electrode is oxidized. A thick oxide film can be formed only on the gate electrode without back-up.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, the semiconductor device of the present invention and the manufacturing method thereof will be described with reference to the drawings. The semiconductor device according to the present invention includes a semiconductor layer 1 of a first conductivity type (for example, n-type), as shown in FIG. A groove 11 is formed, a gate oxide film 4 is formed on the inner surface of the groove 11, and a gate electrode 5 made of polysilicon or the like is embedded in the groove 11. Then, a channel diffusion region 2 of the second conductivity type (for example, p-type) is formed on the surface of the semiconductor layer 1 around the gate electrode 5, and an n-type source region 3 is formed on the surface of the channel diffusion region 2 by diffusion or the like. Has been. On the surface side of the gate electrode 5, the insulating film 6 is formed thick so as to obtain a sufficient breakdown voltage by oxidizing the gate electrode. Furthermore, the source electrode 7 is formed by providing a metal film directly on the surface of the insulating film 6 and the surface of the source region 3. The metal of the source electrode 7 spikes into the source region 3 and the channel diffusion region 2 to form an alloy layer 7a to be in ohmic contact and to be electrically connected to the semiconductor layer 1 and provided with the drain electrode 8. . In the figure, the semiconductor substrate 1a and the drain electrode 8 are written thinner than the other portions, and an accurate thickness relationship is not shown as a whole.
[0017]
The semiconductor layer 1 is made of silicon, for example, and has a high impurity concentration. ⁺ An n-type semiconductor layer made of silicon epitaxially grown to a thickness of several μm to several tens of μm, for example, about 5 μm, on the semiconductor substrate 1a. By diffusing the n-type impurity, the p-type channel diffusion region 2 has a thickness of about 1 μm, and n ⁺ Each source region 3 is formed in a thickness of about 0.5 μm.
[0018]
As shown in a plan view before providing the source electrode in FIG. 1 (b), the pitch is 0.2 to 1 μm wide (E) in a grid pattern with an interval (A) of about 0.7 to 2.0 μm. ), A groove 11 is formed at a depth of about 1.5 μm, and a gate electrode 5 made of polysilicon or the like is formed in the groove 11 via a gate oxide film 4.
[0019]
As will be described later, the gate electrode 5 is formed only in the concave groove 11 by removing the polysilicon film in portions other than the concave groove 11 by etching back after, for example, polysilicon is deposited on the entire surface. Has been. At this time, etching is further performed by etching from the surface of the semiconductor layer (source region 3) to about 0.1 to 0.3 μm by continuing the etch back (the surface of the source region 3 has an oxide film and is etched). Not) Then, by heat treatment, polysilicon is much easier to oxidize than single crystal silicon, so that the exposed portion of the gate electrode 5 surface is particularly oxidized, a thick oxide film 6 is formed on the surface, and the entire surface is etched back. Thus, if the surface of the source region 3 is exposed, the source region 3 and the insulating film 6 are formed on substantially the same plane. A metal film made of Al or the like for forming the source electrode 7 is formed on the surface to a thickness of about 3 μm.
[0020]
In this state, by performing a heat treatment at about 400 ° C. for about 30 minutes, Si is diffused into Al together with the interaction at the interface between the source electrode 7 and the source region 3. The alloy layer with Si advances into the semiconductor layer, and an alloy layer 7a having a sharp tip is formed as shown in FIG. The alloy layer 7a is formed so that the spike depth to the inside thereof changes depending on the temperature and time of the heat treatment, enters the channel diffusion region 2, and does not penetrate the channel diffusion region 2.
[0021]
That is, as described above, the present inventor conducted extensive studies to obtain a semiconductor device capable of reducing the on-resistance of the insulated gate semiconductor device and obtaining a large current with a small chip size. The amount of the metal film provided on the surface entering the semiconductor layer by the spike can be controlled by controlling conditions such as the thickness of the metal film to be deposited and heat treatment, and FIG. As shown in FIG. 5, it has been found that only the source region 3 and the channel diffusion region 2 can be in ohmic contact and can be prevented from penetrating the channel diffusion region 2.
[0022]
The depth of the alloy layer, that is, the so-called spike depth, was deepened by increasing the temperature of the heat treatment or by increasing the time of the heat treatment, and could be controlled very accurately. For example, when an Al film is provided on Si, the spike starts at about 300 ° C., but it is most efficient to perform at about 400 ° C., and the depth of the spike can be accurately controlled. For example, by performing heat treatment at about 400 ° C. for about 30 minutes, spikes are made to a depth of about 0.6 to 0.8 μm, and the source region 3 of about 0.5 μm and the channel diffusion region 2 of about 1 μm are formed. With the diffusion depth, by performing the alloying process under these conditions, there is no possibility of penetrating the channel diffusion region 2 while taking ohmic contact in both layers. As a result, as described above, by forming a portion where the channel diffusion region 2 and the source region 3 overlap in the vertical direction, if a metal such as Al is spiked from the surface, direct ohmic contact with both layers is achieved. I was able to let
[0023]
If the exposed size of the source region 3 is, for example, about 1 μm or less per side, the lateral direction is blocked by the insulating film 6 obtained by oxidizing the gate electrode 5 and is spiked only in the longitudinal direction. Enter with a spike of books. In order to increase the number of transistor cells, the interval between the gate electrodes 5 is preferably narrow (the exposed area of the source region 3 is small), and usually spikes in a shape as shown in FIG. 1, but larger, for example, 10 μm It was also found that with a contact hole of about a degree, spikes can be made by dividing into a number of lines without spikes uniformly.
[0024]
With the structure shown in FIG. 1, a mask is required only when forming the groove, but after that, there is no need to form a mask with reference to the groove 11, and the source is self-aligned. Region 3 and source electrode 7 can be formed. As a result, the gate electrode width E and the interval D can be reduced to the limit of the mask accuracy, and at the minimum, D = 0.4 μm and E = 0.3 μm, that is, the cell interval A is set to about 0.7 μm. Can do.
[0025]
For example, in the conventional structure shown in FIG. 5, the width E of the gate oxide film 4 around the gate electrode 5 is 0.5 .mu.m, and the distance D between adjacent gate oxide films 4 is 4.5 .mu.m (cell spacing A is 5 .mu.m). According to the present invention, when E is the same and D is narrowed to 1 μm, the distance A between the transistor cells becomes 1.5 μm, and the number of cells per unit area is (5 / 1.5). ² = 11.1 times. On the other hand, the length of the periphery of the gate oxide film, which becomes the gate width that affects the on-resistance, is 1 / 4.5 (reduction ratio of the length of the periphery of the gate electrode (4D)) × 11.1 (cells per unit area). Number) = 2.47, the resistance is 1 / 2.47, that is, the current can be increased 2.47 times. Similarly, when D is set to 0.5 μm, the current can be increased by 2.78 times. The accuracy of the exposure technique in the current microfabrication using, for example, i-line can be about 0.35 μm. If this technique is applied, D can be reduced to 0.35 μm, and the width E of the gate electrode is also reduced to 0. Since it can be about .35 μm (A = 0.7), the number of cells is (5 / 0.7) ² = 51 times and the current is (0.35 / 4.5) × 51 = 4 times.
[0026]
Next, a manufacturing method of the MOSFET having the trench structure will be described with reference to FIGS. First, as shown in FIG. ⁺ An n-type semiconductor layer 1 is epitaxially grown on the type semiconductor substrate 1a by about 5 μm. Then, the surface is made of SiO by CVD or the like. ₂ The film 12 is formed to a thickness of about 0.5 μm and patterned to expose the gate electrode formation site in a lattice pattern. Then, the concave groove 11 having a depth of about 1.5 μm is formed by dry etching such as RIE.
[0027]
Thereafter, as shown in FIG. 2B, the gate oxide film 4 is formed on the inner surface of the groove 11 by performing a heat treatment at about 900 to 1000 ° C. for about 30 minutes in an atmosphere of water vapor. Then, polysilicon is deposited on the entire surface, and polysilicon is embedded in the concave grooves. Thereafter, etch back is performed by the RIE method, and the polysilicon film deposited on the surface other than the groove 11 is removed by etching. At this time, when the polysilicon film other than the inside of the groove 11 is etched, the oxide film 12 is exposed and the etching is stopped. On the other hand, since the polysilicon used as the gate electrode 5 in the groove 11 continues to be etched, only the polysilicon film in the groove 11 is further dug. Etching is performed until the digging depth reaches about 0.1 to 0.3 μm from the surface of the semiconductor layer. The reason for etching deeper than the surface of the semiconductor layer is to form an insulating film on the gate electrode 5 by self-alignment.
[0028]
Thereafter, the oxide film 12 on the surface is removed by etching, p-type impurities such as boron are diffused to form a p-type channel diffusion region 2, and then n-type impurities such as phosphorus are diffused to form n ⁺ A source region 3 having a shape is formed. Each channel diffusion region 2 is diffused so that the depth is about 0.7 to 1 μm from the surface, and the source region 3 is about 0.3 to 0.5 μm.
[0029]
Next, by performing a heat treatment at about 900 ° C. for about 30 minutes in an atmosphere of water vapor, the single crystal silicon is hardly oxidized, whereas the polysilicon is easily oxidized, so that only the surface of the gate electrode 5 is oxidized. Then, as shown in FIG. 2C, the oxide film 6 is formed in the dug portion in the concave groove 11.
[0030]
Next, the oxide film 12 on the surface and the insulating film 6 on the gate electrode 5 are etched by etching back from the entire surface by the RIE method to expose the source region 3. As a result, the exposed surface of the source region 3 and the surface of the insulating film 6 on the gate electrode 5 are formed to be substantially flat. Then, for example, Al is deposited on the entire surface to a thickness of about 3 μm by sputtering, thereby forming the source electrode 7 as shown in FIG.
[0031]
Next, nitrogen (N ₂ ) By performing a heat treatment at about 400 ° C. for about 30 minutes in an atmosphere, the metal material of the source electrode 7 is alloyed with Si of the semiconductor layer as shown in FIG. Spikes into the diffusion region 2 form the alloy layer 7a. In this case, as described above, the depth of the spike changes depending on the temperature and time of this heat treatment, so that it enters the channel diffusion region 2 to obtain an ohmic contact, and penetrates the channel diffusion region 2 to the semiconductor layer 1. It is necessary to control the heat treatment conditions so as not to reach it. Note that the spike does not advance in the lateral direction due to the insulating film 6. Thereafter, a metal having a thickness of about 2 μm is formed on the back surface of the semiconductor substrate 1a by sputtering or the like to form the drain electrode 8, thereby obtaining a MOSFET having a trench structure shown in FIG.
[0032]
In the example shown in FIG. 2, the groove 11 is formed and the gate oxide film 4 and the gate electrode 5 are formed, and then the diffusion for the channel diffusion region 2 and the source region 3 is performed. After the epitaxial growth, the channel diffusion region 2 and the source region 3 are formed on the entire surface, and then the groove 11 may be formed to form the gate electrode 5 or the like, or the source electrode 7 in the step of FIG. The channel diffusion region 2 and the source region 3 may be formed before the formation.
[0033]
FIG. 4 is a similar cross-sectional explanatory view showing still another manufacturing method. In this example, an insulating film on the surface of the gate electrode is made thicker by providing an oxidation preventive film such as silicon nitride in a portion other than the gate electrode and oxidizing it.
[0034]
First, as shown in FIG. 4A, n is the same as the above example. ⁺ The n-type semiconductor layer 1 is epitaxially grown on the type semiconductor substrate 1a by about 5 μm and the surface thereof is oxidized to obtain SiO 2. ₂ The film 12 has a thickness of about 0.02 μm, and an antioxidant film such as Si _Three N _Four The film 13 is sequentially formed by using a low pressure CVD method or the like to a thickness of about 0.2 μm, and is patterned to expose the gate electrode formation site in a lattice shape. Then, the concave groove 11 having a depth of about 1.5 μm is formed by dry etching such as RIE. SiO ₂ The film 12 is provided for stress relaxation and the like.
[0035]
Thereafter, as in FIG. 2B, a gate oxide film 4 is formed on the inner surface of the concave groove 11, polysilicon is deposited on the entire surface, etched back by the RIE method, and polysilicon is formed in the concave groove. The buried gate electrode 5 is formed (FIG. 4B).
[0036]
Next, by performing a heat treatment at about 900 ° C. for about 30 minutes in an atmosphere of water vapor, _Three N _Four Under the film 13 is not oxidized, but the exposed polysilicon surface is oxidized, and a thick oxide film 6 is formed on the surface of the gate electrode 5 as shown in FIG.
[0037]
Next, Si _Three N _Four Film 13 and SiO ₂ By removing each of the films 12 by etching, a thick oxide film 6 is formed on the gate electrode 5 and the surrounding semiconductor layer 1 is exposed as shown in FIG. 4D. Thereafter, p-type impurities such as boron are diffused to form a p-type channel diffusion region 2, and then n-type impurities such as phosphorus are diffused to form n ⁺ A source electrode 7 is formed by depositing Al on the entire surface to a thickness of about 3 μm by sputtering, for example, and has a structure similar to that shown in FIG. . Thereafter, Al is spiked in the same manner as described above to obtain a semiconductor device similar to the structure shown in FIG.
[0038]
By using this method, the contact of the source electrode can be formed by the self-alignment method while forming a thick oxide film on the surface of the gate electrode without performing etch back by RIE or the like. As a result, it is possible to obtain a semiconductor device capable of increasing the current with a small gate resistance by increasing the gate width without damaging the semiconductor layer.
[0039]
In the above-described example, silicon is used as the semiconductor substrate 1a and the growing semiconductor layer. However, the use of SiC can further reduce the series resistance and the on-resistance, which is suitable for increasing the current. ing.
[0040]
Further, the above example is an example of a vertical MOSFET, but the same applies to an insulated gate bipolar transistor (IGBT) in which a bipolar transistor is further formed in the vertical MOSFET.
[0041]
【Effect of the invention】
According to the present invention, the channel diffusion region, the source region, and the source electrode can be formed by self-alignment only by forming a mask when forming a trench (concave groove) in a MOSFET having a trench structure, and without forming a mask afterward. Since the ohmic contact between the source region and the channel diffusion region can be obtained, the manufacturing process is very simple, the margin for mask alignment is not required, and the transistor cell can be miniaturized to the mask accuracy for forming the trench. Can do. As a result, the number of transistor cells per unit area can be greatly increased, the on-resistance can be lowered to increase the current, and the performance of the power gate drive transistor can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory view of a cross section and a plan view showing an embodiment of a semiconductor device according to the present invention.
2 is an explanatory cross-sectional view showing a manufacturing step of the MOSFET shown in FIG. 1. FIG.
3 is an explanatory cross-sectional view showing a manufacturing step of the MOSFET shown in FIG. 1. FIG.
4 is a cross-sectional explanatory view showing a manufacturing process of another method of manufacturing the MOSFET shown in FIG. 1. FIG.
FIG. 5 is a cross-sectional explanatory view showing the structure of a MOSFET having a conventional trench structure.
[Explanation of symbols]
1 Semiconductor layer
2-channel diffusion region
3 Source area
4 Gate oxide film
5 Gate electrode
7 Source electrode
7a Alloy layer

Claims (7)

Grooves formed in a lattice pattern in the first conductivity type semiconductor layer, a gate oxide film formed on the inner surface of the groove, and embedded in the groove, the surface being deeper than the surface of the semiconductor layer and dug Ru gate electrode, the channel diffusion region of a second conductivity type formed on the surface side of the semiconductor layer around the gate electrode, of the first conductivity type is further formed on the surface side of the channel diffusion region and the source region, the oxidation of the gate electrode on the surface side of the gate electrode deeply from the surface of the source region, and an insulating film formed from a position shallow than the bottom surface of the source region to the surface of the source region And the source electrode composed of a metal film directly provided on the insulating film surface and the source region surface, and the source region exposed between the adjacent insulating films, the metal of the source electrode is the source region and A semiconductor device having an alloy layer formed by spiking the Yaneru diffusion region, and a drain electrode provided electrically connected to the semiconductor layer. 2. The semiconductor device according to claim 1, wherein the shape exposed on the surface of the source region surrounded by the gate oxide film is a quadrangular shape with a side not exceeding 1 μm . 3. The semiconductor device according to claim 1, wherein the alloy layer formed by the spike has a sharp tip. The semiconductor device according to claim 1, wherein the semiconductor layer in which the channel diffusion region and the source region are formed is made of silicon, and the source electrode is made of Al. The first conductivity type semiconductor layer is n ⁺ An n-type epitaxial semiconductor layer epitaxially grown on a semiconductor substrate, the channel diffusion region is a p-type diffusion region, and a source region formed thereon is n ⁺ The semiconductor device according to claim 1, wherein the semiconductor device is a shaped diffusion region. (A) forming a groove in a lattice shape in the semiconductor layer of the first conductivity type serving as a drain region;
(B) forming a gate oxide film on the surface in the groove and forming a gate electrode in the groove so that the surface is deeper than the surface of the semiconductor layer ;
(C) forming a channel diffusion region and a source region in the vertical direction around the gate electrode by sequentially diffusing a second conductivity type impurity and a first conductivity type impurity in the semiconductor layer in any of the steps;
And (d) oxidizing the surface of the gate electrode deeply than the surface of the source region, and, with an insulating film from a position shallow than the bottom surface of the source region to the surface of said source region, said source Exposing the area;
(E) forming a source electrode made of a metal film on the exposed source region surface and the surface of the insulating film formed on the gate electrode;
(F) Heat treatment is performed to spike the source electrode metal film into the source region and the channel diffusion region in the entire source region exposed between the adjacent insulating films, so that the source electrode Forming an alloy layer in ohmic contact with each of the region and the channel diffusion region;
(G) forming a drain electrode by being electrically connected to the semiconductor layer. The method according to claim 6 , wherein before forming an insulating film on the surface side of the gate electrode, an antioxidant film is formed on the surface of the semiconductor layer around the gate electrode to oxidize only the gate electrode surface.

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