JP2000277531A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of a source offset by forming a trench gate conductor layer and a gate insulating film in a trench and on the main surface of the periphery of the trench in a semiconductor device having a FET of a trench gate structure, in which a conductor to be a gate is provided in a trench extending on the main surface of a semiconductor substrate. SOLUTION: A trench gate 4 of a MISFET of this type is formed in a trench extending to an n-type second semiconductor layer 2a to be a drain region from the main surface of a semiconductor substrate via a multi-layer gate insulating film 5 formed of a thermal oxide film and a deposition film, and is formed of polycrystalline silicon doped with impurities, for example. The top surface of the trench gate 4 is higher than the surface of a third semiconductor layer 2c to be a source region, that is, the main surface of the semiconductor substrate. Therefore, this can prevent the trench gate 4 from being off the source region, that is, a source offset, even if the source region is made shallow. It is desirable that the top surface of the trench gate 4 is formed almost flat or convexly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a semiconductor device having a trench gate structure.

[0002]

2. Description of the Related Art Power transistors are used in power amplification circuits, power supply circuits, converters, power supply protection circuits, and the like. However, these power transistors require high breakdown voltage and large current to handle large power. Required.

A MISFET (Metal Insulator Semicond
In the case of an uctor field effect transistor), a method for achieving a large current can be easily achieved by increasing the channel width. In order to avoid an increase in chip area due to such an increase in channel width, for example, a mesh gate structure is used.

In the mesh gate structure, gates are arranged in a lattice pattern in a plane, so that the channel width per unit chip area can be increased. The FET having the mesh gate structure is described in Ohm's "Semiconductor Handbook", pp. 429-430.
Conventionally, such a power FET has been used in a planar structure because the process is simple and an oxide film serving as a gate insulating film is easily formed.

However, in the FET, the channel length is determined by the gate length. Therefore, in the case of the FET having the planar structure, when the gate is made thinner, the channel length becomes shorter and a short channel effect occurs. Therefore, when the gate is made thin, there is a problem that the allowable current is reduced, and there is a limit to miniaturization. For this reason, an FET having a trench gate structure has been conceived because it is possible to further improve the degree of integration of cells and to reduce on-resistance.

In the trench gate structure, a conductor layer serving as a gate is provided in a groove extending through a main surface of a semiconductor substrate via an insulating film, a deep portion of the main surface is used as a drain region, and a surface layer of the main surface is used as a drain region. A source region, and a semiconductor layer between the drain region and the source region is a channel formation region. This type of MISFET having a trench gate structure is disclosed in, for example, JP-A-8-23092.

[0007]

As the element becomes finer, the source region is made shallower. As the shallowing proceeds, the source region becomes thinner, and it becomes difficult to accurately position the trench gate with respect to this thin source region. When an error in the trench gate causes a source offset in which the trench gate deviates from the source region, the source offset causes the FET to not function.

[0008] With the progress of miniaturization of elements, the shallowness of the source region is further promoted. As the shallowing proceeds, the source region becomes thinner, and it becomes difficult to accurately position the trench gate with respect to this thin source region.

Further, since the end of the gate insulating film is located at the corner of the groove, it may be damaged in the process of forming the trench gate. Operation failure may occur.

An object of the present invention is to provide a technique capable of solving such a problem and preventing occurrence of a source offset. An object of the present invention is to provide a technique capable of solving such a problem and preventing damage to a gate insulating film. An object of the present invention is to provide an FET having a trench gate structure in which shallowness is achieved. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. FET having a trench gate structure in which a conductor layer serving as a gate is provided in a groove extending in a main surface of a semiconductor substrate.
A trench gate conductor layer and a gate insulating film are formed on the main surface of the semiconductor substrate in the trench and on the periphery of the trench.

In the manufacturing method, an insulating film is formed on the main surface of the semiconductor layer, the insulating film is patterned into a pattern corresponding to the trench gate, and the trench gate is formed on the semiconductor substrate layer using the patterned insulating film as a mask. Forming a groove to be formed, a side surface of the insulating film is receded from an upper end of the groove by isotropic etching, and a gate insulating film and a trench gate are formed on the semiconductor substrate main surface in the groove and on the periphery of the groove. Then, a channel layer and a source region which are in contact with the gate insulating film in the trench are formed.

[0013]

According to the above-described means, the source offset can be prevented by forming the upper surface of the trench gate conductor layer higher than the main surface of the semiconductor substrate. Further, since the gate insulating film and the conductive layer serving as the trench gate and the conductive layer of the gate are formed on the main surface of the semiconductor substrate around the trench, damage to the end of the gate insulating film can be prevented. .

[0014]

Embodiments of the present invention will be described below. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view showing a power MISFET having a trench gate structure which is a main part of a semiconductor device according to an embodiment of the present invention, and FIG.
3 is an equivalent circuit diagram of the MISFET shown in FIG. FIG.
FIG. 4 is an enlarged plan view of an essential part showing a middle part, and FIG.
It is a longitudinal cross-sectional view along the aa line in the inside.

The MISFET of the present embodiment is formed on an n + type semiconductor substrate 1 made of, for example, single crystal silicon, and on a semiconductor substrate on which an epitaxial layer 2 is formed by, for example, epitaxial growth. This MISFET is provided in a rectangular ring shape along the outer periphery of the semiconductor substrate, and is surrounded by a plate-shaped field insulating film 3 having a rectangular portion inside a corner portion (indicated by double oblique lines in FIG. 3). Formed within.

In the region, a plurality of cells having a trench gate structure having a hexagonal or flat octagonal planar shape are regularly arranged, and the gates are arranged in a lattice pattern in a plane, and the cells are arranged in parallel. It consists of a connected mesh gate structure.

In each cell, the n − -type first semiconductor layer 2 a formed on the semiconductor substrate 1 serves as a drain region,
The p-type second semiconductor layer 2b formed on the semiconductor layer 2a becomes a base region where a channel is formed, and the n + -type third semiconductor layer 2c formed on the second semiconductor layer 2b becomes a source region. It is a type FET.

The trench gate 4 is formed via a gate insulating film 5 in a groove extending from the main surface of the semiconductor substrate to the n − type second semiconductor layer 2 a serving as a drain region. The trench gate 4 is made of, for example, polycrystalline silicon doped with impurities, and the gate insulating film 5 is made of, for example, a multilayer film in which a thermal oxide film of about 27 nm and a deposited film of about 50 nm are sequentially formed. ing.

As shown in FIGS. 19 to 21 described below,
The upper surface of trench gate 4 of the present embodiment is formed higher than the surface of third semiconductor layer 2c serving as a source region, that is, the main surface of the semiconductor substrate. With this configuration, even if the source region becomes shallow, a source offset in which the trench gate 4 deviates from the source region can be prevented.
It is desirable that the upper surface of the trench gate 4 is formed to be substantially flat or convex.

A trench gate 4 and a gate insulating film 5 are also formed on the semiconductor substrate main surface at the periphery of the trench. With this configuration, the failure of the gate insulating film 5 can be prevented.

As described above, the trench gates 4 of adjacent cells are connected to each other, and the trench gates 4 of the cells located on the outer periphery are formed in the vicinity of the outer periphery of the semiconductor chip, for example, by gate wiring using polycrystalline silicon. 6 is connected.

The gate wiring 6 is formed in an upper layer with an interlayer insulating film 7 interposed therebetween, and is electrically connected to, for example, a gate guard ring 8 (partially indicated by a broken line in FIG. 3) using aluminum containing silicon. It is connected to the. The gate guard ring 8 is formed integrally with a rectangular gate electrode 9 (partially indicated by a broken line in FIG. 3) provided in a rectangular portion of the field insulating film 3.
(Indicated by a broken line in FIG. 1) are provided.

The third semiconductor layer 2c serving as a source is formed as an upper layer on the main surface of the semiconductor substrate with an interlayer insulating film 7 interposed therebetween.
For example, a source line 10 (partially indicated by a broken line in FIG. 3) using aluminum containing silicon is electrically connected. The source wiring 10 is the source wiring 1
0 is provided with a connection region (indicated by a broken line in FIG. 1) of the third semiconductor layer 2c to be a source. This source wiring 10
Represents the p provided in the second semiconductor layer 2b in order to keep the base potential constant in addition to the third semiconductor layer 2c serving as a source.
It is also electrically connected to the + type contact layer 11.

As shown in FIG. 2, FIG. 3, or FIG. 4, a back-to-back configuration is provided between the gate and the source to prevent the gate insulating film 5 from being destroyed by a surge from the source. Of the protection diode 12 is provided. FIG. 5 is an enlarged vertical sectional view showing the protection diode 12, and the protection diode 12 is an n + type semiconductor region 12a.
And the p-type semiconductor region 12b are alternately formed in a concentric annular shape, and the gate electrode 9 and the source line 10 are electrically connected to the n + -type semiconductor regions 12a at both ends, respectively.

On the outer periphery of the field insulating film 3, an n + type semiconductor region 13a provided on the main surface of the semiconductor substrate is provided with a wiring 13 made of aluminum containing silicon, for example.
b (partially indicated by a broken line in FIG. 3), a source guard ring 13 is provided, and the wiring 13b of the source guard ring 13 is also an n + type semiconductor of the protection diode 12 similarly to the source wiring 10. It is connected to the area 12a.

The gate wiring 6 and the gate guard ring 8 are provided on the field insulating film 3 provided in a rectangular ring shape, and the gate electrode 9 and the protection diode 12 are
It is provided on a rectangular portion provided at a corner of the field insulating film 3.

A p-type well 14 is formed below the rectangular ring-shaped field insulating film 3 at a lower portion thereof.
By connecting the termination of the trench gate 4 to the p-type well 14 via the gate insulating film 5, the depletion layer can be gently extended under the field insulating film 3 and discontinuity of the depletion layer can be prevented. The p-type well 14 functions as an electric field relaxing portion for relaxing the electric field at the end of the trench gate 4.

The entire surface of the main surface of the semiconductor substrate covers the gate guard ring 8, the gate electrode 9, the source wiring 10, and the source guard ring 13. For example, a plasma C mainly composed of a tetraethoxysilane (TEOS) gas as a source gas is used.
A silicon oxide film and a protective insulating film 15 using polyimide are formed by the VD method. An opening for partially exposing the gate electrode 9 and the source wiring 10 is provided in the protective insulating film 15, and the gate electrode exposed by the opening is formed. The gate wiring 9 and the source wiring 10 form a connection region between the gate and the source, and an electrical connection is made to this connection region by wire bonding or the like.

As a drain connection region, a drain electrode 16 which is electrically connected to the n + type semiconductor substrate 1 is formed on the entire rear surface of the semiconductor substrate as a laminated film in which nickel, titanium, nickel and silver are laminated, for example. 16
Is electrically connected to the lead frame by, for example, a conductive adhesive.

Next, a method of manufacturing the above-described semiconductor device will be described with reference to FIGS. First, a semiconductor substrate 1 is epitaxially grown on an n + type semiconductor substrate 1 made of single crystal silicon into which arsenic (As) has been introduced.
An n− type epitaxial layer 2 having a lower concentration than that of the epitaxial layer 2 is formed to a thickness of about 5 μm. Next, 600 nm is applied to the main surface of the semiconductor substrate.
A silicon oxide film is formed by, for example, a thermal oxidation method, a mask is formed on the silicon oxide film by photolithography, and etching is performed using the mask to form a rectangular ring along the outer periphery of the semiconductor substrate. A plate-shaped field insulating film 3 having a rectangular portion inside is formed. Thereafter, a mask is formed along the inner periphery of the field insulating film 3 by photolithography, and ion implantation of, for example, boron (B) is performed using the mask to diffuse the introduced impurities, thereby forming an electric field relaxation portion. P-type well 14
To form This state is shown in FIG. Note that the impurity concentration of the p-type well 14 is configured to be equal to or lower than, for example, the second semiconductor layer 2b.

Next, the main surface of the semiconductor substrate is thermally oxidized to 60
A relatively thick insulating film 17 of about 0 nm is formed, and the insulating film 1 in the cell formation region surrounded by the field insulating film 3 is formed.
7, a resist mask 18 having a pattern of a trench gate having a mesh gate structure in which the gates are arranged in a lattice pattern in a plane is formed by photolithography, and etching is performed using the resist mask 18 to form a semiconductor substrate having the pattern described above. An opening for exposing the surface is provided. FIG. 7 is an enlarged view of the trench gate portion in this state.

Next, using the insulating film 17 as a mask, a groove having a depth of, for example, about 1.6 μm is formed in the main surface of the semiconductor substrate by dry etching. This state is shown in FIG.

Next, isotropic wet etching and chemical dry etching are performed on the groove formed by the dry etching to reduce the corners of the bottom edge of the groove, and at the same time, remove the side surface of the insulating film 17. Retreat from the upper end of the groove. This state is shown in FIG.

Next, a thermal oxide film of about 27 nm
A gate insulating film 5 formed by stacking a silicon oxide film by CVD (Chemical Vapor Diposition) is formed. This state is shown in FIGS.

Next, a polycrystalline silicon film 4 'serving as a conductive film of the trench gate 4 is formed on the entire main surface of the semiconductor substrate including the inside of the groove by CVD. An impurity (for example, phosphorus) for reducing the resistance value is introduced into the polycrystalline silicon film 4 'during or after the deposition. Impurity concentration and 1E18 / cm ³ to 1E21 / cm ³ order. This state is shown in FIGS.

Subsequently, the polycrystalline silicon film 4 'is removed by etching to form a trench gate 4 in the trench. By this etching process, the field insulating film 3
The gate wiring 6 connected to the trench gate 4 and the polycrystalline silicon film 9a serving as the base of the gate electrode 9 are formed on the rectangular portion. This state is shown in FIGS.

Next, the extra insulating film 17 remaining on the main surface of the semiconductor substrate is removed to expose the main surface of the semiconductor substrate. This state is shown in FIGS.

In this state, since the insulating film 17 is recessed by the above-described isotropic etching, the third insulating film serving as the source region at the periphery of the trench is formed by the gate insulating film 5 and the conductor film of the trench gate 4. It is also formed on the surface of the semiconductor layer 2c, that is, on the main surface of the semiconductor substrate. That is, the gate insulating film 5 and the conductor film of the trench gate 4 cover the periphery of the groove, and the trench gate 4 is provided with an eaves, and the eaves damage the gate insulating film 5 at the corners of the groove. Can be prevented. Further, the recess of the insulating film 17 is performed in a self-aligned manner, so that the peripheral edge of the groove can be covered with a minimum dimension.

Next, after an insulating film 12c made of silicon oxide is formed, a polycrystalline silicon film is deposited on the insulating film 12c, and p-type impurities are introduced into the polycrystalline silicon film.
On the rectangular portion of the field insulating film 3, a concentric annular pattern surrounding the polycrystalline silicon film 9a of the gate electrode 9 is formed. During this patterning, the insulating film 12c serves as the trench gate 4
And acts as an etching stopper for preventing the gate wiring 6 from being patterned. Thereafter, the n + -type semiconductor region 12a is formed by, for example, ion implantation, and the protection diode 12 in which the n + -type semiconductor region 12a and the p-type semiconductor region 12b are formed alternately and concentrically is formed. This state is shown in FIG.

Next, ion implantation of a p-type impurity (for example, boron) is performed on the entire surface of the epitaxial
About 10% in a nitrogen gas atmosphere containing 1% O ₂ at about 0 ° C
A diffusion process (first heat treatment) for about 0 minutes is performed to form a p-type second semiconductor layer 2b to be a channel formation region. Subsequently, an n-type impurity (for example, arsenic) is selectively ion-implanted, and an annealing process (second heat treatment) is performed for about 30 minutes in a nitrogen gas atmosphere containing about 1% O ₂ at about 950 ° C. Then, a third semiconductor layer 2c to be a source region is formed.

In order to function as an FET, it is important that the second semiconductor layer 2b and the third semiconductor layer 2c go under the eaves of the trench gate 4 and come into contact with the gate insulating film 5 provided in the trench. It is. According to the present invention, in order to control the channel, the first heat treatment and the second heat treatment are performed independently as described above.

Then, the deep portion of the epitaxial layer 2 into which these impurities are not introduced, specifically, the epitaxial layer 2 located between the second semiconductor layer 2b and the semiconductor substrate 1, serves as a first region functioning as a drain region. It becomes the semiconductor layer 2a. Note that the number of steps may be reduced by performing the same ion implantation process as that of the first semiconductor layer 2a on the n + type semiconductor region 12a. This state is shown in FIGS. 19 and 20.

As described above, with the upper surface of trench gate 4 positioned above the main surface of the semiconductor substrate, the second semiconductor layer 2b serving as a channel formation region and the third semiconductor layer serving as a source region are formed by ion implantation. 2c, the profile in the depth direction and the depths of the second semiconductor layer 2b and the third semiconductor layer 2c in the semiconductor substrate 2 can be accurately controlled, so that the second semiconductor layer 2b and the third semiconductor layer 2c are formed. Layer 2c
Can be made thinner. That is, since the depth of the second semiconductor layer 2b can be accurately controlled, the channel length can be accurately controlled.

Next, for example, a BPSG film is deposited to a thickness of about 500 nm on the entire surface of the main surface of the semiconductor substrate to form an interlayer insulating film 7. Next, anisotropic dry etching using CHF ₃ gas is performed to connect the third semiconductor layer 2 c serving as a source region, the gate wiring 6, the source guard ring semiconductor region 13 a, and the protection diode 12 to the interlayer insulating film 7. An opening CH (Contact Hole) for exposing the region is provided, a conductive film (metal film) made of, for example, aluminum containing silicon is formed on the entire surface of the main surface of the semiconductor substrate including the inside of the opening, and the metal film is patterned. , Gate guard ring 8,
Gate electrode 9, source wiring 10, source guard ring 1
Form 3 This state is shown in FIG.

Conventionally, as for the contact layer 11, a contact layer 11 extending from the main surface of the semiconductor substrate to the second semiconductor layer 2b is formed, and the source wiring 10 is connected to the contact layer 11 and the third semiconductor layer 2c around the contact layer. Was.
On the other hand, in the present embodiment, first, an opening CH reaching the second semiconductor layer 2b is formed by etching as shown in FIG. 22, and the second semiconductor layer 2b exposed through this opening CH is formed as shown in FIG. Is directly introduced with a p-type impurity such as boron. With this configuration, the p-type contact layer 1
1 is formed deeply, so that the avalanche resistance is improved. Since a mask for covering the contact layer 11 is not required when the source is formed, the number of photoresist steps is reduced. On the other hand, if the contact layer 11 is unnecessary in the contact portion at another opening CH due to the IC, the source wiring 10 can be easily formed by using another mask covering the contact.
Contact layer 11 only in opening CH to which is electrically connected.
Can be created.

Thereafter, as shown in FIG. 24, in the present embodiment, after the impurity is introduced from the opening CH, the silicon oxide of the interlayer insulating film 7 is selectively removed with respect to the silicon on the main surface of the semiconductor substrate. Etching is performed to expose the surface of the third semiconductor layer 2c in self-alignment with the opening CH. FIG.
As shown in FIG. 7, the contact area between the third semiconductor layer 2c and the source wiring 10 is increased by this configuration, so that the connection resistance can be reduced.

Next, for example, a plasma C using a tetraethoxysilane (TEOS) gas as a main source gas is used.
Polyimide is applied and laminated on the silicon oxide film by VD to form a protective insulating film 15 covering the entire main surface of the semiconductor substrate, and an opening for exposing the connection region of the gate electrode 9 and the source wiring 10 is formed in the protective insulating film 15. Then, the back surface of the n + type semiconductor substrate 1 is subjected to a grinding treatment, and a drain electrode 14 in which nickel, titanium, nickel, and silver are sequentially laminated is formed on the back surface by, for example, vapor deposition, and the state shown in FIG. 4 is obtained.

In this embodiment, the p-type well 14 is provided in a rectangular ring shape as the electric field relaxing portion. However, as the electric field relaxing portion, for example, an opening is provided in the field insulating film 3 and impurities are introduced from this opening. Thus, a configuration in which the p-type wells 14 are scattered annularly below the field insulating film may be adopted. In this configuration, the electric field relaxation portion can be formed after the formation of the gate wiring 6.

(Embodiment 2) FIG. 26 shows another embodiment of the present invention. In the present embodiment, unlike the above embodiment, the insulating film 17 is also formed by the step of forming the field insulating film 3. Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIG.

First, an n− type epitaxial layer 2 having a concentration lower than that of the semiconductor substrate 1 is formed to a thickness of about 5 μm on the n + type semiconductor substrate 1 made of, for example, single crystal silicon into which arsenic (As) is introduced by epitaxial growth. Next, a silicon oxide film of about 600 nm is formed on the main surface of the semiconductor substrate by, for example, a thermal oxidation method.

Next, a mask is formed on the silicon oxide film by photolithography, and by etching using this mask, a rectangular ring is formed along the outer periphery of the semiconductor substrate.
The field insulating film 3 having a rectangular portion inside the corner is formed. At the same time, a resist mask having a trench gate pattern having a mesh gate structure in which the gates are arranged in a planar lattice is formed on the insulating film in the cell formation region surrounded by the field insulating film 3 by photolithography. By etching using this resist mask,
An insulating film 17 having an opening for exposing the semiconductor substrate main surface of the pattern is formed. The subsequent steps are shown in FIGS.
5, the description is omitted.

According to the present embodiment, the number of steps can be reduced by forming the field insulating film 3 and the insulating film 17 in the same step. In this embodiment, the p-type well serving as the electric field relaxation portion is omitted. However, if necessary, for example, an opening may be provided in the field insulating film 3 so that
By introducing impurities through this opening, the electric field relaxation portion can be formed as a structure in which the p-type wells 14 are scattered annularly below the field insulating film.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. For example, the present invention provides an IGBT (Integrated Gate Bipolar Transistor) as well as a power MISFET.
r) can also be applied.

[0055]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that a source offset can be prevented by forming the upper surface of the trench gate conductor layer higher than the main surface of the semiconductor substrate.

(2) According to the present invention, the effect (1) is that the shallowing of the source can be promoted.

(3) According to the present invention, the effect (2) has an effect that the cell can be miniaturized.

(4) According to the present invention, there is an effect that a trench gate conductor layer and a gate insulating film can be formed on the semiconductor substrate main surface around the trench where the trench gate is formed.

(5) According to the present invention, the effect (4) has an effect that damage to the gate insulating film can be prevented.

(6) According to the present invention, since the channel formation region and the source region are formed by independent heat treatment control after the formation of the trench gate, there is an effect that these regions can be made shallow.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a plan view illustrating a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 4 is a partial longitudinal sectional view taken along line aa in FIG. 3;

FIG. 5 is a partial longitudinal sectional view showing a protection diode of the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 7 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 8 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 9 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 10 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 11 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 12 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 13 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 15 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 16 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 17 is a longitudinal sectional view showing a trench gate of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 18 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 19 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 20 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 21 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 22 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 23 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 24 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 25 is a longitudinal sectional view showing a trench gate of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 26 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each manufacturing process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... Epitaxial layer, 2a ... First semiconductor layer (drain region), 2b ... Second semiconductor layer (channel formation region), 2c ... Third semiconductor layer (source region), 3
... field insulating film, 4 ... trench gate, 5 ... gate insulating film, 6 ... gate wiring, 7 ... interlayer insulating film, 8 ... gate guard ring, 9 ... gate electrode, 10 ... source wiring, 1
DESCRIPTION OF SYMBOLS 1 ... Contact layer, 12 ... Protection diode, 13 ... Source guard ring, 14 ... Well, 15 ... Protective insulating film, 1
6 ... drain electrode, 17 ... insulating film, 18 ... resist mask.

Continued on the front page (72) Inventor Nobuo Machida 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division of Hitachi, Ltd. (72) Kentaro Oishi 5--22, Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 In Hitachi Cho LSI Systems

Claims (8)

[Claims] 1. A semiconductor device having an FET having a trench gate structure in which a conductor layer serving as a gate is provided in a groove extending in a main surface of a semiconductor substrate, wherein a trench gate conductor layer is provided on the main surface of the semiconductor substrate in the groove and on the periphery of the groove. A semiconductor device comprising: 2. A semiconductor device having an FET having a trench gate structure in which a conductor layer serving as a gate is provided in a groove extending in a main surface of a semiconductor substrate, wherein a gate insulating film is formed on the main surface of the semiconductor substrate in the groove and on the periphery of the groove. A semiconductor device characterized by being formed. 3. A semiconductor device having an FET having a trench gate structure in which a conductor layer serving as a gate is provided in a groove extending in a main surface of a semiconductor substrate, wherein a trench gate conductor layer is provided in the groove and on the main surface of the semiconductor substrate in the periphery of the groove. And a gate insulating film. 4. The semiconductor device according to claim 1, wherein the conductor layer serving as the gate is made of polycrystalline silicon, and the gate insulating film is made of silicon oxide formed by thermal oxidation. Semiconductor device. 5. A method of manufacturing a semiconductor device having an FET having a trench gate structure in which a semiconductor layer is used as a drain and a conductor layer serving as a gate is provided in a groove extending in the main surface of the semiconductor layer. Forming an insulating film; patterning the insulating film into a pattern corresponding to the trench gate; forming a trench in which a trench gate is to be formed on a semiconductor layer main surface using the patterned insulating film as a mask; A step of retreating a side surface of the insulating film from an upper end of the groove by isotropic etching; a step of forming a gate insulating film on the semiconductor layer main surface in the groove and on the periphery of the groove; Forming a conductor layer to be a trench gate on the semiconductor layer main surface at the periphery of the groove; and forming a channel region and a source region in contact with the gate insulating film in the groove. The method of manufacturing a semiconductor device characterized by having a degree. 6. The method according to claim 5, wherein the insulating film serving as the mask and the field insulating film are formed in the same step. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the conductor layer serving as the gate is made of polycrystalline silicon, and the gate insulating film is made of silicon oxide formed by thermal oxidation. . 8. The method according to claim 5, wherein heat treatments for forming the channel region and the source region are performed independently.