JP2012039133A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure capable of sufficiently increasing gate breakdown voltage, even in the semiconductor device in which a number of transistor cells having a trench structure are formed in a matrix shape, and gate wiring composed of a metal film is in contact with the gate electrodes of the transistors.SOLUTION: A semiconductor device comprises a cell region 10 in which transistor cells are arranged in a matrix shape. Each transistor cell has a trench structure in which recessed grooves 11 are formed in a semiconductor layer 1, a gate insulating film 4 is formed in the recessed grooves 11, and gate electrodes 5 composed of, for example, polysilicon are provided in the narrow groves 11. In order to contact a gate wiring 9 composed of a metal film, a gate pad 5a, which is successively provided with the gate electrodes 5, is formed in a recessed part 12 simultaneously provided with the recessed grooves 11.

Description

  The present invention relates to a semiconductor device having an insulated gate type power MOSFET in which gate electrodes are formed in concave grooves formed from the surface of a semiconductor layer, so-called trench structure transistor cells are arranged in a matrix, and a method for manufacturing the same. . More specifically, a MOSFET with improved breakdown voltage of the gate is formed by forming a gate pad that is in contact with the gate wiring in a recess dug from the surface of the semiconductor layer in the same manner as the recess groove in which the gate electrode is formed. The present invention relates to a semiconductor device having the same and a manufacturing method thereof.

A conventional high-power gate drive MOS transistor having a trench structure employs a structure in which a large number of transistor cells are formed in parallel in a matrix to increase the current. For example, as shown in a partial cross-sectional explanatory diagram in FIG. 8A, an n-type semiconductor layer (epitaxial growth layer) 21 serving as a drain region is epitaxially grown on an n ^{+ -type} semiconductor substrate 21a, and the semiconductor layer A concave groove is formed in a lattice shape in 21, a gate oxide film 24 is formed on the inner surface thereof, and polysilicon serving as a gate electrode 25 is embedded. Then, a p-type channel diffusion region 22 is formed in the surrounding semiconductor layer 21, and an n ^{+ -type} source region 23 is formed around the gate electrode 25 side, thereby contacting the gate oxide film 24 in the vertical direction. A channel region 22a is formed. Further, a contact hole is formed in the insulating film 26 made of SiO ₂ or the like formed on the surface, and a source wiring 27 is formed so as to make ohmic contact with the exposed source region 23 and channel diffusion region 22, and is formed on the back surface of the semiconductor substrate 21a. A drain electrode 28 is formed.

  Since the aforementioned gate electrode 25 is made of polysilicon or the like and is not formed with a low resistance completely, as shown in FIG. 8B, a plan view illustrating an example of the gate wiring 29 of the semiconductor chip is shown. A gate wiring made of a metal film made of Al or the like is connected around the region 30 or partially in the cell region 30 so that the resistance is not increased in a cell far from the wire bonding portion 29a. In order to contact the polysilicon film and a metal film made of Al or the like, the surface of the semiconductor layer is continuously formed with the gate electrode 25 as shown in FIG. A gate pad 25a is formed through a gate oxide film (not shown), and a gate wiring is formed on the gate pad 25a through an insulating film 31 (an insulating film is also formed on the left side of the figure, but is omitted in the figure). 29 is formed. As shown in FIG. 8B, there are cases where gate wirings called gate fingers 29b are provided in the cell region 30 in some places, and in this case, the structure is the same.

  The planar structure of the cell surrounded by the gate electrode in this transistor cell is formed in an arbitrary shape such as a square, a pentagon, or a hexagon. Also, these transistors are often connected to an inductive load such as a motor. In that case, when the operation is turned off, an electromotive force in the reverse direction may be applied, and the transistor is destroyed. In order to prevent this, as described above, a method of forming a protective diode in the reverse direction between the source and the drain by connecting the source electrode 27 to the channel diffusion region 22 is employed.

  As described above, in the MOSFET having the trench structure, the gate pad 25a connected to the gate wiring 29 is formed on the surface of the semiconductor layer via the gate oxide film, and thus the gate electrode 25 formed in the concave groove. The gate pad 25a formed at a higher position and continuous with the gate electrode 25 passes through the corner of the concave groove as indicated by A in FIG. 8C. The corner portion is generally thin because an oxide film is hardly formed, and there is a problem that the gate pad and the semiconductor layer are short-circuited or the gate breakdown voltage is lowered. For this reason, a process called a rounding process, that is, a process of rounding the corners is performed so that the gate oxide film is sufficiently formed at the corners, but the breakdown voltage cannot be sufficiently improved. In the process of rounding the corners, for example, a step of performing sacrificial oxidation and removing the oxide film to remove the semiconductor layer having a rough surface after etching such as RIE is performed. This is performed by forming and removing a thick oxide film at a high temperature (usually about 900 ° C.).

  Further, in this type of semiconductor device, it is important to be sufficiently protected especially against a surge or the like.

  In addition, it is possible to transmit signals to the surrounding transistor cells with a low resistance without providing a gate finger or the like, to increase the number of cells as much as possible, and to reduce the on-resistance and increase the current. It is rare.

  Further, in a semiconductor device in which a large number of transistor cells of this type are arranged in a matrix, there is a problem that the electric field tends to concentrate on the transistor cells on the outer periphery of the cell region and is easily destroyed.

  The present invention has been made to solve such a problem, and a semiconductor device in which a large number of transistor cells having a trench structure are formed in a matrix and a gate wiring made of a metal film is contacted to the gate electrode thereof. It is an object of the present invention to provide a semiconductor device having a structure capable of sufficiently increasing the gate breakdown voltage and a manufacturing method thereof.

  Another object of the present invention is to provide a semiconductor device having a structure that is difficult to break down against a surge or the like while improving the breakdown voltage with a trench structure.

  Still another object of the present invention is to provide a semiconductor device having a structure capable of uniformly transmitting signals to each cell while minimizing gate wiring.

  Still another object of the present invention is to provide a semiconductor device having a high power MOSFET capable of increasing the number of cells as much as possible and increasing the current while improving the breakdown voltage with a trench structure.

  Still another object of the present invention is to provide a semiconductor device having a structure capable of extending the depletion layer of the pn junction in the cell region to the outer periphery of the chip and improving the breakdown voltage even when the gate pad is formed in the recess. It is in.

A semiconductor device according to the present invention is a semiconductor device having a cell region in which transistor cells having a trench structure in which a gate electrode is provided in a concave groove formed in a semiconductor layer via a gate oxide film, arranged in a matrix, In order to make contact with the gate wiring made of a metal film, a gate pad portion formed continuously with the gate electrode is formed in a concave portion provided simultaneously with the concave groove, and the gate electrode in the concave groove and in the concave portion The surface of the gate pad is made lower than the surface of the semiconductor layer by etch back, and the corners of the concave groove and the concave portion are covered with an insulating film provided on the surface of the gate electrode and the gate pad,
Further, the recess in which the gate pad is formed is formed wider than the width of the recess, and the gate pad is shaped higher on the side surface side of the recess than on the bottom surface side.

  With this structure, the gate pad portion is formed at a low position in the recess (so-called sink pad), so that the gate electrode formed in the recess and the gate pad in contact with the gate wiring are continuous without a step. Even when the gate pad is formed on the surface of the semiconductor layer through a thin gate oxide film, the gate oxide film is formed with a stable film thickness with no corners, and a sufficiently high gate breakdown voltage can be obtained. Can do. As a result, a semiconductor device having a sufficiently high gate breakdown voltage can be obtained even with an insulated gate MOSFET having a trench structure.

  Each of the transistor cells having the trench structure is provided with a channel diffusion region having a conductivity type different from that of the semiconductor layer and a source region having the same conductivity type as that of the semiconductor layer in the vertical direction around the gate electrode. And a source wiring made of a metal film is directly provided on the surface of the source region, and an alloy layer is formed in which an ohmic contact is obtained when the metal of the source wiring spikes into the source region and the channel diffusion region. In the case of a transistor, the area of the source electrode contact portion can be made extremely small, the number of transistor cells per unit area can be greatly increased, the gate structure is high in the trench structure, the on-resistance is small, and the transistor is large. A current power MOSFET is obtained.

  Bidirectional protection diodes are formed by alternately providing ring-shaped p-type layers and n-type layers on the insulating film on the outer peripheral side of the cell region, and the p-type layer or the n-type layer is formed. Metal films that contact each other in a ring shape are provided on the innermost and outermost layers of each layer, and each of the metal films that contact the ring shape is formed continuously with either the source wiring or the gate wiring made of the metal film. As a result, a protection diode can be inserted between the source and drain with a small series resistance, and even if a surge or the like is applied, it can escape through the protection diode, resulting in a MOSFET with a stable trench structure.

  A gate wiring is provided in contact with the outermost layer of the protection diode, and a gate connection portion is formed so that the gate wiring is partially connected to the gate pad around the cell region across the protection diode The gate connection portion and the source connection portion that contacts the innermost layer of the source wiring are alternately formed in a plane, so that the gate wiring is not formed around the cell region. Signals can be transmitted to the gate electrode of the entire cell by the gate wiring connected to the protection diode on the outer periphery of the chip.

  A diffusion region having a conductivity type different from that of the semiconductor layer is formed on the outermost periphery of the cell region, and the source wiring contacted with the innermost layer of the protection diode is also contacted with the diffusion region, The depletion layer extends to the outside of the diffusion region, and the cell in the outermost periphery of the cell region that is easily damaged can be protected.

  A gate pad provided inside or on the outer periphery of the cell region is divided without forming the recess and the gate pad in a portion facing the channel diffusion region of the cell region adjacent to the gate pad. Therefore, even if a recess is formed for forming the gate pad and the shallow diffusion region having the same conductivity type as the channel diffusion region is crushed, for example, the channel diffusion region of the transistor cell and the lateral side of the source region are interposed via the gate electrode. Since the well region is formed up to the end side of the semiconductor chip, the depletion layer formed between the channel diffusion region and the semiconductor layer can be extended to the end side of the semiconductor chip, thereby improving the breakdown voltage. it can. On the other hand, the gate pad is formed in the concave portion continuously with the gate electrode by forming the gate electrode in a linearly extending portion, and is connected to the gate wiring contacted on the gate pad. There is no hindrance to signal transmission.

  The gate pad is recessed by forming a diffusion region deeper than the channel diffusion region of the transistor cell and having the same conductivity type as the channel diffusion region below the gate pad provided inside or on the outer periphery of the cell region. Even if formed inside, a well region is formed under the recess, and the depletion layer can be extended to the end side of the semiconductor chip.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a cell region in which transistor cells having a trench structure in which a gate electrode is provided in a concave groove formed in a semiconductor layer via a gate oxide film are arranged in a matrix. (A) forming the concave groove and a concave portion wider than the concave groove in the semiconductor layer, forming an oxide film on the surface, and (b) depositing a polysilicon film over the entire surface to form the concave layer. A semiconductor in which polysilicon is embedded in a groove and a recess, a mask is provided only on the surface of the recess, and etching back is performed. (C) The mask is removed and etching is further performed to form the recess and recess. Etchback is performed until the gate oxide film on the surface of the layer is completely exposed, whereby the gate electrode is formed in the recessed groove, the gate pad is formed in the recessed portion, and each surface is formed on the surface. A lower side than the surface of the conductor layer, and a side surface of the gate pad is formed higher than a bottom surface, and (d) the entire surface including the surface of the gate electrode and the gate pad is covered with the corners of the concave groove and the concave portion. Forming an insulating film; and (e) forming a contact hole in the surface of the semiconductor layer and the surface of the gate pad to deposit a metal film, thereby connecting the source wiring connected to the surface of the semiconductor layer, and the gate pad; A method of manufacturing a semiconductor device, comprising forming a connected gate wiring.

  According to the present invention, in the MOSFET having the trench structure, since the gate pad is also formed in the concave portion similar to the trench of the gate electrode, the connection portion between the gate electrode and the gate pad is continuous in the concave groove and the concave portion, A step rising from the concave groove to the surface of the semiconductor substrate is not formed. Therefore, the connecting portion between the gate electrode and the gate pad does not pass over the gate oxide film at the corner of the groove, and the gate breakdown voltage can be greatly improved. As a result, it is possible to overcome the weak point of the gate breakdown voltage that is fatal to the MOSFET having the trench structure.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional, perspective, and plan view showing a trench type vertical MOSFET that is an embodiment of a semiconductor device according to the present invention. FIG. 7 is an explanatory cross-sectional view showing a manufacturing step of the MOSFET shown in FIG. 1. FIG. 7 is an explanatory cross-sectional view showing another configuration example of the cell portion of the MOSFET shown in FIG. 1. FIG. 2 is a cross-sectional explanatory view showing a protection diode provided at a chip peripheral portion of the MOSFET shown in FIG. 1. FIG. 5 is an explanatory plan view showing a connection portion between the protection diode of FIG. 4 and a source wiring and a gate wiring. It is a section explanatory view showing other embodiments of the gate pad structure by the present invention. It is sectional explanatory drawing of the example which extends the depletion layer of a cell area | region to a chip | tip edge part, forming a gate pad in a recessed part. It is explanatory drawing which shows the structure of MOSFET by the conventional trench structure.

  Next, the semiconductor device of the present invention will be described with reference to the drawings. A semiconductor device according to the present invention has a groove 11 formed in a semiconductor layer 1 and a gate oxide film in the groove 11 as shown in FIG. 4 has a cell region 10 in which transistor cells having a trench structure in which a gate electrode 5 made of polysilicon or the like is provided in a concave groove 11 are arranged in a matrix. A gate pad 5a is provided continuously with the gate electrode 5 to make contact with the gate wiring 9 made of a metal film. The gate pad 5a is formed in a concave portion 12 provided simultaneously with the concave groove 11. Yes.

The semiconductor layer 1 is an n-type semiconductor layer made of silicon, for example, made of silicon and epitaxially grown to a thickness of about 10 μm on an n ^{+ -type} semiconductor substrate 1a made of silicon and having a high impurity concentration. Further, by diffusing an n-type impurity such as phosphorus, a p-type channel diffusion region 2 is formed with a thickness of about 1 μm, and a mask is formed on the surface to diffuse the n-type impurity. The n ^{+ -type} source region 3 is formed so as to be separated to a thickness of about 0.5 μm. The channel diffusion region 2 and the source region 3 can be formed by diffusion after forming a concave groove 11 and a gate electrode 5 described later.

  As shown in the perspective explanatory view before providing the source electrode in FIG. 1B, the pitch A is about 0.3 to 1.0 μm wide (E) in a lattice pattern with an interval of about 0.7 to 5 μm. Thus, a concave groove 11 is formed at a depth of about 1.5 μm, and a gate electrode 5 made of polysilicon or the like is formed in the concave groove 11 with a gate oxide film 4 interposed therebetween.

  The gate electrode 5 is formed only in the concave groove 11 by removing the polysilicon film at portions other than the concave groove 11 by etching back after polysilicon is deposited on the entire surface, for example. In the present invention, a recess 12 is formed in a portion where a gate pad 5a for connecting to a gate wiring 9 made of Al or the like is formed at the same time as a recess 11 for forming the gate electrode 5, and a polysilicon film As a result, the gate pad 5a is formed in the recess 12.

  The gate pad 5a is formed around the cell region 10 (the surface of the cell region 10 is almost covered with the source wiring 7) and, if necessary, as shown in FIG. It is formed as a gate finger in the region 10 and is formed to have a width of about 20 μm so that it can contact the gate wiring 9 made of Al or the like formed continuously with the wire bonding portion 9a. This is because the polysilicon film as the gate electrode 5 alone has a large resistance component, and the transistor cell far from the wire bonding portion 9a cannot sufficiently transmit the signal. It is because it connects directly.

  In the example shown in FIG. 1, a protection diode, which will be described later, is formed in a ring shape further on the outer peripheral side than the gate pad 5a, and the gate wiring 9 is connected to the outermost layer of the protection diode. The gate pad 5a has a structure in which the gate wiring 9 is contacted by a connecting portion 9b partially cut into the inner peripheral side. That is, since the source wiring is connected to the innermost peripheral layer of the protection diode, it is formed so as to alternately engage with the connection portion 7b of the source wiring. The meshing between the connecting portions 9b and 7b is formed over the entire circumference of the chip, but in FIG. 1 (c), only a part is shown and the rest is omitted with a one-dot chain line.

  Conventionally, the gate pad 5a is formed on the surface of the semiconductor layer via the oxide film 4a formed simultaneously with the gate oxide film 4, but as described above, the gate in the concave groove 11 adjacent to the gate pad 5a. Since the connection portion between the electrode 5 and the gate pad 5a passes through the corner portion of the concave groove 11, and the thin gate oxide film 4 is further thinned at the corner portion, there is a problem that the withstand voltage does not exist. However, in the present invention, the gate pad 5 a is formed in the recess 12 formed at the same depth as the recess 11. As a result, the connection portion between the gate electrode 5 and the gate pad 5a is connected through the concave groove and does not need to go through the corner portion of the gate groove 11, so that the gate breakdown voltage can be sufficiently improved. A method for forming the gate pad 5a will be described later. In FIG. 1C, reference numeral 7a denotes a wire bonding portion of the source wiring, and a cross section taken along the line AA is shown in FIG. 1A and a cross section taken along the line III-III is shown in FIG.

In the example shown in FIG. 1, an insulating film 6 such as SiO ₂ is provided on the surface where the gate electrode 5 and the gate pad portion 5a are formed by a CVD method or the like, and a contact hole is formed by patterning. A metal film made of Al or the like for forming the source wiring 7 is formed on the surface to a thickness of about 3 μm. The contact hole is formed in the isolation portion of the source region 2 described above, and is formed so as to make ohmic contact with both the channel diffusion region 2 and the source region 3 exposed therebetween.

Next, a method for manufacturing this MOSFET will be described with reference to FIG. First, as shown in FIG. 2A, an n-type semiconductor layer 1 is epitaxially grown on the n ^{+ -type} semiconductor substrate 1a by about 10 μm. Then, an SiO ₂ film (not shown) is formed on the surface by a CVD method or the like to a thickness of about 0.5 μm and patterned to expose the gate electrode formation site in a lattice shape and further expose the gate pad 5a formation site. Then, the concave groove 11 and the concave portion 12 having a depth of about 1.5 μm are formed by dry etching such as RIE. Thereafter, a gate oxide film 4 is formed on the inner surface of the groove 11 and an oxide film 4a is formed on the surface of the recess 12 simultaneously by performing a heat treatment at about 900 to 1000 ° C. for about 30 minutes in an atmosphere of water vapor.

  Thereafter, as shown in FIG. 2B, polysilicon is deposited on the entire surface, and the polysilicon is embedded in the recessed groove 11 and the recessed portion 12. In order to completely fill the groove 11, the polysilicon film 13 is formed by being deposited to a thickness of about twice the depth of the groove 11. Thereafter, a mask 14 made of a resist or the like is formed only on the surface in the recess 12, and the polysilicon film 13 on the surface of the semiconductor layer 1 is etched back by the RIE method by a thickness of about half. Thereafter, by removing the mask 14 and continuing the etch back, the polysilicon film 13 on the surface of the semiconductor layer 1 is completely etched, the gate oxide film 4 is exposed, and the etching stops. As a result, as shown in FIG. 2C, the polysilicon film remains only in the recessed groove 11 and the recessed portion 12, and the gate electrode 5 and the gate pad 5 a are formed in the recessed groove 11 and the recessed portion 12. . In this case, the use of an isotropic etchant can further flatten the shape.

Thereafter, as shown in FIG. 2C, p-type impurities such as boron are diffused to form a p-type channel diffusion region 2, and then a mask (not shown) is formed to remove n-type impurities such as phosphorus. An n ^{+ -type} source region 3 is formed by diffusion. Each channel diffusion region 2 is diffused so that the depth of the channel diffusion region 2 is about 0.5 to 1 μm from the surface, and the source region 3 is about 0.3 to 0.5 μm. Note that only the p-type diffusion region 2a is provided in the outermost periphery of the cell region without diffusing the n-type impurity. Then, an insulating film 6 made of SiO ₂ or the like is provided on the entire surface by CVD or the like, contact holes are formed so that the source region 3 and the gate pad 5a are exposed, and Al is formed to a thickness of about 3 μm by sputtering, for example. A source wiring 7 is formed by depositing on the entire surface. Thereafter, a metal having a thickness of about 1 μm is formed on the back surface of the semiconductor substrate 1 a by sputtering or the like to form the drain electrode 8, thereby obtaining a MOSFET having a trench structure shown in FIG.

  In the example shown in FIG. 2, the groove 11 and the recess 12 are formed to form the gate oxide film 4 and the gate electrode 5, and then diffusion for the channel diffusion region 2 and the source region 3 is performed. After the semiconductor layer 1 is epitaxially grown, the channel diffusion region 2 and the source region 3 may be formed on the entire surface, and then the groove 11 or the like may be formed to form the gate electrode 5 or the like. Further, although silicon is used as the semiconductor substrate 1a and the semiconductor layer to be grown, the use of SiC can further reduce the series resistance and the on-resistance, which is suitable for increasing the current.

  In the example shown in FIGS. 1 and 2, the source region 3 is formed separately on the surface side of the channel diffusion region 2, and the source wiring 7 is formed in ohmic contact with both the channel diffusion region 2 and the source region 3. However, for example, as shown in FIG. 3 which is a cross-sectional explanatory view similar to FIG. 1A, the source region 3 is not formed separately, but is formed on the entire surface of the channel diffusion region 2, and the source from the surface is formed. By spiking the metal of the wiring 7, the alloy layer 7 a can be formed to make ohmic contact with both the source region 3 and the channel diffusion region 2. Such a structure is preferable because the cell pitch is reduced, the number of cells can be increased, and a large current can be obtained.

The alloy layer 7a is formed by forming a metal film such as Al as the source wiring 7 described above, and then performing a heat treatment at about 400 ° C. for about 30 minutes in an N ₂ atmosphere, for example. As Si at the interface with the region 3 diffuses into Al, the alloying of Al and Si proceeds to the inside of the semiconductor layer and spikes to form a pointed tip as shown in FIG. The alloy layer 7a has a spike depth to the inside that varies depending on the temperature and time of the heat treatment, so that it enters the channel diffusion region 2 to obtain an ohmic contact, and penetrates the channel diffusion region 2 to the semiconductor layer 1. It is necessary to control the heat treatment conditions so as not to reach it.

  That is, the present inventors have made extensive studies in order to obtain a semiconductor device capable of obtaining a large current with a small chip size by reducing the on-resistance of the insulated gate semiconductor device. The amount of the metal film that enters the semiconductor layer due to the spike can be controlled by controlling the thickness of the metal film to be deposited and the conditions such as the heat treatment. As shown in FIG. It has been found that ohmic contact can be made only to the region 3 and the channel diffusion region 2, and that the channel diffusion region 2 can be prevented from penetrating, and the cell size can be made extremely small.

  The depth of the alloy layer, that is, the so-called spike depth, was deepened by increasing the temperature of the heat treatment or by increasing the time of the heat treatment, and could be controlled very accurately. For example, when an Al film is provided on Si, alloying starts at about 300 ° C., but it is most efficient to perform at about 400 ° C., and the depth of the spike can be accurately controlled. For example, by performing heat treatment at about 400 ° C. for about 30 minutes, spikes are made to a depth of about 0.6 to 0.8 μm, and the source region 3 of about 0.5 μm and the channel diffusion region 2 of about 1 μm are formed. With the diffusion depth, by performing the alloying process under these conditions, there is no possibility of penetrating the channel diffusion region 2 while taking ohmic contact in both layers. As a result, as described above, by forming a portion where the channel diffusion region 2 and the source region 3 overlap in the vertical direction, if a metal such as Al is spiked from the surface, direct ohmic contact with both layers is achieved. I was able to let

  As shown in FIGS. 1 and 3, the present invention is characterized in that the gate pad 5 a portion is formed in the recess 12. That is, since the gate electrode 5 and the gate pad 5a are continuous in the concave groove 11 and the concave portion 12, no step is formed in the middle so as to rise from the concave groove 11 to the surface of the semiconductor layer. It is formed without going through. As a result, even if the gate pad 5a is formed through a thin oxide film such as a gate oxide film, the oxide film is surely formed because it does not pass through the corner of the concave groove where the oxide film is difficult to be formed. A sufficient gate breakdown voltage can be obtained.

  In the example shown in FIG. 1 and FIG. 3, only the cell region 10 and the gate pad 5a portion are shown, but for protection against a surge or the like, protection like a bidirectional Zener diode between the gate and the source is provided. A diode is preferably inserted. This protection diode portion is shown in FIG.

The protection diode 15 is not provided on the cell region 10 (see FIG. 1C), but is formed on the outer peripheral side of the cell region 10 (region where the source wiring 9 is formed). In the example shown in FIG. 4, a field portion is provided on the entire outer periphery of the semiconductor chip so that the depletion layer in each transistor cell portion is terminated as far as possible from the cell region. For example, a polysilicon film is formed in a ring shape on an insulating film (field oxide film) 6 made of SiO ₂ or the like. FIG. 4 corresponds to the III-III cross-sectional view of FIG. In the example shown in FIG. 4, the polysilicon film is formed by forming a gate electrode 5 and a gate pad 5a, providing an insulating film 6, and then forming a polysilicon film again. 5 and the gate pad 5a may be formed at the same time. The polysilicon film is patterned, and impurities are introduced to alternately arrange n-type layers 15a and p-type layers 15b, and a plurality of pn junctions are formed in series in the lateral direction.

The aforementioned polysilicon film is formed to have a thickness of about 0.5 μm, for example, and is formed by alternately forming n-type layers 15 a and p-type layers 15 b in a ring shape with a width of about 4 μm, for example. Yes. The impurity concentrations of the n-type layer 15a and the p-type layer 15b are, for example, about 5 × 10 ²⁰ cm ⁻³ and 7 × 10 ¹⁷ cm ⁻³ , respectively, and a desired break depends on the impurity concentration and the number of pn junctions. It is set to obtain a down voltage. The protection diode 15 is formed by the n-type layer 15a and the p-type layer 15b. For example, after the p-type dopant is doped on the entire surface of the polysilicon film, the n-type dopant is formed into a ring shape by patterning, and the impurities described above are used. By doping so as to have a concentration, the n-type layer 15a and the p-type layer 15b are doped so as to be alternately repeated in a plane to form a bidirectional Zener diode.

  As described above, the breakdown voltage of the protection diode 15 can be adjusted to some extent by adjusting its impurity concentration. Usually, the impurity concentration is about 5 to 10 V with one diode. Is set. Then, for example, about 3 to 4 pn junctions are formed, and the protection diode 15 that breaks down at about 20 to 30 V is formed.

  In the example shown in FIG. 4, the gate wiring 9 is in contact with the outermost n-type layer 15d of the protection diode 15, and the source wiring 7 is in contact with the innermost layer 15c. Therefore, as mentioned in FIG. 1 above, the gate wiring 9 is located on the outer peripheral side of the gate pad 5a and contacts the gate wiring 9 and the gate pad 5a. As shown in a partial plan view illustrating the connection structure with the source wiring 7, the connection portion 7 b of the source wiring 7 to the protection diode 15 and the connection portion 9 b of the gate wiring 9 to the gate pad 5 a Are formed by alternately biting into the protective diode 15 side so that the comb teeth mesh with each other. As a result, the gate wiring 9 is also in contact with the gate pad while making contact with the outermost layer of the protective diode 15. In FIG. 5, the cross section taken along the line III-III is the cross sectional view of FIG.

  In this way, since both ends of the protective diode 15 are directly in contact with the gate wiring and source wiring made of a metal film, it can be built in with a very low series resistance, so that it can be opened immediately even if a surge or the like enters. And can sufficiently function as a protective diode. That is, when a protective diode is connected via a high concentration region of a semiconductor layer, it takes time to pass a current due to a surge because the resistance component exists even in the high concentration region, and the transistor cell is destroyed during that time. However, since the protective diode is inserted with low resistance by being directly connected by the wiring made of the metal film, the surge can be immediately released.

  As shown in FIGS. 1 and 4, as described above, no transistor cell is formed on the outermost peripheral side of the cell region 10 (on the side of the gate pad 5a provided in a ring shape on the outer peripheral portion of the chip) (n-type impurities are not formed). In this case, only the p-type diffusion region 2a, which is the same as the body region, is formed, and the source wiring 7 is brought into contact with the diffusion region 2a, whereby the curvature of the depletion layer can be increased. Since the concentration can be avoided, the breakdown voltage is further improved. That is, since the depletion layer formed between the semiconductor layer of the transistor cell extends outward from the p-type well and can extend to the end side of the semiconductor chip, the breakdown voltage can be increased.

  FIG. 6 is an example of a structure for preventing the depletion layer from spreading from the cell region due to the gate pad 5a being formed in the recess 12 as described above. That is, since the p-type channel diffusion region 2 and the p-type diffusion region 2a are formed shallower than the concave groove 11 and the concave portion 12, the concave portion 12 is formed on the outer periphery of the cell region (if there is a gate finger, the corresponding portion). If it is provided continuously, the depletion layer ends at the recess 12 and cannot be extended to the outer peripheral edge of the chip, and the withstand voltage decreases. 6 (a) is a perspective view, FIG. 6 (b) is an explanatory plan view showing the gate electrode 5 and the gate pad 5a in oblique lines, and FIG. 6 (c) is a cross-sectional view taken along the line CC of FIG. As shown in the figure, the gate pad 5a is not continuously formed on the outer periphery of the cell region 10, and the gate pad 5a is formed at the connection portion with the gate electrode 5 while the adjacent portion of the p-type diffusion region (well) 2a. The p-type diffusion region (well) 2a is formed so as to extend as it is toward the end of the chip without forming a recess.

  By forming in this way, the gate pad 5a is formed in the recess 12, and even if the p-type diffusion region 2a is shallow, the depletion layer of the pn junction continues from the cell region 10 to the portion of the gate pad 5a. The depletion layer can be extended to the field portion on the chip end side, and the breakdown voltage can be sufficiently improved. Even if the gate pad is divided in this way, the gate wiring 9 is contacted on the gate pad, and the gate wiring 9 is continuously formed around the chip, so that no problem occurs.

  FIG. 7 is a diagram showing another example of the structure for preventing the depletion layer from spreading from the cell region 10 due to the formation of the gate pad 5 a in the recess 12. That is, in this example, the gate pad 5a is continuously formed on the outer periphery of the cell region 10 (if there is a gate finger, the corresponding region inside the cell region), and the recess 12 for forming the gate pad 5a is formed. Only the portion is further subjected to p-type diffusion to form a deep diffusion region (p-type well). In order to form this deep diffusion region 2b, for example, after forming the recess 12 forming the gate pad together with the above-described recess groove by etching, the portion other than the recess 12 is covered with a mask such as a resist, and p-type impurities are formed by ion implantation. By introducing and diffusing, a deep p-type diffusion region 2b can be formed only on the lower side of the recess 12. In FIG. 7, the same parts as those in FIG.

  By doing so, the depletion layer 16 by the pn junction can extend from the cell region under the gate pad portion to the field portion at the end of the chip. Moreover, with such a structure, the gate pad around the cell region can be continuously formed without interruption, and thus the above-described protective diode can be formed on the gate pad.

  Each of the above examples is an example of a vertical MOSFET, but can be applied to all power devices having a trench structure such as an insulated gate bipolar transistor (IGBT) in which a bipolar transistor is further formed in the vertical MOSFET. .

1 semiconductor layer 2 channel diffusion region 3 source region 4 gate oxide film 5 gate electrode 5a gate pad 7 source wiring 7a alloy layer 9 gate wiring 11 concave groove 12 concave portion

Claims (8)

A semiconductor device having a cell region in which a transistor cell having a trench structure in which a gate electrode is provided in a concave groove formed in a semiconductor layer through a gate oxide film arranged in a matrix, and a gate wiring made of a metal film; In order to make contact, a gate pad portion formed continuously with the gate electrode is formed in a concave portion provided simultaneously with the concave groove, and the gate electrode in the concave groove and the surface of the gate pad in the concave portion are The corners of the grooves and the recesses are covered with an insulating film provided on the surfaces of the gate electrode and the gate pad, and lower by etchback than the surface of the semiconductor layer,
Furthermore, the concave portion in which the gate pad is formed is formed wider than the width of the concave groove, and the gate pad has a shape higher on the side surface side of the concave portion than on the bottom surface side. Each of the transistor cells having the trench structure is provided with a channel diffusion region having a conductivity type different from that of the semiconductor layer and a source region having the same conductivity type as that of the semiconductor layer in the vertical direction around the gate electrode. A source wiring made of a metal film is directly provided on the surface of the source region, and an alloy layer is formed in which an ohmic contact is obtained when the metal of the source wiring spikes into the source region and the channel diffusion region. The semiconductor device according to claim 1. Bidirectional protection diodes are formed by alternately providing ring-shaped p-type layers and n-type layers on the insulating film on the outer peripheral side of the cell region, and the p-type layer or the n-type layer is formed. Metal films that contact each other in a ring shape are provided on the innermost and outermost layers of each layer, and each of the metal films that contact the ring shape is formed continuously with either the source wiring or the gate wiring made of the metal film. The semiconductor device according to claim 1 or 2, wherein A gate wiring is provided in contact with the outermost layer of the protection diode, and a gate connection portion is formed so that the gate wiring is partially connected to the gate pad around the cell region across the protection diode 4. The semiconductor device according to claim 3, wherein the gate connection portions and the source connection portions in contact with the innermost layer of the source wiring are alternately formed in a plane. A diffusion region having a conductivity type different from that of the semiconductor layer is formed on the outermost periphery of the cell region, and the source wiring contacted with the innermost layer of the protection diode is also in contact with the diffusion region. 3. The semiconductor device according to 3 or 4. The gate pad provided inside or on the outer periphery of the cell region is divided without forming the concave portion and the gate pad in a portion facing the channel diffusion region of the cell region adjacent to the gate pad. Item 6. The semiconductor device according to any one of Items 1 to 5. 6. The diffusion region of the same conductivity type as that of the channel diffusion region, which is deeper than the channel diffusion region of the transistor cell, is formed below the gate pad provided inside or on the outer periphery of the cell region. The semiconductor device according to any one of the above. A method of manufacturing a semiconductor device having a cell region in which transistor cells having a trench structure in which a gate electrode is provided in a concave groove formed in a semiconductor layer via a gate oxide film, arranged in a matrix,
(A) forming the concave groove and a concave portion wider than the concave groove in the semiconductor layer to form an oxide film on the surface thereof;
(B) depositing a polysilicon film on the entire surface, embedding polysilicon in the concave groove and in the concave portion, providing a mask only on the surface of the concave portion, and performing etch back;
(C) Etching back until the mask is removed and etching back is further performed until the gate oxide film on the surface of the semiconductor layer in which the recess and the recess are not formed is completely exposed. Forming an electrode, a gate pad in the recess, each surface being lower than the surface of the semiconductor layer, and the side surface of the gate pad being higher than the bottom surface;
(D) forming an insulating film so as to cover the corners of the concave groove and the concave portion over the entire surface including the surfaces of the gate electrode and the gate pad;
(E) Forming contact holes on the surface of the semiconductor layer and the surface of the gate pad and depositing a metal film to form source wiring connected to the semiconductor layer surface and gate wiring connected to the gate pad A method for manufacturing a semiconductor device.

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