CN105977157A - IGBT device manufacturing method and device - Google Patents
IGBT device manufacturing method and device Download PDFInfo
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- CN105977157A CN105977157A CN201610589984.0A CN201610589984A CN105977157A CN 105977157 A CN105977157 A CN 105977157A CN 201610589984 A CN201610589984 A CN 201610589984A CN 105977157 A CN105977157 A CN 105977157A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000001259 photo etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 103
- 239000011159 matrix material Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000000407 epitaxy Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 abstract description 3
- 238000001465 metallisation Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910017109 AlON Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention relates to the technical field of a semiconductor device, and especially relates to an IGBT device manufacturing method and device. The method comprises the following steps: carrying out epitaxy on a P+ substrate through epitaxy technology to obtain a voltage withstand drift region, a P-type body area epitaxial layer and an N+ source region epitaxial layer in sequence, which form a base body; through photoetching and etching technique, providing a gate trench and a Schottky groove in the base body; carrying out thermal oxidation on the inner wall of the gate trench to form a gate oxide layer; forming a gate electrode on the inner wall of the gate oxide layer through deposition, photoetching and etching; carrying out passivation layer deposition on the outer surface of the gate electrode, and forming a gate electrode insulation protection layer through photoetching and etching; lastly, carrying out Schottky barrier metal deposition and annealing on the surface of the Schottky groove to form a Schottky diode; and finally, obtaining an IGBT device. According to the IGBT device manufacturing method and device, impurity doping and diffusion processes are saved, and reliability of the gate oxide layer is enhanced.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to the manufacture method of a kind of IGBT device
And device.
Background technology
Wide bandgap semiconductor IGBT device, especially carborundum IGBT device and gallium nitride IGBT device,
Being the device for power switching got most of the attention at present, its drive circuit is very simple, and with existing merit
The compatibility of rate component driving circuit is good.
IGBT (insulated gate bipolar transistor), is by BJT (double pole triode) and MOSFET (gold
Belong to oxide semiconductor audion) the compound full-control type voltage driven type power semiconductor that forms, hold concurrently
There is advantage of both the high input impedance of MOSFET and the low conduction voltage drop of BJT (also referred to as GTR).
Wherein longitudinal IGBT device, the p-type launch site of chip back, it is achieved mode be mainly ion implanting
Technology and epitaxy technology.
Owing to wide bandgap semiconductor IGBT device design aspect exists two technical problem underlying: one is ditch
Road electron mobility is low, and then causes the problem that the channel resistance of MOSFET is big；Two is at high temperature, height
The problem that under electric field, grid oxygen reliability is not enough；So, wide bandgap semiconductor IGBT device design aspect
Technical problem underlying is the above-mentioned technical problem that wide bandgap semiconductor MOSFET element faces.
Currently for the problem that channel electron mobility is low, settling mode mainly has two kinds:
One is to select suitable crystal orientation, because the electron mobility of different crystal orientations is different, mobility is maximum
5 times can be differed, so selecting to be formed on the crystal face of high electron mobility raceway groove；Due to carborundum
Crystal orientation is relatively random, so the bad selection of the crystal face of high electron mobility.
Two is by special annealing process, improves channel interface state, improves channel electron mobility；
This special annealing process operation inconvenience.
For the problem of trench gate oxygen reliability, settling mode mainly uses special grid oxygen material,
Such as materials such as AlN, AlON；And only can not solve trench gate oxygen well by special grid oxygen material
The problem of reliability.
It addition, the process aspect in wide bandgap semiconductor IGBT device still suffers from difficult point, this difficult point master
The form of PN junction to be, PN junction needs suitable impurity concentration and distribution, and the mode solved at present is
Use high temperature high energy ion repeatedly to inject, then carry out high annealing；Repeatedly inject high temperature high-energy from
Son can damage the lattice of semiconductor material with wide forbidden band, in addition, it is desirable to producer buys new equipment or green wood
Material, so can cause a large amount of inputs of fixed fund, and cost increases.
To sum up, for prior art, the above-mentioned of wide bandgap semiconductor IGBT device how is overcome to lack
Falling into is those skilled in the art's technical problems urgently to be resolved hurrily.
Summary of the invention
It is an object of the invention to provide manufacture method and the structure thereof of a kind of IGBT device, on solving
State problem.
In order to achieve the above object, the technical scheme is that and be achieved in that:
The invention provides the manufacture method of a kind of IGBT device, comprise the steps:
Using one piece of heavily doped p-type wide bandgap semiconductor as substrate, i.e. P+ substrate, surface thereon
Carry out N-type and be epitaxially formed pressure drift region, on the basis of described pressure drift region, then carry out P again
Type is epitaxially formed PXing Ti district epitaxial layer, finally carries out N again on the basis of described PXing Ti district epitaxial layer
Type heavy doping is epitaxially formed N+ source region epitaxial layer；By described pressure drift region, described PXing Ti district extension
Layer and described N+ source region epitaxial layer form matrix.
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the first mask layer；
And carry out photoetching, etching processing on the surface of described first mask layer, and then in described N+ source region extension
The middle position of layer forms grid region etching groove window；In the position of described grid region etching groove window,
Described matrix is performed etching, etches into the inside of described pressure drift region, form grid region groove.
At the inwall of described grid region groove, carry out thermal oxide or deposit, form gate oxide；Described
The inner side of gate oxide, then be deposited, and form gate electrode by photoetching, etching；At described grid
The surface of electrode is passivated layer deposit, forms grid electrode insulating protective layer by photoetching, etching.
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the second mask layer；
And carry out photoetching, etching processing on the surface of described second mask layer, and then in described N+ source region extension
The position, both sides of the edge of layer forms schottky trench etching window；Window is etched in described schottky trench
The position of mouth, performs etching described matrix, etches into the inside of described pressure drift region, forms Xiao
Special base groove, and the degree of depth of described schottky trench is greater than the degree of depth of described grid region groove, end form
Become groove MOSFET.
Carry out Schottky barrier metal deposit, annealing on the surface of described schottky trench, form Xiao Te
Based diode；Described groove MOSFET and described Schottky diode share metal electrode.
Preferably, as a kind of embodiment, the thickness of described PXing Ti district epitaxial layer is in 0.1 μm-1
Between μm.
Preferably, as a kind of embodiment, described P+ substrate carries out the later stage of N-type extension,
Increase doping content, form N1 dense doped epitaxial layer；In the position of described grid region etching groove window,
When described matrix is performed etching, etch into the inside of described N1 dense doped epitaxial layer, form described grid
District's groove.
Preferably, as a kind of embodiment, when forming described gate oxide, described grid are increased
The bottom thickness of oxide layer.
Accordingly, present invention also offers a kind of IGBT device, including P+ substrate, Schottky diode
And groove MOSFET；
Wherein, described P+ substrate is fixing with the bottom surface of described groove MOSFET is connected；
Described groove MOSFET includes pressure drift region, PXing Ti district epitaxial layer and N+ the most successively
All it is in close contact between source region epitaxial layer, and every adjacent two layers；In the middle of the upper end of described groove MOSFET
Position offers grid region groove；The upper end-face edge position of described groove MOSFET offers schottky trench；
The bottom surface of described grid region groove and described schottky trench is respectively positioned on the inside of described pressure drift region；Institute
State the degree of depth degree of depth more than described grid region groove of schottky trench.
Described groove MOSFET also includes gate electrode；Described gate electrode is fixedly installed on described grid region groove
In；Gate oxide is there is between described grid region groove and described gate electrode；Described gate electrode exceeds described
The periphery of the part of grid region groove is provided with grid electrode insulating protective layer；
The lower end of described Schottky diode is upper by described schottky trench and described groove MOSFET
End coordinates；Described Schottky diode shares metal electrode with the source electrode of described groove MOSFET.
Preferably, as a kind of embodiment, described Schottky diode includes that central authorities' groove is with outer
Lobe；Described schottky trench coordinates with described exterior protrusion, described central authorities groove and described grid electricity
Pole insulating protective layer coordinates.
Preferably, as a kind of embodiment, the thickness of described PXing Ti district epitaxial layer is in 0.1 μm-1
Between μm.
Preferably, as a kind of embodiment, the end face of described pressure drift region is additionally provided with N1
Dense doped epitaxial layer；Described N1 dense doped epitaxial floor is positioned at described pressure drift region and described PXing Ti district
Between epitaxial layer.
Preferably, as a kind of embodiment, the bottom surface of described grid region groove is positioned at that described N1 is dense to be mixed
In miscellaneous epitaxial layer.
Preferably, as a kind of embodiment, the bottom thickness of described gate oxide is more than described grid
The lateral thickness of oxide layer.
Compared with prior art, this have the advantage that:
The manufacture method of a kind of IGBT device that the present invention provides and structure thereof, use wide bandgap semiconductor
(preferably manufacturing silicon carbide semiconductor or gallium nitride semiconductor) as material, by heavily doped p-type broad stopband
Semi-conducting material is as substrate；Epitaxy technology is utilized to carry out N-type extension, P successively from the upper surface of substrate
Type extension and N-type heavy doping extension, from bottom to top sequentially form pressure drift region, PXing Ti district epitaxial layer
With N+ source region epitaxial layer, this makes the doped region of wide bandgap semiconductor IGBT device, all at epitaxial wafer
Carry out during extension, overcome the impurity doping of semiconductor material with wide forbidden band, difficult the asking of diffusion
Topic；Meanwhile, this manufacture method can be enterprising at the production line of existing silicon materials power IGBT device
Row produces, and is not required to buy new equipment, thus has saved the biggest cost.
In carrying out the etching process of grid region groove and schottky trench, at the matrix that needs perform etching
Surface deposition etching groove shelters film, ensures when performing etching matrix as far as possible, do not damage matrix its
The integrity degree in his place；Photoetching, lithographic technique is used to sequentially form grid region groove and Schottky ditch afterwards
Groove；Wherein, the bottom position of grid region groove will be in pressure drift region, so, and guarantee raceway groove
Architecture quality and energising quality.
After grid region groove is formed, within it on wall, carry out thermal oxide or deposit, form gate oxide；It
After, it is deposited in the inner side of gate oxide, and carries out photoetching, etching in the structure that deposit is formed
Form gate electrode；Then, it is passivated layer deposit on the surface of gate electrode, and passivation layer is carried out light
Carve, etching formed grid electrode insulating protective layer, grid electrode insulating protective layer by gate electrode at grid region groove
The part on top is surrounded completely so that gate electrode insulate with external structure, obtains final groove
MOSFET.In schottky trench, finally carry out Schottky barrier metal deposit and annealing, form Xiao Te
Based diode, Schottky diode forms one to the subregion being enclosed in internal pressure drift region
Individual blind zone.
It will be apparent that the degree of depth of schottky trench is more than the degree of depth of grid region groove so that partly lead in broad stopband
The when of body IGBT device carrying voltage, schottky junction forms electric field shielding to the bottom of grid region groove,
And then reduce the electric field of grid region channel bottom gate oxide, improve the reliability of gate oxide.
It addition, Schottky diode and the source electrode metal electrode to be shared of groove MOSFET.
Accompanying drawing explanation
In order to be illustrated more clearly that the specific embodiment of the invention or technical scheme of the prior art, under
The accompanying drawing used required in detailed description of the invention or description of the prior art will be briefly described by face,
It should be evident that the accompanying drawing in describing below is some embodiments of the present invention, general for this area
From the point of view of logical technical staff, on the premise of not paying creative work, it is also possible to obtain according to these accompanying drawings
Obtain other accompanying drawing.
The IGBT that in the manufacture method of the IGBT device that Fig. 1 provides for the embodiment of the present invention, step one is formed
The sectional structure schematic diagram of device；
The IGBT that in the manufacture method of the IGBT device that Fig. 2 provides for the embodiment of the present invention, step 2 is formed
The sectional structure schematic diagram of device；
The IGBT that in the manufacture method of the IGBT device that Fig. 3 provides for the embodiment of the present invention, step 3 is formed
The sectional structure schematic diagram of device；
The IGBT that in the manufacture method of the IGBT device that Fig. 4 provides for the embodiment of the present invention, step 4 is formed
The sectional structure schematic diagram of device；
The IGBT that in the manufacture method of the IGBT device that Fig. 5 provides for the embodiment of the present invention, step 5 is formed
The sectional structure schematic diagram of device；
The manufacture method of the IGBT device that Fig. 6 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging layer, the sectional structure schematic diagram of the IGBT device that step one is formed；
The manufacture method of the IGBT device that Fig. 7 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging layer, the sectional structure schematic diagram of the IGBT device that step 2 is formed；
The manufacture method of the IGBT device that Fig. 8 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging layer, the sectional structure schematic diagram of the IGBT device that step 3 is formed；
The manufacture method of the IGBT device that Fig. 9 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging layer, the sectional structure schematic diagram of the IGBT device that step 4 is formed；
The manufacture method of the IGBT device that Figure 10 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging layer, the sectional structure schematic diagram of the IGBT device that step 5 is formed；
The manufacture method of the IGBT device that Figure 11 provides for the embodiment of the present invention increases in step 3
In the case of the bottom thickness of gate oxide, the sectional structure schematic diagram of the IGBT device of formation；
The manufacture method of the IGBT device that Figure 12 provides for the embodiment of the present invention increases gate oxide
In the case of bottom thickness, the sectional structure schematic diagram of the IGBT device that step 4 is formed；
The manufacture method of the IGBT device that Figure 13 provides for the embodiment of the present invention increases gate oxide
In the case of bottom thickness, the sectional structure schematic diagram of the IGBT device that step 5 is formed；
The manufacture method of the IGBT device that Figure 14 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging layer, in step 3, increase again the IGBT device of the bottom thickness formation of gate oxide
Sectional structure schematic diagram；
The manufacture method of the IGBT device that Figure 15 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging the bottom thickness of layer and increase gate oxide, the section view of the IGBT device that step 4 is formed
Structural representation；
The manufacture method of the IGBT device that Figure 16 provides for the embodiment of the present invention increases outside the dense doping of N1
In the case of prolonging the bottom thickness of layer and increase gate oxide, the section view of the IGBT device that step 5 is formed
Structural representation.
Description of reference numerals:
Schottky diode 1；Groove MOSFET 2；P+ substrate 3；
Exterior protrusion 11；
Grid electrode insulating protective layer 21；Pressure drift region 22；PXing Ti district epitaxial layer 23；
N+ source region epitaxial layer 24；Grid region groove 25；Schottky trench 26；
Gate electrode 27；Gate oxide 28；
N1 dense doped epitaxial layer 221；Blind zone 222.
Detailed description of the invention
Below in conjunction with accompanying drawing, technical scheme is clearly and completely described, it is clear that
Described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on this
Embodiment in bright, those of ordinary skill in the art are obtained under not making creative work premise
Every other embodiment, broadly fall into the scope of protection of the invention.
In describing the invention, it should be noted that term " " center ", " on ", D score, " left ",
Orientation or the position relationship of the instruction such as " right ", " interior ", " outward " are based on orientation shown in the drawings or position
Put relation, be for only for ease of the description present invention and simplify description rather than instruction or imply indication
Device or element must have specific orientation, with specific azimuth configuration and operation, therefore can not manage
Solve as limitation of the present invention.Additionally, term " first ", " second " are only used for describing purpose, and
It is not intended that instruction or hint relative importance.
In describing the invention, it should be noted that unless otherwise clearly defined and limited, art
Language " is connected ", " connection " should be interpreted broadly, and connects for example, it may be fixing, it is also possible to be can
Dismounting connects, or is integrally connected；Can be to be mechanically connected, it is also possible to be electrical connection；Can be straight
Connect connected, it is also possible to be indirectly connected to by intermediary, can be the connection of two element internals.Right
For those of ordinary skill in the art, above-mentioned term can be understood in the present invention with concrete condition
Concrete meaning.
Below by specific embodiment and combine accompanying drawing the present invention is described in further detail.
See Fig. 1-Fig. 5, embodiments provide the manufacture method of a kind of IGBT device, including
Following steps；
Step one, by one block of heavily doped p-type wide bandgap semiconductor (preferably manufacturing silicon carbide semiconductor or nitrogen
Change gallium quasiconductor) material is as substrate, and surface carries out N-type and is epitaxially formed pressure drift region 22 thereon,
Then on the basis of pressure drift region 22, carry out p-type be again epitaxially formed PXing Ti district epitaxial layer 23,
Carry out N-type heavy doping on the basis of HouPXing Ti district epitaxial layer 23 again and be epitaxially formed N+ source region epitaxial layer
24, pressure drift region 22, PXing Ti district epitaxial layer 23 and N+ source region epitaxial layer 24 form matrix (tool
Body sees Fig. 1).
Step 2, the upper surface at N+ source region epitaxial layer 24 deposits etching groove and shelters film, forms first
Mask layer (not shown)；And photoetching, etching processing is carried out on the surface of the first mask layer, and then
Middle position at N+ source region epitaxial layer 24 forms grid region etching groove window (not shown)；
In the position of grid region etching groove window, matrix is performed etching, etch into pressure drift region 22
Inside, formed grid region groove 25 (referring specifically to Fig. 2).
Step 3, at the inwall of grid region groove 25, carries out thermal oxide or deposit, forms gate oxide 28；
In the inner side of gate oxide 28, then it is deposited, and forms gate electrode 27 by photoetching, etching；
It is passivated layer deposit on the surface of gate electrode 27, forms grid electrode insulating by photoetching, etching
Protective layer 21 (referring specifically to Fig. 3).
Step 4, the upper surface at N+ source region epitaxial layer 24 deposits etching groove and shelters film, forms second
Mask layer (not shown)；And photoetching, etching processing is carried out on the surface of the second mask layer, and then
Form schottky trench etching window (figure not to show in the position, both sides of the edge of N+ source region epitaxial layer 24
Go out)；
In the position of schottky trench etching window, matrix is performed etching, etch into pressure drift region
The inside of 22, forms schottky trench 26, and the degree of depth of schottky trench 26 is greater than grid region groove
The degree of depth of 25；Ultimately form groove MOSFET 2 (referring specifically to Fig. 4).
Step 5, carries out Schottky barrier metal deposit, annealing, shape on the surface of schottky trench 26
Become Schottky diode 1；Groove MOSFET 2 shares metal electrode with Schottky diode 1 (specifically joins
See Fig. 5).
In the manufacture method of above-mentioned IGBT device, (preferably carborundum is partly led to use wide bandgap semiconductor
Body or gallium nitride semiconductor) as material, using heavily doped p-type semiconductor material with wide forbidden band as lining
The end；Epitaxy technology is utilized to carry out N-type extension, p-type extension and N-type successively from the upper surface of substrate heavily doped
Miscellaneous extension, from bottom to top sequentially forms outside pressure drift region 22, PXing Ti district epitaxial layer 23 and N+ source region
Prolonging layer 24, this makes the doped region of wide bandgap semiconductor IGBT device, all in the mistake of extension sheet epitaxy
Journey is carried out, overcomes the impurity doping of semiconductor material with wide forbidden band, the problem of diffusion difficulty；Meanwhile,
This manufacture method can produce, no on the production line of existing silicon materials power IGBT device
New equipment need to be bought, thus saved the biggest cost.
In the etching process carrying out grid region groove 25 and schottky trench 26, perform etching at needs
Matrix surface deposit etching groove shelter film, ensure, when matrix is performed etching, not damage as far as possible
Matrix integrity degree elsewhere；Photoetching, lithographic technique is used to sequentially form grid region groove 25 and afterwards
Schottky trench 26；Wherein, the bottom position of grid region groove 25 will be in pressure drift region 22, this
Sample, the architecture quality of guarantee raceway groove and energising quality.
After grid region groove 25 is formed, within it on wall, carry out thermal oxide or deposit, form gate oxide
28；Afterwards, it is deposited in the inner side of gate oxide 28, and carries out light in the structure that deposit is formed
Carve, etching forms gate electrode 27；Then, it is passivated layer deposit on the surface of gate electrode 27, and right
Passivation layer carries out photoetching, etching forms grid electrode insulating protective layer 21, and grid electrode insulating protective layer 21 will
The gate electrode 27 part on the top of grid region groove 25 is surrounded completely so that gate electrode 27 and outside knot
Structure insulate, and obtains final groove MOSFET 2.Finally in schottky trench 26, carry out Schottky gesture
Building Metal deposition and annealing, form Schottky diode 1, Schottky diode 1 is to surrounding therein
Pressure drift region 22 subregion formed a blind zone 222.
It will be apparent that the degree of depth of schottky trench 26 is more than the degree of depth of grid region groove 25 so that prohibit at width
The when of band quasiconductor IGBT device carrying voltage, the bottom of grid region groove 25 is formed by schottky junction
Electric field shielding, and then reduce the electric field of the gate oxide 28 of the bottom of grid region groove 25, improve
The reliability of gate oxide 28.
It addition, Schottky diode 1 and the source electrode metal electrode to be shared of groove MOSFET 2.
It should be noted that P+ i.e. represents heavily doped P-type semiconductor.
Especially, in order to increase the mobility of the channel electrons of wide bandgap semiconductor IGBT device further,
Reducing channel resistance, during extension, the PXing Ti district epitaxial layer 23 of groove MOSFET 2 uses super
Thin p-type extension, thickness is between 0.1 μm-1 μm, and on the premise of there is not tunnel breakdown,
It is thin that PXing Ti district epitaxial layer 23 should be tried one's best, so that the channel length of MOSFET is the shortest, and Jin Erda
To the purpose reducing channel resistance.
In order to further enhance the practicality of the manufacture method of the IGBT device that the embodiment of the present invention provides,
Following three kinds of improved procedures can also be carried out.
See Fig. 6, Fig. 7, Fig. 8, Fig. 9 or Figure 10, increase the feelings of N1 dense doped epitaxial layer 221
Condition:
In view of the Schottky diode 1 blind zone 222 to groove MOSFET 2, there is conducting resistance
Loss, so, time delay outside, for reducing loss, it is preferred that increases the epitaxial layer in this region
Doping content, is i.e. carried out the later stage of N-type extension on P+ substrate 3, increases doping content, forms N1
Dense doped epitaxial layer 221, reduces the resistance of blind zone 222.
For adapting to above-mentioned preferred version, the bottom surface of grid region groove 25 should be positioned at N1 dense doped epitaxial layer 221
In, this just requires, when etching grid region groove 25, to get hold of the bottom position of grid region groove 25,
The inside of N1 to be etched into dense doped epitaxial layer 221.
See Figure 11, Figure 12 or Figure 13, the situation of the bottom thickness of increase gate oxide 28:
In view of increasing the bottom voltage endurance capability of grid region groove 25 in groove MOSFET 2 so that broad stopband
The performance of quasiconductor IGBT device increases, so, when forming gate oxide 28, it is preferable that
Increase the bottom thickness of gate oxide 28.
See Figure 14, Figure 15 or Figure 16, increase N1 dense doped epitaxial layer 221 and increase gate oxide
The assembled scheme of the bottom thickness of 28, both can reduce the resistance of blind zone 222, can improve again broad stopband
The performance of quasiconductor IGBT device.
Accordingly, present invention also offers a kind of IGBT device, see Fig. 1-Fig. 5, it is according to upper
State the manufacture method manufacture of IGBT device, including P+ substrate 3, Schottky diode 1 and groove
MOSFET2。
Wherein, groove MOSFET 2 includes pressure drift region 22, PXing Ti district extension the most successively
All it is in close contact between layer 23 and N+ source region epitaxial layer 24, and every adjacent two layers；Groove MOSFET 2
Centre position, upper end offer grid region groove 25；The upper end-face edge position of groove MOSFET 2 offers
Schottky trench 26；The bottom surface of grid region groove 25 and schottky trench 26 is respectively positioned on pressure drift region 22
Inside；The degree of depth of schottky trench 26 is more than the degree of depth of grid region groove 25.
Groove MOSFET 2 also includes gate electrode 27；Gate electrode 27 is fixedly installed in grid region groove 25；
Gate oxide 28 is there is between grid region groove 25 and gate electrode 27；Gate electrode 27 exceeds grid region groove
The periphery of the part of 25 is provided with grid electrode insulating protective layer 21.
The lower end of Schottky diode 1 is coordinated with the upper end of groove MOSFET 2 by schottky trench 26；
Schottky diode 1 shares metal electrode with the source electrode of groove MOSFET 2.
It should be noted that the IGBT device that the present invention provides, it is not necessary to use special grid oxygen material just
Overcome the problem that raceway groove reliability of the gate oxide is not enough so that the system of wide bandgap semiconductor IGBT device
Make technique more convenient, save cost.
In the concrete structure of the IGBT device of present invention offer, Schottky diode 1 includes Rolandic fissure
Groove and exterior protrusion 11；Exterior protrusion 11 is used for joining with the schottky trench 26 on groove MOSFET 2
Closing, central authorities' groove is used for coordinating with the grid electrode insulating protective layer 21 of groove MOSFET 2 upper end.
Especially, the thickness of PXing Ti district epitaxial layer 23 should be arranged between 0.1 μm-1 μm, to increase
Channel electron mobility in big wide bandgap semiconductor IGBT device, reduces channel resistance.
According to three kinds of improved procedures of the manufacture method of above-mentioned IGBT device, following three kinds of structures can be formed:
See Fig. 6-Figure 10, the situation of increase N1 dense doped epitaxial layer 221:
On device architecture, N1 dense doped epitaxial layer 221 is arranged on the end face of pressure drift region 22,
I.e. N1 dense doped epitaxial floor 221 is between the district's epitaxial layer 23 of pressure drift region 22 and PXing Ti；Separately
Outward, N1 dense doped epitaxial layer 221 is positioned at blind zone 222, and the bottom surface of grid region groove 25 is positioned at N1
In dense doped epitaxial layer 221, to arrive purpose as above.
See Figure 11-Figure 13, the situation of the bottom thickness of increase gate oxide 28:
On device architecture, the bottom thickness of gate oxide 28 is greater than its lateral thickness, and then makes
The performance of wide bandgap semiconductor IGBT device increases.
See Figure 14-Figure 16, increase N1 dense doped epitaxial layer 221 and the end increasing gate oxide 28
The assembled scheme of portion's thickness, both can reduce the resistance of blind zone 222, can improve again wide bandgap semiconductor
The performance of IGBT device.
Concrete, schottky trench 26 is annular structural part, and utilizes this structure by groove MOSFET 2
Top half be surrounded, and in pressure drift region 22 formed blind zone 222.
Especially, the P+ substrate 3 structure to being disposed thereon, serve supporting role, so P+ lining
The thickness at the end can not be the thinnest, be otherwise susceptible to deformation, thickness can be arranged on 5 μm-500 μm it
Between.
It addition, N+ source region epitaxial layer should be the thinnest, thickness should be less than 1 μm；Optimum, thickness
Elect 0.5 μm as.
In sum, the embodiment of the present invention provides the manufacture method of IGBT device and device thereof, it is possible to
The impurity overcoming semiconductor material with wide forbidden band adulterates, spreads difficult problem, and can be in existing silicon merit
Produce on rate IGBT production line, meanwhile, it is capable to reduce channel resistance, strengthen gate oxide can
By property；The performance making wide bandgap semiconductor IGBT device is improved, and manufacturing cost is minimized.
So, the manufacture method of the IGBT device that the embodiment of the present invention provides and device thereof, will bring good
Market prospect.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than
It is limited；Although the present invention being described in detail with reference to foregoing embodiments, this area
Those of ordinary skill is it is understood that the technical scheme described in foregoing embodiments still can be entered by it
Row amendment, or the most some or all of technical characteristic is carried out equivalent；And these amendment or
Person replaces, and does not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. the manufacture method of an IGBT device, it is characterised in that comprise the steps:
Using one piece of heavily doped p-type semiconductor material with wide forbidden band as substrate, i.e. P+ substrate, thereon
Surface carries out N-type and is epitaxially formed pressure drift region, then enters on the basis of described pressure drift region again
Row p-type is epitaxially formed PXing Ti district epitaxial layer, finally epitaxial layer on the basis of described PXing Ti district again
Carry out N-type heavy doping and be epitaxially formed N+ source region epitaxial layer；By described pressure drift region, described p-type body
District's epitaxial layer and described N+ source region epitaxial layer form matrix；
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the first mask layer；
And carry out photoetching, etching processing on the surface of described first mask layer, and then in described N+ source region extension
The middle position of layer forms grid region etching groove window；
In the position of described grid region etching groove window, described matrix is performed etching, etch into described
The inside of pressure drift region, forms grid region groove；
At the inwall of described grid region groove, carry out thermal oxide or deposit, form gate oxide；
In the inner side of described gate oxide, then it is deposited, and forms gate electrode by photoetching, etching；
Be passivated on the surface of described gate electrode layer deposit, by photoetching, etching formed gate electrode exhausted
Edge protective layer；
Upper surface at described N+ source region epitaxial layer deposits etching groove and shelters film, forms the second mask layer；
And carry out photoetching, etching processing on the surface of described second mask layer, and then in described N+ source region extension
The position, both sides of the edge of layer forms schottky trench etching window；
In the position of described schottky trench etching window, described matrix is performed etching, etch into institute
State the inside of pressure drift region, form schottky trench, and the degree of depth of described schottky trench is greater than
The degree of depth of described grid region groove, ultimately forms groove MOSFET；
Carry out Schottky barrier metal deposit, annealing on the surface of described schottky trench, form Xiao Te
Based diode；Described groove MOSFET and described Schottky diode share metal electrode.
2. the manufacture method of IGBT device as claimed in claim 1, it is characterised in that
The thickness of described PXing Ti district epitaxial layer is between 0.1 μm-1 μm.
3. the manufacture method of IGBT device as claimed in claim 2, it is characterised in that
Described P+ substrate is carried out the later stage of N-type extension, increase doping content, form that N1 is dense mixes
Miscellaneous epitaxial layer；In the position of described grid region etching groove window, when described matrix is performed etching, carve
Erosion, to the inside of described N1 dense doped epitaxial layer, forms described grid region groove.
4. the manufacture method of the IGBT device as described in any one of claim 1-3, it is characterised in that
When forming described gate oxide, increase the bottom thickness of described gate oxide.
5. an IGBT device, it is characterised in that include P+ substrate, Schottky diode and groove
MOSFET；
Wherein, described P+ substrate is fixing with the bottom surface of described groove MOSFET is connected；
Described groove MOSFET includes pressure drift region, PXing Ti district epitaxial layer and N+ the most successively
All it is in close contact between source region epitaxial layer, and every adjacent two layers；In the middle of the upper end of described groove MOSFET
Position offers grid region groove；The upper end-face edge position of described groove MOSFET offers schottky trench；
The bottom surface of described grid region groove and described schottky trench is respectively positioned on the inside of described pressure drift region；Institute
State the degree of depth degree of depth more than described grid region groove of schottky trench；
Described groove MOSFET also includes gate electrode；Described gate electrode is fixedly installed on described grid region groove
In；Gate oxide is there is between described grid region groove and described gate electrode；Described gate electrode exceeds described
The periphery of the part of grid region groove is provided with grid electrode insulating protective layer；
The lower end of described Schottky diode is by described schottky trench and described groove MOSFET
Upper end coordinates；
Described Schottky diode shares metal electrode with the source electrode of described groove MOSFET.
6. IGBT device as claimed in claim 5, it is characterised in that
Described Schottky diode includes central authorities' groove and exterior protrusion；Described schottky trench is with described
Exterior protrusion coordinates, and described central authorities groove coordinates with described grid electrode insulating protective layer.
7. IGBT device as claimed in claim 5, it is characterised in that
The thickness of described PXing Ti district epitaxial layer is between 0.1 μm-1 μm.
8. IGBT device as claimed in claim 7, it is characterised in that
N1 dense doped epitaxial layer it is additionally provided with on the end face of described pressure drift region；The dense doping of described N1
Epitaxial layer is between described pressure drift region and described PXing Ti district epitaxial layer.
9. IGBT device as claimed in claim 8, it is characterised in that
The bottom surface of described grid region groove is positioned in described N1 dense doped epitaxial layer.
10. the IGBT device as described in any one of claim 5-9, it is characterised in that
The bottom thickness of described gate oxide is more than the lateral thickness of described gate oxide.
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