CN104347403B - A kind of manufacture method of insulated gate bipolar transistor - Google Patents
A kind of manufacture method of insulated gate bipolar transistor Download PDFInfo
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- CN104347403B CN104347403B CN201310329221.9A CN201310329221A CN104347403B CN 104347403 B CN104347403 B CN 104347403B CN 201310329221 A CN201310329221 A CN 201310329221A CN 104347403 B CN104347403 B CN 104347403B
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- 239000012535 impurity Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000003786 synthesis reaction Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 6
- 150000002500 ions Chemical group 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
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- 238000000137 annealing Methods 0.000 description 6
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a kind of manufacture method of insulated gate bipolar transistor, including, there is provided the Semiconductor substrate of the first conduction type, the Semiconductor substrate have the first interarea and the second interarea；The ion implanting of active area photoetching and the first conduction type is carried out in the Semiconductor substrate of the first conduction type；The base of the second conduction type is formed in the interarea of active area first of the Semiconductor substrate of the first conduction type and the protection terminal of the second conduction type is formed on the outside of the interarea of active area first；Residue the first interarea structure of insulated gate bipolar transistor is formed in base of first interarea based on formation of the Semiconductor substrate；The second interarea structure of insulated gate bipolar transistor is formed in the second interarea side of the Semiconductor substrate.The invention provides one kind to reduce reticle usage quantity, and technological process is simple, the IGBT preparation methods that manufacturing cost reduces and application reliability is high.
Description
Technical field
The invention belongs to power semiconductor device technology field, is related to insulated gate bipolar transistor (IGBT), especially
Simplify the preparation method of the insulated gate bipolar transistor of technique.
Background technology
IGBT is by GTR (Giant Transistor, power transistor or huge transistor) and MOSFET (Metal-
Oxide-Semiconductor-Field-Effect-Transistor, mos field effect transistor) composition
Compound full-control type voltage driven type power semiconductor, have MOSFET high input impedance and GTR low conduction voltage drop concurrently
Both sides advantage, there is the features such as working frequency is high, and control circuit is simple, and current density is high, and on-state is forced down, be widely used in
Power Control field.
IGBT can be divided into plane IGBT and groove-shaped IGBT, the architectural feature of the two according to the structure type of grid
And its individual features are known to those skilled in the art knows.But both IGBT are during preparation, including positive work
Skill and back process, wherein, positive technique is mainly used to complete IGBT grid (Gate, G) and emitter stage (Emitter, E)
Prepare, back process is mainly used to complete the preparation of IGBT colelctor electrode (Collector, C).
Normally, existing plane IGBT mainly prepares to be formed by following two methods.
The first is to complete positive technique on a monocrystaline silicon substrate, then substrate back is thinned, the more secondary ions in the back side are noted
Enter and form colelctor electrode to draw；This method is to rely on energetic ion injection and annealed and swash independent of epitaxy technique
Technical process living, the equipment cost height of energetic ion injection, technical process cost of implementation are also higher；Also, ion implanting is simultaneously
The activity ratio of the doped source for the collector area that annealing is formed is not high, and then causes IGBT saturated characteristic bad.
Second is the thicker epitaxial layer of transoid epitaxial growth, and being completed just on the epitaxial layer on a monocrystaline silicon substrate
Face technique, then silicon substrate is thinned at its back side and forms colelctor electrode；This method uses epitaxy technique and with epitaxial layer
IGBT (more than cushion being formed by epitaxial layer) mainly is prepared, epitaxial layer is thicker and to the performance requirement of epitaxial layer
Very high (such as defect counts), usually cause IGBT degradations (for example, overvoltage is held because the quality of epitaxial layer is not good enough
It is poor by ability and overcurrent ability to bear) or yield rate it is low.
As the world is to the demand of energy-saving and emission-reduction, for IGBT using more and more extensive, IGBT is used for a variety of circuits, is not difficult to send out
Existing, existing process flow is that terminal structure has independent reticle, and complex process, manufacturing cost is higher, therefore, it is necessary to provide one
Improved technical scheme is planted to overcome above mentioned problem.
The content of the invention
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduce some preferably to implement
Example.It may do a little simplified or be omitted to avoid making our department in this part and the description of the present application summary and denomination of invention
Point, the purpose of specification digest and denomination of invention obscure, and this simplification or omit and cannot be used for limiting the scope of the present invention.
In view of problem present in above-mentioned and/or existing IGBT manufacture method, it is proposed that the present invention.
It is therefore an object of the present invention to it is that terminal structure has independent reticle, complex process, system for existing procedure technique
Cause this higher, there is provided one kind reduces reticle usage quantity, and technological process is simple, and manufacturing cost reduces and application reliability is high
IGBT preparation methods.
In order to solve the above technical problems, the invention provides following technical scheme：A kind of insulated gate bipolar transistor
Manufacture method, including, there is provided the Semiconductor substrate of the first conduction type, the Semiconductor substrate have the first interarea and the second master
Face；The ion implanting of active area photoetching and the first conduction type is carried out in the Semiconductor substrate of the first conduction type；First
The interarea of active area first of the Semiconductor substrate of conduction type forms the base of the second conduction type and led in active area first
The protection terminal of the second conduction type is formed on the outside of face；Formed absolutely in base of first interarea based on formation of the Semiconductor substrate
Residue the first interarea structure of edge grid bipolar transistor；Insulated gate bipolar is formed in the second interarea side of the Semiconductor substrate
Second interarea structure of transistor.
As a kind of preferred scheme of the manufacture method of insulated gate bipolar transistor of the present invention, wherein：Form institute
Stating the process of protection terminal and the base includes：Field oxygen is generated on the first interarea of the Semiconductor substrate of the first conduction type
Change layer；Protection terminal and base photoetching, etching, the second conductive type ion inject, push away trap to form the protection terminal and institute
State base；Gate oxide is grown on the first interarea of active area.
As a kind of preferred scheme of the manufacture method of insulated gate bipolar transistor of the present invention, wherein：It is described
The second interarea structure that second interarea side of the Semiconductor substrate forms insulated gate bipolar transistor includes：Pass through thinning back side
Technique, the thick bottom of the Semiconductor substrate of the first conduction type is thinned from the second interarea；The of Semiconductor substrate after being thinned
Two interareas play the second semiconductor layer that the second conduction type is internally formed towards Semiconductor substrate；The second of the second conduction type
Metal level is formed on semiconductor layer to form the second main electrode.
As a kind of preferred scheme of the manufacture method of insulated gate bipolar transistor of the present invention, wherein：First leads
Electric type is N-type, and the second conduction type is p-type.
As a kind of preferred scheme of the manufacture method of insulated gate bipolar transistor of the present invention, wherein：At this partly
Residue the first interarea structure that base of first interarea of conductor substrate based on formation forms insulated gate bipolar transistor includes：
The surface of the base along the second conduction type of selectivity forms the first conductive-type into the Semiconductor substrate of the first conduction type
Type emitter region；Deposit forms dielectric layer；Contact hole is etched in the dielectric layer；Using deposit metal and flatening process deposit one
Layer surface metal level is to form the first main electrode.
As a kind of preferred scheme of the manufacture method of insulated gate bipolar transistor of the present invention, wherein：It is described
IGBT Facad structure also includes：It is formed at the passivation layer on the outside of the first main electrode described in the first interarea.
As a kind of preferred scheme of the manufacture method of insulated gate bipolar transistor of the present invention, wherein：Described
Two conductive type ions inject, and the energy of ion implanting is 20KeV~1MeV, dosage 1E11/cm2~1E14/cm2。
The invention provides a kind of manufacture method of insulated gate bipolar transistor, POLY photoetching in this method IGBT structure
And P-Body regions and Ring region etch, p type impurity injection, push away trap and form body traps and Ring areas p-well in same step
Middle completion, reduce the use number of plies of reticle.The present invention is that terminal structure has independent reticle, work for existing procedure technique
The problems such as skill is complicated, and manufacturing cost is higher, there is provided one kind reduces reticle usage quantity, and technological process is simple, manufacturing cost drop
Low and high application reliability IGBT preparation methods.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these accompanying drawings other
Accompanying drawing.Wherein：
Fig. 1~Figure 11 is the method flow schematic diagram that IGBT is made according to first embodiment of the invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
It is different from other manner described here using other to implement, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when the embodiment of the present invention is described in detail, for purposes of illustration only, table
Show that the profile of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
First embodiment of the invention is related to a kind of method for making IGBT device, specifically using silicon chip as Semiconductor substrate
Flow is as shown in Fig. 1~Figure 11.
It should be noted that the Semiconductor substrate in the present embodiment can include semiconductor element, for example, monocrystalline, polycrystalline or
The silicon or SiGe (SiGe) of non crystalline structure, can also include mixing semiconductor structure, such as carborundum, indium antimonide, lead telluride,
Indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination；Can also be silicon-on-insulator (SOI).In addition,
Semiconductor substrate can also include other materials, such as the sandwich construction of epitaxial layer or buried layer.Can although there is described herein
To form several examples of the material of Semiconductor substrate, but the present invention can be each fallen within as any material of Semiconductor substrate
Spirit and scope.
As shown in figure 1, the first step, there is provided the Semiconductor substrate of the first conduction type, the Semiconductor substrate have the first master
Face and the second interarea.In the present embodiment, specifically, the preferred silicon chip of N-type substrate 101, N- doping concentrations and thickness according to
Required IGBT characteristics selection, such as breakdown voltage are higher, and N- doping concentration requires lower, and thickness requirement is thicker, and
Thickness is formed on first interarea isOxide layer 102.
Second step, as shown in Fig. 2 the Semiconductor substrate in the first conduction type carries out active area photoetching and the first conduction
The ion implanting of type.Specifically, the first interarea in the N-type substrate 101 etches active area 100 by photoetching process
Oxide layer 102, and the oxidation layer pattern of terminal area 200, JFET injections are carried out afterwards, N-type impurity injection is carried out, in this implementation
In example, the energy of ion implanting is 20KeV~1MeV, and dosage is, for example, 1E11/cm2~1E14/cm2, form JFET regions.
3rd step, one layer of gate oxide 401 is formed by thermal oxide growth technique on the interarea of active area 100 first, such as
Shown in Fig. 3 and Fig. 4, one layer of polysilicon layer 402 is deposited on gate oxide 401 to manufacture polysilicon gate.
Referring to Fig. 3, gate oxide 401 is formed on the interarea of active area 100 first, the gate oxide 401 in the present embodiment
Including at least silica, forming the mode of gate oxide 401 can be, once property grows grid on the interarea of active area 100 first
Oxide layer 401, in the present embodiment, gate oxide is formed using relative to the thermal oxidation method of conventional high temperature process lower temperature
401, specifically, the dry oxygen 5min first at 800 DEG C~850 DEG C, oxidated layer thickness as needed afterwards carries out H2-O2Synthesis
Oxidation, then in 800 DEG C~850 DEG C dry-oxygen oxidation 3min~5min, the finally N at 1000 DEG C~1250 DEG C2Annealed in atmosphere
10min~1000min；So it is because lasting high-temperature oxidation process can greatly increase SiO in grid2Layer interface charge with
And the lattice defect density of silicon, cause high device leakage current, the reliability and Radiation hardness for making device decline, and low temperature
Thermal oxide can then suppress the growth of the defects of stacking fault and the fractional condensation of channel region impurity, and high annealing can reduce SiO2Layer is consolidated
Determine electric charge, improve quality of oxide layer, forming thickness isGate oxide 401.
As shown in figure 4, the depositing polysilicon layer 402 on gate oxide 401, in the present embodiment, forming thickness isPolysilicon layer 402, wherein polysilicon layer 402 can use chemical vapor deposition, physical vapor deposition
Or other means formed, the present embodiment is not specifically limited.
4th step, the base of the second conduction type is formed in the interarea of active area first of the Semiconductor substrate of the first conduction type
Area and the terminal protection area 200 that the second conduction type is formed on the outside of the interarea of active area first.As shown in figure 5, specifically,
The active area 100 of first interarea of the N-type substrate 101 etches gate oxide 401 and polysilicon layer 402 by photoetching process,
The photoresist layer with grid region pattern is formed in the gate polysilicon layer surface using photoetching process, afterwards with grid region pattern
Photoresist layer be mask, polysilicon gate 502 (referring to Fig. 5) and the He of the first p-well region 301 are formed by the way of dry etching
The figure of second p-well region 302, at the same the interarea of photoetching first on the outside of formed the second conduction type terminal protection area 200, using from
The mode of son injection forms the ion implanted layer of the first p-well region 301, the ion implanted layer of the second p-well region 302, and terminal p-well
Area 201, the ion implanted layer and p-well region 201 of ion implanted layer, the second p-well region 302 to the first p-well region 301 push away
Enter and activate the p type impurity of injection, form the first p-well region 301, the second p-well region 302 and terminal p-well region 201.In the present embodiment
In, the energy of ion implanting is 20KeV~1MeV, and dosage is, for example, 1E12/cm2~1E16/cm2, then 1100 DEG C~1250
Trap 20min~1000min is pushed away under conditions of DEG C.
5th step, as shown in fig. 6, selectivity along the second conduction type base (herein for the first p-well region 301 and
Second p-well region 302) surface formed and first lead into the Semiconductor substrate (being herein N-type substrate 101) of the first conduction type
The active area of electric type (being herein N-type).Specifically, by photoetching process in the p-well region of the first p-well region 301 and second
302 surface selection N+ injection windows, using ion implanting and annealing process the down either side of polysilicon gate 502 the first P
N-type heavy doping the first source region 602 and the second source region 601 are formed respectively in the p-well region 302 of well region 301 and second.In the present embodiment
In, the energy of ion implanting is 20KeV~1MeV, and dosage is, for example, 1E15/cm2~1E16/cm2；The annealing process, it is moved back
Fiery temperature is 800 DEG C~1000 DEG C, and the time is 10min~1000min, forms N-type heavy doping the first source region 602 and the second source region
601。
6th step, referring to Fig. 7, in the present embodiment, medium deposited in the 5th step formed dielectric layer 701 surround it is more
The side of polysilicon gate 502 (referring to Fig. 7) and top surface, etch contact hole in dielectric layer 701, then carry out the N-type impurity in hole
Inject twice, the energy of first time ion implanting is 20KeV~90KeV, and dosage is, for example, 1E12/cm2~1E16/cm2；Second
The energy of secondary ion injection is 20KeV~1MeV, and dosage is, for example, 1E13/cm2~1E16/cm2.Certainly, it is possible to use the N in hole
Type impurity once injects.
7th step, using deposit metal, in silicon chip surface deposit layer of surface metal level (Al/AlCu/AlSiCu/
AlSi), in the present embodiment, the metal layer thickness is about 2um~6um, then carries out photoetching and etching to metal level, forms metal
Wiring layer 801, form the first main electrode (being herein emitter stage).These steps all after the completion of silicon chip section it is as shown in Figure 8.
Referring to Fig. 9, the 8th step, formed sediment on the first main electrode (being herein emitter stage) metal wiring layer 801 and oxide layer 102
Product passivation layer 901.Specifically, by way of chemical vapor deposition, in the first main electrode (being herein emitter stage) and oxide layer
The passivation layer 901 for protecting chip surface not by extraneous ion contamination is deposited on 102, and passes through photoetching, etching technics, etching
Go out PAD (pad) region (not shown) for drawing gate electrode and emitter stage.
9th step, by technique for thinning back side, by the Semiconductor substrate (being herein N-type substrate 101) of the first conduction type
Thick bottom be thinned.Specifically, grinding the Semiconductor substrate from the second interarea of N-type substrate 101, defined thickness is complied with
Degree requires, and removes back side silicon stressor layers using wet method.
Tenth step, as shown in Figure 10, referring to Fig. 3, the second of the terminal protection area 200 of the N-type substrate 101 after being thinned
The second semiconductor layer that interarea is internally formed the second conduction type towards N-type substrate 101 (is herein P+ collector layers
1101) towards the of the conduction type of formation second of selectivity inside Semiconductor substrate, and from the second interarea of active area 100
Two semiconductor layers (being herein P+ collector layers 1101).Specifically, in the second interarea from the N-type Semiconductor substrate 1 after grinding
By the implanting p-type impurity of photoetching process selectivity, P+ collector layers 1101 and activation of annealing are formed.In the present embodiment, from
The energy of son injection is 20KeV~80KeV, and dosage is, for example, 1E12/cm2~1E16/cm2；During annealing, temperature be 300 DEG C~
550 DEG C, duration 10min~500min.
Finally, back metal deposits, and (is herein P+ collection in the second semiconductor layer of the second conduction type as shown in figure 11
Electrode layer 1101) on form metal level 1201 to form the second main electrode.
It is seen that in the present embodiment, POLY photoetching and P-Body regions and Ring regions are carved in IGBT structure
Erosion, p type impurity injection, pushes away trap formation body traps and Ring areas p-well is completed in same step, and reduce reticle uses layer
Number.
It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention and it is unrestricted, although with reference to preferable
The present invention is described in detail embodiment, it will be understood by those within the art that, can be to the technology of the present invention
Scheme is modified or equivalent substitution, and without departing from the spirit and scope of technical solution of the present invention, it all should cover in this hair
Among bright right.
Claims (5)
- A kind of 1. manufacture method of insulated gate bipolar transistor, it is characterised in that：Including,The Semiconductor substrate of the first conduction type is provided, the Semiconductor substrate has the first interarea and the second interarea, in the first master Oxide layer is formed on face, the first conduction type is N-type；In the oxide layer and terminal that the first interarea of the Semiconductor substrate of the first conduction type passes through photoetching process etching active area The oxide layer in region, the ion implanting of the first conduction type is carried out afterwards；Generate gate oxide on the first interarea of the Semiconductor substrate of the first conduction type, specifically, first 800 DEG C~ Dry oxygen 5min at 850 DEG C, oxidated layer thickness as needed afterwards carry out H2-O2Synthesis oxidation, then in 800 DEG C~850 DEG C dry oxygen 3min~5min is aoxidized, finally the N at 1000 DEG C~1250 DEG C2Anneal 10min~1000min in atmosphere, and forming thickness isGate oxide；One layer of polysilicon layer is deposited on gate oxide to manufacture polysilicon gate；Gate oxide and polysilicon layer are etched by photoetching process in the first interarea of the Semiconductor substrate, afterwards using p-type The mode of ion implanting forms the ion implanted layer of the first p-well region, the ion implanted layer of the second p-well region, and terminal p-well region, The ion implanted layer and terminal p-well region of ion implanted layer, the second p-well region to the first p-well region are promoted and activate injection P type impurity, form the first p-well region, the second p-well region and terminal p-well region, the first p-well region and the second p-well region are base；The residue first that insulated gate bipolar transistor is formed in base of first interarea based on formation of the Semiconductor substrate is led Face structure；The second interarea structure of insulated gate bipolar transistor is formed in the second interarea side of the Semiconductor substrate.
- 2. the manufacture method of insulated gate bipolar transistor according to claim 1, it is characterised in that：The second interarea structure that insulated gate bipolar transistor is formed in the second interarea side of the Semiconductor substrate includes：By technique for thinning back side, the thick bottom of the Semiconductor substrate of the first conduction type is thinned from the second interarea；The second of the second conduction type is internally formed towards Semiconductor substrate from the second interarea of the Semiconductor substrate after being thinned Semiconductor layer；Metal level is formed on the second semiconductor layer of the second conduction type to form the second main electrode, the second conduction type is P Type.
- 3. the manufacture method of insulated gate bipolar transistor according to claim 1, it is characterised in that：The residue first that insulated gate bipolar transistor is formed in base of first interarea based on formation of the Semiconductor substrate is led Face structure includes：The surface of the base along the second conduction type of selectivity forms first into the Semiconductor substrate of the first conduction type and led Electric type emitter region；Deposit forms dielectric layer；Contact hole is etched in the dielectric layer；Deposit metal and flatening process is used to deposit layer of surface metal level to form the first main electrode, the second conduction type is P-type.
- 4. the manufacture method of insulated gate bipolar transistor according to claim 3, it is characterised in that：The insulated gate is double The Facad structure of polar transistor also includes：It is formed at the passivation layer on the outside of the first main electrode described in the first interarea.
- 5. the manufacture method of insulated gate bipolar transistor according to claim 1, it is characterised in that：The p-type from During son injection, the energy of ion implanting is 20KeV~1MeV, and dosage is 1E11/cm2~1E14/cm2.
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| US5945692A (en) * | 1994-05-31 | 1999-08-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating same |
| CN1264164A (en) * | 1998-12-23 | 2000-08-23 | 因芬尼昂技术北美公司 | Method for formation grid oxide of metal oxide semiconductor |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
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| US20040061170A1 (en) * | 1995-07-31 | 2004-04-01 | Ixys Corporation | Reverse blocking IGBT |
| US7019358B2 (en) * | 2003-07-31 | 2006-03-28 | Clare, Inc. | High voltage semiconductor device having an increased breakdown voltage relative to its on-resistance |
| JP2009194330A (en) * | 2008-02-18 | 2009-08-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP4635067B2 (en) * | 2008-03-24 | 2011-02-16 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP2010109031A (en) * | 2008-10-29 | 2010-05-13 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
| CN103050523B (en) * | 2012-12-14 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Insulated gate bipolar transistor and manufacture method thereof |
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| US5945692A (en) * | 1994-05-31 | 1999-08-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating same |
| CN1264164A (en) * | 1998-12-23 | 2000-08-23 | 因芬尼昂技术北美公司 | Method for formation grid oxide of metal oxide semiconductor |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
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