JP2009194330A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a sufficient reverse bias safe action region. <P>SOLUTION: An n-substrate 11 has a first main face having an outer circumferential face P1oand an inner circumferential face P1i surrounded by the outer circumferential face P1o, and a second main face opposed to the first main face. An insulation gate type field transistor part FT is provided on the inner circumferential face P1i of the n-substrate 11. An n+ layer 15 is provided on the part opposed to the circumferential face P1oof the second main face, and has an impurity concentration higher than that of the n-substrate 11. An n++ buffer layer 20 of which at least a part is located on the part opposed to the circumferential face P1oof the second main face, and has an impurity concentration higher than that of the n+ layer 15. A p+ layer 16 is provided on the n+ layer 15 and the n++ buffer layer 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an insulated gate field transistor portion and a collector layer and a manufacturing method thereof.

  Power semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor) are widely used from consumer equipment to electric railway applications. Normally, when the loss reduction of the IGBT is advanced, the tolerance expressed by using the safe operating area (SOA) as an index is lowered. As the SOA, for example, there is a reverse bias safe operation region: RBSOA (Reverse Bias SOA). RBSOA is an SOA when a reverse bias is applied to the IGBT, and serves as an index of resistance at turn-off. In recent years, a structure for suppressing the decrease in resistance has been proposed.

For example, according to Japanese Patent Laid-Open No. 2005-136092, an IGBT includes an n − type semiconductor layer, an n + type semiconductor layer, a p type semiconductor layer, an emitter region, a gate electrode, a guard ring portion, a collector layer, have. The collector layer has a lower impurity concentration than the other regions immediately below the region where the guard ring portion is provided. It is described that this improves the latch-up resistance, which is a weak point of the IGBT.
Japanese Patent Laying-Open No. 2005-136092 (FIG. 1)

  When the IGBT is turned off, holes injected from the collector layer immediately below the guard ring portion are intensively absorbed into the p-type semiconductor layer on the outermost periphery of the cell portion. Since this amount of absorption exceeds a certain value, the IGBT may be thermally destroyed, so that there is a problem that the RBSOA of the IGBT cannot be sufficiently secured.

  Therefore, an object of the present invention is to provide a semiconductor device having sufficient RBSOA and a manufacturing method thereof.

  A semiconductor device of the present invention is a semiconductor device including an insulated gate field effect transistor portion having a gate electrode and a collector layer, the first conductivity type semiconductor substrate, an insulated gate field effect transistor portion, A first conductivity type buffer layer; a first conductivity type high concentration buffer layer; and a second conductivity type collector layer different from the first conductivity type. The semiconductor substrate has a first main surface having an outer peripheral surface and an inner peripheral surface surrounded by the outer peripheral surface, and a second main surface facing the first main surface. The insulated gate field effect transistor portion is provided on the inner peripheral surface of the semiconductor substrate. The buffer layer is provided on a portion facing the inner peripheral surface of the second main surface, and has a higher impurity concentration than the semiconductor substrate. The high-concentration buffer layer is at least partially located on the portion facing the outer peripheral surface of the second main surface, and has a higher impurity concentration than the buffer layer. The collector layer is provided on the buffer layer and the high concentration buffer layer.

  A manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device including an insulated gate field effect transistor portion having a gate electrode and a collector layer, and includes the following steps.

  An insulated gate field effect transistor portion is formed on the inner peripheral surface surrounded by the outer peripheral surface in the first main surface of the first conductivity type semiconductor substrate. A first conductivity type buffer layer is formed on a portion of the second main surface facing the inner peripheral surface. A phosphorous glass layer is formed on the film formation surface including at least a part of the portion facing the outer peripheral surface of the second main surface. By heating the phosphorous glass layer, a high-concentration buffer layer of the first conductivity type is located at least partially on the portion facing the outer peripheral surface of the second main surface and has an impurity concentration higher than that of the buffer layer. It is formed. A collector layer of a second conductivity type different from the first conductivity type is formed on the buffer layer and the high concentration buffer layer.

  According to the present invention, the high-concentration buffer layer eliminates most of the holes injected from the collector layer above the portion facing the outer peripheral surface of the second main surface, so that sufficient RBSOA of the semiconductor device is ensured. can do.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a top view schematically showing a configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1 is a cross-sectional view taken along the line II of FIG.

  1 to 3, the semiconductor device of the present embodiment is an IGBT (semiconductor device) having a cell region CL and a guard ring region GR provided so as to surround the cell region CL. More specifically, the IGBT includes an n− substrate 11 (semiconductor substrate), an n + layer 15 (buffer layer), an n ++ buffer layer 20 (high concentration buffer layer), a p + layer 16 (collector layer), and a back surface. The electrode 17, the base 31 (p well layer), the emitter 32e, the emitter 12e, the gate insulating film 41g, the gate electrode 51, the oxide film 42, the interlayer film 43, the guard ring 61, , N + portion 32, electrode 12, insulating film 41, and overcoat film 63.

The n-substrate 11 is a substrate having an n-type (first conductivity type) conductivity type, for example, an FZ wafer. The n-substrate 11 has an outer peripheral surface P1o and an inner peripheral surface P1i surrounded by the outer peripheral surface P1o as the upper surface (first main surface). The n-substrate 11 has an inner peripheral facing surface P2i facing the inner peripheral surface P1i and an outer peripheral facing surface P2o facing the outer peripheral surface P1o as the back surface (second main surface) facing the upper surface. Yes. A portion sandwiched between the inner peripheral surface P1i and the inner peripheral facing surface P2i of the n − substrate 11 is included in the cell region CL. Further, the portion sandwiched between the outer peripheral surface P1o and the outer peripheral facing surface P2o of the n-substrate 11 is included in the guard ring region GR. The n − substrate 11 has a lifetime killer layer 11k on the inner peripheral facing surface P2i and the outer peripheral facing surface P2o side. The lifetime killer layer 11k is formed by, for example, irradiating hydrogen ions (H ⁺ ) at an irradiation dose of 1 × 10 ¹⁰ / cm ² .

  On the inner peripheral surface P1i of the n− substrate 11, an insulated gate field transistor portion FT having the n− substrate 11, a base portion 31, an emitter portion 32e, a gate insulating film 41g, and a gate electrode 51 is formed. Is formed. The base portion 31 has a high concentration base portion 31d on the emitter electrode 12e side.

The n + layer 15 is an n-type layer provided on the inner peripheral facing surface P <b> 2 i and having an impurity concentration higher than that of the n− substrate 11. The impurity of the n + layer 15 is, for example, phosphorus (P) implanted at an implantation amount of 1 × 10 ¹¹ / cm ² .

The n ++ buffer layer 20 is an n-type layer that is at least partially located on the outer peripheral facing surface P <b> 2 o and has a higher impurity concentration than the n + layer 15. The impurity of the n ++ buffer layer 20 is, for example, phosphorus (P) implanted with an implantation amount of 5 × 10 ¹³ / cm ² .

The p + layer 16 is a p-type layer provided on the n + layer 15 and the n ++ buffer layer 20. The impurity of the p + layer 16 is, for example, boron (B) implanted at an implantation amount of 5 × 10 ¹² / cm ² .

  The gate pad 22 (pad layer) is provided on the inner peripheral surface P1i and electrically connects the outside of the IGBT and the gate electrode 51. The n ++ buffer layer 20 has a portion facing the gate pad 22 with the n− substrate 11 interposed therebetween.

Next, the switching operation of the IGBT of this embodiment will be described.
First, the turn-on operation of the switching operation will be described. By applying a predetermined voltage to the gate electrode 51, electrons are injected from the insulated gate field transistor portion FT into the n − substrate 11. Further, by applying a predetermined voltage between the back electrode 17 and the emitter electrode 12e, the forward bias is applied between the p + layer 16 and the emitter portion 32e. Due to this forward bias state, holes are injected from the p + layer 16 into the n− substrate 11. In the cell region CL, the electrons and holes are in an equilibrium state, and conductivity modulation occurs. On the other hand, in the guard ring region GR, an n ++ buffer layer 20 that is an n-type high concentration impurity region is formed between the p + layer 16 and the n− substrate 11. For this reason, most of the holes from the p + layer 16 disappear.

  Next, the turn-off operation of the switching operation will be described. By switching the IGBT from the forward bias state to the reverse bias state, the injection of electrons is stopped. In the cell region CL, the holes remaining in the vicinity of the n + layer 15 of the n− substrate 11 are trapped in the lifetime killer layer 11k, and the holes remaining in the intermediate portion in the thickness direction of the n− substrate 11 disappear due to the self lifetime. The holes remaining on the inner peripheral surface P1i side of the n − substrate 11 pass to the emitter portion 32e side. On the other hand, in the guard ring region GR, most of the holes are eliminated by the n ++ buffer layer 20 as described above. A small amount of remaining holes flow into the base 31 on the outermost periphery of the cell region CL.

Next, a method for forming the n ++ layer 15 and the n ++ buffer layer 20 will be described. First, phosphorus (P) is injected into the entire surface on the inner peripheral facing surface P2i and outer peripheral facing surface P2o side of the n-substrate 11 at an injection amount of 1 × 10 ¹¹ / cm ² . Thereafter, phosphorus (P) is selectively implanted into the outer peripheral facing surface P2o at an injection amount of 5 × 10 ¹³ / cm ² , so that the impurity concentration of the outer peripheral facing surface P2o is 5 × 10 ¹³ / cm ² . The concentration is defined by This selective impurity implantation is performed by applying a double-side aligner and performing patterning using a back mask.

  Next, a semiconductor device of a comparative example will be described. FIG. 4 is a partial cross-sectional view schematically showing a configuration of a semiconductor device in a comparative example. Referring to FIG. 4, in the IGBT of the comparative example, n + layer 15 is formed on inner peripheral facing surface P2i and outer peripheral facing surface P2o, and n ++ buffer layer 20 is not formed. For this reason, more holes than in the present embodiment are injected into the n− substrate 11 in the guard ring region GR at the time of turn-on. The holes are concentrated on the base portion 31 at the outermost periphery of the cell region CL at the time of turn-off. Since this concentration tends to be excessive because there are many holes as described above, the IGBT is likely to be thermally destroyed.

  On the other hand, according to the present embodiment, only a small amount of holes from the p + layer 16 are injected into the n− substrate 11 due to the influence of the n ++ buffer layer 20 in the guard ring region GR. Therefore, the amount of holes flowing into the outermost base portion 31 of the cell region CL during turn-off is reduced. For this reason, since thermal destruction due to the concentration of holes is suppressed, sufficient RBSOA can be secured.

  As shown in FIG. 3, the n ++ buffer layer 20 has a portion facing the region where the gate pad 22, which is an invalid region, is formed, similarly to the guard ring region GR. As a result, the amount of holes injected into the n-substrate 11 is suppressed, so that a wider RBSOA can be secured based on the same principle as described above.

(Embodiment 2)
FIG. 5 is a partial cross-sectional view schematically showing a configuration of the semiconductor device according to the second embodiment of the present invention.

Referring to FIG. 5, the IGBT as the semiconductor device of the present embodiment has an n ++ buffer layer 21 instead of the n ++ buffer layer 20 of the IGBT of the first embodiment (FIG. 1). Similar to the n ++ buffer layer 20, the n ++ buffer layer 21 is an n-type layer having an impurity concentration higher than that of the n + layer 15. The n ++ buffer layer 21 has, for example, phosphorus (P) added at a concentration of 2 × 10 ¹⁶ / cm ³ as an impurity. The impurity concentration on the p ++ layer 16 side surface of the n ++ buffer layer 21 is 1 × 10 ¹⁹ / cm ³ or more. The n + layer 15 has, for example, phosphorus (P) with a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ as an impurity.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

Next, the manufacturing method of IGBT of this Embodiment is demonstrated.
Referring to FIG. 5, insulated gate field transistor portion FT is formed on inner peripheral surface P <b> 1 i of n− substrate 11. By injecting phosphorus (P) at a low concentration into the entire inner peripheral facing surface P2i and outer peripheral facing surface P2o, the n + layer 15 is formed.

  Next, the n-substrate 11 is covered with a thick oxide film. Of this oxide film, a surface including at least a part of the outer peripheral facing surface P2o is selectively exposed to be a coated surface. This selective exposure is possible by applying a double-side aligner and patterning the back surface. Next, a phosphorus (P) film forming process is performed.

  FIG. 6 is a schematic partial cross-sectional view for explaining one step of the method of manufacturing a semiconductor device in the second embodiment of the present invention. FIG. 7 is a temperature profile diagram for explaining one step of the method of manufacturing a semiconductor device in the second embodiment of the present invention.

Referring to FIGS. 6 and 7, first, in step S01, n-substrate 11 is carried into a manufacturing apparatus in which a mixed gas of nitrogen and oxygen is ejected. In step S02, the temperature T is raised to a value suitable for forming a phosphorus glass layer. In step S03, PH ₃ gas is jetted into the manufacturing apparatus. Thereby, the phosphorous glass layer 2u is formed on the film formation surface described above, that is, the surface including at least a part of the outer peripheral facing surface P2o. In step S04, the temperature T is lowered, and a flash process is performed in step S05.

  In step S06, the temperature T is raised to a value suitable for the drive process. Thereby, the phosphorus glass layer 2u is heated. By performing the drive process in step S07, the n ++ buffer layer 21 is formed on at least a part of the outer peripheral facing surface P2o. Thereafter, the phosphorus glass layer 2u and the oxide film are removed. A p + layer 16 is formed on the n + layer 15 and the n ++ buffer layer 21. Gate pad 22 is provided on inner peripheral surface P1i such that n ++ buffer layer 21 has a portion facing gate pad 22 with n-substrate 11 interposed therebetween. Thereby, the IGBT shown in FIG. 5 is obtained.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, as shown by the arrows in FIG. 6, the gettering effect of the impurity IP by the phosphorus glass layer 2u can be obtained, so that the leakage current of the IGBT can be suppressed.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be particularly advantageously applied to a semiconductor device having an insulated gate field transistor portion and a collector layer and a method for manufacturing the same.

1 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. 1 is a top view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic sectional drawing along the III-III line of FIG. It is a fragmentary sectional view which shows roughly the structure of the semiconductor device in a comparative example. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is a schematic fragmentary sectional view for demonstrating 1 process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a temperature profile figure for demonstrating 1 process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention.

Explanation of symbols

  CL cell region, FT insulated gate field transistor portion, GR guard ring region, 2u phosphor glass layer, 11 n− substrate, 12e emitter electrode, 15 n + layer, 16 p + layer, 17 back electrode, 20, 21 n ++ buffer layer, 22 gate pad, 41 g gate insulating film, 51 gate electrode, 61 guard ring part.

Claims (4)

A semiconductor device including an insulated gate field effect transistor portion having a gate electrode and a collector layer,
A first conductive type semiconductor substrate having a first main surface having an outer peripheral surface and an inner peripheral surface surrounded by the outer peripheral surface; and a second main surface opposite to the first main surface;
The insulated gate field effect transistor portion provided on the inner peripheral surface of the semiconductor substrate;
A buffer layer of the first conductivity type provided on a portion of the second main surface facing the inner peripheral surface and having an impurity concentration higher than that of the semiconductor substrate;
A high-concentration buffer layer of the first conductivity type that is at least partially located on a portion of the second main surface facing the outer peripheral surface and has an impurity concentration higher than that of the buffer layer;
A semiconductor device comprising: a collector layer of a second conductivity type different from the first conductivity type provided on the buffer layer and the high concentration buffer layer. A pad layer for electrically connecting the outside of the semiconductor device and the gate electrode provided on the first main surface;
The semiconductor device according to claim 1, wherein the high-concentration buffer layer has a portion facing the pad layer across the semiconductor substrate. A method of manufacturing a semiconductor device including an insulated gate field effect transistor portion having a gate electrode and a collector layer,
Forming the insulated gate field effect transistor portion on the inner peripheral surface surrounded by the outer peripheral surface in the first main surface of the first conductivity type semiconductor substrate;
Forming a buffer layer of the first conductivity type on a portion of the second main surface facing the inner peripheral surface;
Forming a phosphorous glass layer on a film formation surface including at least a part of a portion of the second main surface facing the outer peripheral surface;
By heating the phosphorous glass layer, at least part of the second main surface is located on a portion facing the outer peripheral surface and has a higher impurity concentration than the buffer layer. Forming a high concentration buffer layer;
Forming a collector layer of a second conductivity type different from the first conductivity type on the buffer layer and the high-concentration buffer layer. Forming a pad layer for electrically connecting the outside of the semiconductor device and the gate electrode on the first main surface;
The method for manufacturing a semiconductor device according to claim 3, wherein the film formation surface has a portion facing the pad layer with the semiconductor substrate interposed therebetween.

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