JPH0252468A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0252468A JPH0252468A JP63204397A JP20439788A JPH0252468A JP H0252468 A JPH0252468 A JP H0252468A JP 63204397 A JP63204397 A JP 63204397A JP 20439788 A JP20439788 A JP 20439788A JP H0252468 A JPH0252468 A JP H0252468A
- Authority
- JP
- Japan
- Prior art keywords
- source electrode
- current detection
- electrode material
- electrodes
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001514 detection method Methods 0.000 abstract description 38
- 239000007772 electrode material Substances 0.000 abstract description 22
- 238000009792 diffusion process Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000011521 glass Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野）
この発明は半導体基板上に複数の電極を有する半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a plurality of electrodes on a semiconductor substrate.
第３図は従来の複数の電極を有りる半導体装置の一例と
して、電流検出用ソース電極を右する半導体装置を示す
平面図である。同図に４３いて、１８は出力用ソース電
極の外部接続用ポンディングパッド部、２８は電流検出
用ソース電極の外部接続用ポンディングパッド部、３ａ
はゲート電極の外部接続用ポンディングパッド部、４は
ガラスコート、５は絶縁膜、７はゲート電極接続用アル
ミ配線層である。上記した外部接続用ポンディングパッ
ド部１８．２８．３ａ上で直接ワイヤボンディングが行
われる。FIG. 3 is a plan view showing a semiconductor device including a current detection source electrode as an example of a conventional semiconductor device having a plurality of electrodes. 43 in the figure, 18 is a bonding pad portion for external connection of the output source electrode, 28 is a bonding pad portion for external connection of the current detection source electrode, 3a
Reference numeral 4 indicates a bonding pad portion for external connection of the gate electrode, 4 a glass coat, 5 an insulating film, and 7 an aluminum wiring layer for connection to the gate electrode. Direct wire bonding is performed on the external connection bonding pad portion 18.28.3a described above.
第４図は第３図の半導体装置の１−１断面図である。同
図に示すＪ：うに、ｒ）”ｌｔ板１０上にｎエピタキシ
ャル層１１を形成し、この日 エピタキシャル層１１の
上層部に多数のｐ＋拡散層１２を形成している。各ｐ＋
拡散層１２の上層部には２つずつｎ＋拡散層１３が形成
されており、隣接するｐ＋拡散層１２間には周囲を絶縁
膜１４で覆われたポリシリコンゲート１５が形成されて
いる。FIG. 4 is a 1-1 sectional view of the semiconductor device of FIG. 3. An n epitaxial layer 11 is formed on the J: uni, r)''lt board 10 shown in the same figure, and on this day, a large number of p+ diffusion layers 12 are formed on the upper layer of the epitaxial layer 11. Each p+
Two n+ diffusion layers 13 are formed in the upper layer of the diffusion layer 12, and a polysilicon gate 15 whose periphery is covered with an insulating film 14 is formed between adjacent p+ diffusion layers 12.
このポリシリコンゲート１５は第３図で示した外部接続
用ポンディングパッド部３ａにアルミ配線層７を介して
電気的接続される。This polysilicon gate 15 is electrically connected to an external connection bonding pad portion 3a shown in FIG. 3 via an aluminum wiring layer 7.
また、外部接続用ポンディングパッド部２ａにおいては
、電流検出用ソース電極２が絶縁膜１４を含むｎ−エピ
タキシャル層１１上に形成され直下（７） ｐ” 拡ｒ
ｌ１ｍ ｌ ２ 、 ｎ ” 拡ｒｌｌＩ １３１．：
’ｍ気的ＩＩＦ続される。一方、他の領域においてＡ、
Ｘ−Ｓ＋等により出力用ソース電極１が形成され直下の
ｐ＋拡散層１２．ｎ＋拡散層１３に電気的接続される。In addition, in the external connection bonding pad section 2a, the current detection source electrode 2 is formed on the n-epitaxial layer 11 including the insulating film 14, and is directly below (7) p"
l1m l2, n” expansion rllI 131.:
'm's spirit continues. On the other hand, in other areas A,
The output source electrode 1 is formed by X-S+, etc., and the p+ diffusion layer 12. It is electrically connected to the n+ diffusion layer 13.
この出力用ソース電極１は第３図で示した外部接続用ポ
ンディングパッド部１ａに電気的接続されている。ぞし
て、ガラスコー１〜４がこの出力用ソース電極１を覆う
と共に、電流検出用ソース電極２どの絶縁分離を果たし
ている。このガラスコート４は第１図で示すＪ：うに、
各外部接続用ポンディングパッド部１ ａ、２ａ、３ａ
１絶縁膜５、アルミ配線層７以外の領域を覆っている。This output source electrode 1 is electrically connected to an external connection bonding pad portion 1a shown in FIG. Glass coats 1 to 4 cover the output source electrode 1 and provide insulation and isolation between the current detection source electrodes 2 and the like. This glass coat 4 is J: sea urchin shown in FIG.
Each external connection bonding pad part 1a, 2a, 3a
1 insulating film 5 and the area other than the aluminum wiring layer 7 is covered.
なお、１７はＭＯ８ＦＥＴセルを示し、１Ｂはドレイン
電極である。Note that 17 indicates a MO8FET cell, and 1B is a drain electrode.
このような構成において、動作時にポリシリコンゲート
５に正の電圧を印加し、各ＭＯ８ＦＥＴセル１７のチャ
ネル領域であるポリシリコンゲート１５下のｐ＋拡ｒ１
１．層１２をｒ）型に反転させることで、電流をドレイ
ン？１ｌｌｉ極１８からｎ＋Ｗ板１０゜ｎ−エピタキシ
ャル層１１．各ＭＯ８ＦＥＴセル１７のチャネル領域及
びｎ＋拡散層１３を介して出力用ソース電極１及び電流
検出用ソース電極２に流している。In such a configuration, a positive voltage is applied to the polysilicon gate 5 during operation, and the p+ expansion r1 under the polysilicon gate 15, which is the channel region of each MO8FET cell 17, is
1. By inverting the layer 12 to r) type, the current can be drained? 1lli pole 18 to n+W plate 10°n-epitaxial layer 11. The current flows through the channel region of each MO8FET cell 17 and the n+ diffusion layer 13 to the output source electrode 1 and the current detection source electrode 2.
各ＭＯ８ＦＦＴセル１７を流れる電流量は一定であるこ
とから、出力用ソース１ＩｆｉｉとＮ流検出用ソース電
極２にそれぞれ流れる電流量の比は、出力用ソース電極
１と電流検出用ソース電極２にそれぞれ接続されている
ＭＯ８ＦＥＴセル１７の数の比に等しい。従って、電流
検出用ソース電極２より得られる電流量より出力用ソー
ス電極１を流れる電流量を容易に口出することができる
。Since the amount of current flowing through each MO8FFT cell 17 is constant, the ratio of the amount of current flowing through the output source 1 Ifii and the N current detection source electrode 2 is as follows: It is equal to the ratio of the number of MO8FET cells 17 connected. Therefore, the amount of current flowing through the output source electrode 1 can be easily determined from the amount of current obtained from the current detection source electrode 2.
電流検出用ソース電極を有する従来の半導体装置は以上
のように構成されており、電流検出用ソース電極２を流
れる電流を大きくとると、その分出力用ソース電１！！
１を流れる電流量を削減することになる。A conventional semiconductor device having a current detection source electrode is configured as described above, and when the current flowing through the current detection source electrode 2 is increased, the output source electrode 1! !
This will reduce the amount of current flowing through 1.
従って、電流検出用ソース電極２に接続されるＭＯ３Ｆ
ＥＴセル１７の数は電流量検出が可能な範囲において、
少なくする方が望ましい。Therefore, MO3F connected to the current detection source electrode 2
The number of ET cells 17 is within the range where current amount detection is possible.
Less is better.
しかし４′Ｋがら、電流検出用ソース電極２に接続され
るＭＯ８ＦＥＴセル１７の数を少なくすると、電流検出
用ソース電極２の形成面積が狭くなり、十分な広さの外
部接続用ポンディングパッド部２ａを確保できなくなる
。このため、通常のパワー半導体素子に用いる３００μ
ｍφ程度のＡＩワイヤを使用すると、ワイヤボンディン
グが困難になるという問題点があった。また、電流検出
用ソース電極２の外部接続用ポンディングパッド部２ａ
は大電流を流す必要がないため、このポンディングパッ
ド部２ａのみ径の細い金ワイヤを使用することも考えら
れるが、ポンディングパッド部２ａへのワイヤボンディ
ングのみ径の細いワイヤを使用すると作業性が低下する
という別の問題点を生じてしまう。However, unlike 4'K, if the number of MO8FET cells 17 connected to the current detection source electrode 2 is reduced, the formation area of the current detection source electrode 2 becomes narrower, and the bonding pad area for external connection is sufficiently large. 2a cannot be secured. For this reason, the 300μ
When an AI wire with a diameter of approximately mφ is used, there is a problem in that wire bonding becomes difficult. Also, a bonding pad portion 2a for external connection of the source electrode 2 for current detection.
Since it is not necessary to flow a large current, it may be possible to use a gold wire with a small diameter only for this bonding pad portion 2a, but it is easier to work if a wire with a small diameter is used only for wire bonding to the bonding pad portion 2a. Another problem arises in that the value decreases.
この発明は上記のような問題点を解決するためになされ
たもので、半導体基板内の活性層との接続状態に関係な
く、十分な広さのワイヤボンディング領域を確保するこ
とのできる電極を有する半導体装置を得ることを目的と
する。This invention was made to solve the above problems, and has an electrode that can secure a sufficiently large wire bonding area regardless of the connection state with the active layer in the semiconductor substrate. The purpose is to obtain a semiconductor device.
この発明にかかる半導体装置は、半導体基板−ヒに複数
の電極を有し、前記複数の電極のうち、少なくと−し１
つの電極が絶縁膜を介して他の電極」ニに形成される。A semiconductor device according to the present invention has a plurality of electrodes on a semiconductor substrate, and at least one of the plurality of electrodes has a plurality of electrodes.
One electrode is formed on the other electrode through an insulating film.
この発明におりる少なくどし１つの電極は、他の７Ｅｌ
上に絶縁膜を介して形成されるため、この電極は半導体
基板上に直接形成される電極領域に加え、上記した他の
？ｆ２１４上の電極領域をワイＡ７ボンデイングパツド
領域とすることができる。。At least one electrode according to this invention has another 7El
Since this electrode is formed on the semiconductor substrate with an insulating film interposed therebetween, in addition to the electrode region formed directly on the semiconductor substrate, this electrode is also used in other regions as mentioned above. The electrode area on f214 can be a wire A7 bonding pad area. .
第１図はこの発明の一実施例である電流検出用ソース電
極を右する半導体装置を示Ｊ断面図である。この断面図
は、従来の第３図のＩ−Ｉ断面図に相当する。１１１図
に示づ−ように、少数（図中２つ）のＭＯ３Ｆ［ＥＴセ
ル１７上に第１の電流検出用ソース電極材２０が形成さ
れ、その他のＭ ＯＳ Ｆ ＥＴセル１７上には出力用
ソース電極１が形成されている。ざらに、第２の電流検
出用ソース電極月２１が第１の電流検出用ソース電極材
２０上に積層されるとともに、ポンディングパッド部り
ａ内において、絶縁膜６を介して出力用ソース電極１上
にも形成されている。この絶縁膜６は第１の電流検出用
ソース電極材２０と出力用ソース電極１間にし形成され
、両者１．２０を絶縁分離している。他の構成は従来と
同じであるため説明は省略でる。FIG. 1 is a cross-sectional view of a semiconductor device showing a current detection source electrode according to an embodiment of the present invention. This sectional view corresponds to the conventional sectional view taken along line II in FIG. As shown in Figure 111, the first current detection source electrode material 20 is formed on a small number (two in the figure) of MOSFET cells 17, and the A source electrode 1 is formed. Roughly speaking, the second current detection source electrode material 21 is laminated on the first current detection source electrode material 20, and the output source electrode 21 is laminated on the first current detection source electrode material 20, and the output source electrode 21 is laminated on the first current detection source electrode material 20. It is also formed on 1. This insulating film 6 is formed between the first current detection source electrode material 20 and the output source electrode 1, and insulates and separates both. The other configurations are the same as the conventional ones, so the explanation is omitted.
このにうに構成することで、第１の電流検出用ソース電
極ｔ４２０に接続されるＭＯ３ＦＥＴセル１７の数を少
なくしても、第１及び第２の電流検出用ソース電極材２
０．２１により電流検出用ソース電極２を形成すること
で、十分な大きさのワイヤボンディング部２ａを確保す
ることができる。With this configuration, even if the number of MO3FET cells 17 connected to the first current detection source electrode t420 is reduced, the first and second current detection source electrode materials 2
By forming the current detection source electrode 2 with a thickness of 0.21, a sufficiently large wire bonding portion 2a can be secured.
従って、電流検出用ソース電極材２０を設けることによ
る出力用ソース電極１を流れる電流量の減少を最小限に
抑えるとともに、十分な広さのワイヤボンディング領域
を確保できる。Therefore, a reduction in the amount of current flowing through the output source electrode 1 due to the provision of the current detection source electrode material 20 can be minimized, and a sufficiently large wire bonding area can be secured.
また、第２の電流検出用ソース電極材２１を第１の電流
検出用ソース電極材２０上あるいは絶縁膜６を介して出
力用ソース″市極１上に形成することで電極材料の厚み
が増すため、ボンディング時における活性層（ｐ＋拡散
層１２．ｎ＋拡散層１３）へのダメージを軽減させる効
果もある。この効果は、第２の？ｆｉ流検出用ソース電
極月２１どしてΔＡ−８ｉ、にり柔かいＡｉ等を用いる
ことでざらに向上づる。また、ＡＩはＡｌ−５；より伝
導率が高いという利点も有している。Furthermore, by forming the second current detection source electrode material 21 on the first current detection source electrode material 20 or on the output source electrode 1 via the insulating film 6, the thickness of the electrode material increases. Therefore, it has the effect of reducing damage to the active layer (p+ diffusion layer 12, n+ diffusion layer 13) during bonding. This can be improved by using a soft material such as Al.Al-5 also has the advantage of higher conductivity than Al-5.
なお、この実施例では、電流検出用ソース電極の構造を
改良した崖導体装置について述べたが、第２図に示すよ
うにゲート電極３の構造を改良づ゛ることも考えられる
。第２図に示すように少数（図中１つ）のポリシリコン
ゲート１５上に第１のゲート電極材３０が形成されるこ
とでポリシリコンゲート１５と電気的接続されている。Although this embodiment describes a cliff conductor device in which the structure of the current detection source electrode is improved, it is also possible to improve the structure of the gate electrode 3 as shown in FIG. As shown in FIG. 2, a first gate electrode material 30 is formed on a small number (one in the figure) of polysilicon gates 15 to electrically connect them to the polysilicon gates 15.
そして、第２のゲート電極材３１が第１のゲート電極材
３０上に積層されると共に、ポンディングパッド部り０
ａ内において、絶縁膜６を介して出力用ソース電極１上
に形成される。他の構成は第１図と同様である。このよ
うに構成することで、ポリシリコンゲート１５との電気
的接続箇所が少くとも、十分なワイヤボンディング領域
を有するゲート電極３が形成できる。Then, the second gate electrode material 31 is laminated on the first gate electrode material 30, and the bonding pad portion is
A is formed on the output source electrode 1 with an insulating film 6 interposed therebetween. The other configurations are the same as in FIG. 1. With this configuration, it is possible to form the gate electrode 3 having at least a sufficient wire bonding area at the electrical connection point with the polysilicon gate 15.
また、ＭＯＳＦＥＴに限らずバイポーラトランジスタや
ｌ Ｇ Ｂ Ｔ等の他の種類の半導体装置について゛し
、基板表面に複数の電極を有するものであれば広くこの
発明を適用することかできる。Furthermore, the present invention is widely applicable not only to MOSFETs but also to other types of semiconductor devices such as bipolar transistors and 1GBTs, as long as they have a plurality of electrodes on the substrate surface.
〔発明の効果］
以上説明したように、この発明によれば、電極の一部を
、他の゛上極−ヒに絶縁ｎ９を介して形成することで、
半導体基板上に直）＆形成される電極領域に加え、上記
した他の電極上の電極領域をワイヤポンディングパッド
領域とづることができるため、この電極は、半導体基板
内の活性層との接続状態に関係なく十分な広さのワイヤ
ボンディング領域を形成することができる効果がある。[Effects of the Invention] As explained above, according to the present invention, by forming a part of the electrode on the other upper electrode via the insulation n9,
In addition to the electrode area formed directly on the semiconductor substrate, the electrode area on the other electrodes mentioned above can be referred to as the wire bonding pad area, so that this electrode can be used for connection with the active layer within the semiconductor substrate. This has the advantage that a wire bonding area of sufficient size can be formed regardless of the state.
第１図はこの発明の一実施例である半導体装置を示す断
面図、第２図はこの発明の他の実施例である半導体装置
を示す断面図、第３図は従来の半導体装置を示寸平面図
、第４図は第３図の半導体装置のｉ−Ｉ断面図である。
図において、１は出ツノ用ソース電極、２は電流検出用
ソース電極、６は絶縁膜、２０は第１の電流検出用ソー
ス電極材、２１は第２の電流検出用ソース電極材である
。
なお、各図中同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄
第
図
ａ
ａ
手続補正書（自発）
平成
≠抑 １年 ５月
８日
２、発明の名称
半導体装置
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名
称 （６０１）三菱電機株式会社代表者 志 岐
守 哉
４、代理人
５、補正の対象
明細書の［発明の詳細な説明の欄」並びに図面の第１図
、第３図及び第４図
６、補正の内容
（１） 明細書第２頁第１行ないし第２行の「４はガ
ラスコート、５は絶縁膜１を、［５はゲート・ソース間
絶縁部、６は絶縁膜］に訂正する。
（２） 明ｍ書第２頁第９行、同第１０行、同第１２
ｔｌ、同第２０行、第３頁第２行ないし第３行。
同第１７行及び第８頁第２行の「ｐ＋拡散層１２」を、
［ｐ−拡散層１２」に訂正する。
（３） 明細書第３頁第１０行ないし第１１行の［上
層部には２つずつ］を［内部には１に訂正する。
（４） 明細書第３頁第１４の「ガラスコート４」を
、［絶縁１！ｉ！６Ｊに訂正する。
（５） 明細書第３頁第８行ないし第１１行の［この
ガラスコート４は・・・覆っている。」を削除する。
（６） 明細書第３頁第１４行ないし第１５行の「ポ
リシリコンゲート５」を、「ポリシリコンゲート１５」
に訂正する。
（１） 明細書第４頁第１行の「及び」を、「または
１に訂正する。
（８） 明細書筒Ｅ３頁第１７行のｒ３０ａｌ゛を、
ｒ３ａｌに訂正り“る。
（９） 明細書第８頁第１９行ないし第９頁第２行の
［ポリシリコンゲート１５との・・・形成できる。
」を、［ボンゲイングパッド部りａ内にす、ＭＯＳ Ｆ
Ｅ Ｔヒルを形成することが可能となるとともに、ゲ
ート抵抗を減少さぼることにもつながる。−１に訂正す
る。
（１０）図面の第１図、第３図および第４図を別紙の通
り補正する。
以上
第
図
ａ
Ｎ！−〇FIG. 1 is a sectional view showing a semiconductor device which is an embodiment of the present invention, FIG. 2 is a sectional view showing a semiconductor device which is another embodiment of the invention, and FIG. 3 is a sectional view showing a conventional semiconductor device. The plan view, FIG. 4, is a sectional view taken along line i--I of the semiconductor device shown in FIG. In the figure, reference numeral 1 denotes a source electrode for output, 2 a source electrode for current detection, 6 an insulating film, 20 a first source electrode material for current detection, and 21 a second source electrode material for current detection. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Diagram a a Procedural amendment (voluntary) May 8, 1999 2 Name of the invention Semiconductor device 3 Relationship to the case of the person making the amendment Patent applicant address Chiyoda, Tokyo 2-2-3 Marunouchi Ward Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, Agent 5, [Detailed description of the invention column] of the specification to be amended, Figures 1, 3 and 4 of the drawings 6, Contents of the amendment (1) Page 2 of the specification In the first and second lines, "4 is the glass coat, 5 is the insulating film 1, [5 is the gate-source insulating part, 6 is the insulating film]". (2) Memorandum, page 2 9th line, 10th line, 12th line
tl, line 20, page 3, lines 2 and 3. "p+ diffusion layer 12" in line 17 and line 2 of page 8,
Corrected to "p-diffusion layer 12". (3) In lines 10 and 11 of page 3 of the specification, [2 each in the upper part] is corrected to [1 in the inside]. (4) Add "Glass Coat 4" on page 3, No. 14 of the specification to [Insulation 1! i! Corrected to 6J. (5) [This glass coat 4 covers...] on page 3 of the specification, lines 8 to 11. ” to be deleted. (6) "Polysilicon gate 5" on page 3, line 14 to line 15 of the specification is replaced with "polysilicon gate 15".
Correct. (1) Correct “and” in the first line of page 4 of the specification to “or 1.” (8) Correct r30al゛ in line 17 of page 3 of the specification tube E.
(9) From page 8, line 19 to page 9, line 2 of the specification, [can be formed with polysilicon gate 15] has been changed to [in bonding pad area a]. Nisu, MOS F
This makes it possible to form an ET hill and also leads to a reduction in gate resistance. Correct to -1. (10) Figures 1, 3, and 4 of the drawings will be corrected as shown in the attached sheet. Above is Figure a N! −〇
Claims (1)
おいて、 前記複数の電極のうち、少なくとも１つの電極が絶縁膜
を介して他の電極上に形成されることを特徴とする半導
体装置。(1) A semiconductor device having a plurality of electrodes on a semiconductor substrate, wherein at least one electrode among the plurality of electrodes is formed on another electrode with an insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63204397A JPH0252468A (en) | 1988-08-17 | 1988-08-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63204397A JPH0252468A (en) | 1988-08-17 | 1988-08-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0252468A true JPH0252468A (en) | 1990-02-22 |
Family
ID=16489865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63204397A Pending JPH0252468A (en) | 1988-08-17 | 1988-08-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0252468A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0394472A (en) * | 1989-09-06 | 1991-04-19 | Matsushita Electron Corp | Vertical type mos field-effect transistor |
| JP2002314086A (en) * | 2001-04-13 | 2002-10-25 | Sanyo Electric Co Ltd | Mosfet |
| JP2009105177A (en) * | 2007-10-23 | 2009-05-14 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
| JP2009194330A (en) * | 2008-02-18 | 2009-08-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| WO2020250869A1 (en) * | 2019-06-14 | 2020-12-17 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
| EP3817039A4 (en) * | 2019-02-07 | 2021-12-08 | Fuji Electric Co., Ltd. | Semiconductor device |
| JP2022527399A (en) * | 2019-04-11 | 2022-06-01 | ウルフスピード インコーポレイテッド | Transistor semiconductor die with increased working area |
-
1988
- 1988-08-17 JP JP63204397A patent/JPH0252468A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0394472A (en) * | 1989-09-06 | 1991-04-19 | Matsushita Electron Corp | Vertical type mos field-effect transistor |
| JP2002314086A (en) * | 2001-04-13 | 2002-10-25 | Sanyo Electric Co Ltd | Mosfet |
| JP2009105177A (en) * | 2007-10-23 | 2009-05-14 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
| JP2009194330A (en) * | 2008-02-18 | 2009-08-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| EP3817039A4 (en) * | 2019-02-07 | 2021-12-08 | Fuji Electric Co., Ltd. | Semiconductor device |
| JP2022527399A (en) * | 2019-04-11 | 2022-06-01 | ウルフスピード インコーポレイテッド | Transistor semiconductor die with increased working area |
| WO2020250869A1 (en) * | 2019-06-14 | 2020-12-17 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
| JP2020205298A (en) * | 2019-06-14 | 2020-12-24 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
| US20220359694A1 (en) * | 2019-06-14 | 2022-11-10 | Hitachi Astemo, Ltd. | Semiconductor device |
| EP3985716A4 (en) * | 2019-06-14 | 2023-06-28 | Hitachi Astemo, Ltd. | Semiconductor device |
| US11855166B2 (en) | 2019-06-14 | 2023-12-26 | Hitachi Astemo, Ltd. | Semiconductor device including sub-cell disposed at chip center |
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