JPH0430531A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0430531A JPH0430531A JP13875290A JP13875290A JPH0430531A JP H0430531 A JPH0430531 A JP H0430531A JP 13875290 A JP13875290 A JP 13875290A JP 13875290 A JP13875290 A JP 13875290A JP H0430531 A JPH0430531 A JP H0430531A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- potential
- insulating film
- side wiring
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229920001721 polyimide Polymers 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000009719 polyimide resin Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 2
- 230000007797 corrosion Effects 0.000 abstract description 10
- 238000005260 corrosion Methods 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 8
- 238000002161 passivation Methods 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 239000008151 electrolyte solution Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 229910001679 gibbsite Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はアルミ配線の電解腐食による不良発生を防止で
きる半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit that can prevent defects caused by electrolytic corrosion of aluminum wiring.
（ロ）従来の技術
半導体素子の配線金属として、アルミニウムはオーミッ
ク性が容易に得られる、電気伝導性が良い、低コストで
あるなどの点でもっとも多く用いられている。素子内部
の構造は、第３図に示す如＜ Ｓｉｎ、やポリイミド系
樹脂から成る絶縁膜（１）表面をアルミ（Ａｌ）又はア
ルミ・シリフン（Ａｌ−５ｉ）から成る配線（２）（３
）を延在きせたもので、配線（２）（３）は絶縁膜（１
）に開けられたコンタクトホールを介してその下の基板
表面に設けられた拡散領域とオーミックコンタクトし、
所望の回路接続を行なうようになっている。多層配線構
造では、配線（２）（３）の絶縁膜（１）に開けられた
スルーホールを介してその下の配線層と電気接続するこ
とになる。そして、配線（２＞（３）の表面はＳｉｎ、
やポリイミド系樹脂等のパッシベーション被膜（４）で
覆われている。(B) Prior Art Aluminum is most often used as a wiring metal for semiconductor devices because it can easily obtain ohmic properties, has good electrical conductivity, and is low cost. The internal structure of the element is as shown in Figure 3. The surface of an insulating film (1) made of Sin or polyimide resin is covered with wiring (2) (3) made of aluminum (Al) or aluminum silicon (Al-5i).
) is extended, and the wiring (2) and (3) are insulating film (1
) makes ohmic contact with the diffusion region provided on the substrate surface below through the contact hole opened in
The desired circuit connections are made. In the multilayer wiring structure, the wirings (2) and (3) are electrically connected to the underlying wiring layer through through holes formed in the insulating film (1). Then, the surface of the wiring (2>(3) is Sin,
It is covered with a passivation film (4) made of polyimide resin or the like.
（ハ〉発明が解決しようとする課題
しかしながら、隣接する配線（２）（３）間に例えばｙ
ｃｃとＧＮＤの如きバイアス電圧が印加された場合、
樹脂中に含まれる又は外部より侵入した水分と、樹脂中
に含まれる可動イオンにより配線り２）（３）間に電解
質溶液が生じ、前記バイアス印加に伴うリーク電流の作
用によって電気分解が生じることに起因し、
高電位側配線（３）では
ＡＮ ＋４Ｃ１−→ＡｊＩＣｊ２４−＋３ｅＡＩＣ１ｍ
−＋５ｕｚｏ−Ａｆｆｉ （ＯＨ）、＋３Ｈ“＋４Ｃ！
−・・・（１）なる反応式で、低電位側配線（２）では
Ａｊ！＋３（ＯＨ＞−＝Ａｊ！（ＯＨ）ｓ＋３ｅ ・
＝・”・””・”＜２）なる反応式で電解腐食が発生す
るのである。このようなＡｆｆｉの腐食は、ポンディン
グパッド部の例であるが例えば特開昭６３−１７９５３
８号に記載されている。(C) Problem to be solved by the invention However, for example, between the adjacent wirings (2) and (3)
When a bias voltage such as cc and GND is applied,
Moisture contained in the resin or invaded from the outside and mobile ions contained in the resin generate an electrolyte solution between wiring lines 2) and 3), and electrolysis occurs due to the action of leakage current accompanying the bias application. Due to this, in the high potential side wiring (3), AN +4C1-→AjICj24-+3eAIC1m
-+5uzo-Affi (OH), +3H"+4C!
-...(1) In the reaction formula, Aj! on the low potential side wiring (2)! +3(OH>-=Aj!(OH)s+3e ・
Electrolytic corrosion occurs according to the reaction formula =・”・””・”<2). Such corrosion of Affi is an example of the bonding pad part, and for example,
It is stated in No. 8.
また、絶縁膜（１）やパッシベーション被膜（４）とし
て段差の被覆性、コスト、および工程の簡素化に優れた
ポリイミド系樹脂を用いると、上述した腐食が著しい。Further, if polyimide resin, which is excellent in step coverage, cost, and process simplification, is used as the insulating film (1) or the passivation film (4), the above-mentioned corrosion is significant.
理由は、第１にポリイミド系樹脂の耐湿性自体がシリコ
ン窒化膜（ＳｉＮ）等のものより劣ること、第２にポリ
イミド系樹脂表面にアルミとの密着性を向上する目的で
アルミ堆積前に処す粗面処理（逆スパッタ等）によって
絶縁膜（１〉表面に導電層（カーボン等）が形成され、
前記電解イオンが移動しやすい状態であること、である
。The reason is that firstly, the moisture resistance of polyimide resin itself is inferior to that of silicon nitride (SiN) films, etc., and secondly, the polyimide resin surface is treated before aluminum is deposited in order to improve its adhesion with aluminum. A conductive layer (carbon, etc.) is formed on the surface of the insulating film (1) by roughening (reverse sputtering, etc.),
The electrolytic ions are in a state where they are easy to move.
このような電解腐食による断線を防止するため、従来は
低電位側配線（２〉と高電位側配線（３）との距離を広
くとることで対応していたが、チップサイズが大きくな
る欠点を有していた。In order to prevent such disconnection due to electrolytic corrosion, the conventional method was to widen the distance between the low potential side wiring (2) and the high potential side wiring (3), but this method had the drawback of increasing the chip size. had.
（ニ）課題を解決するための手段
本発明は上記従来の欠点に鑑み成されたもので、低電位
側配線（２）と高電位側配線（３〉との間の絶縁膜（１
〉上に、何の電位も印加しないフローティング状態とし
た遮断配線（５）を配置することにより、腐食による断
線を防止できる半導体集積回路を提供するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks of the conventional art.
By arranging a cutoff wiring (5) in a floating state with no potential applied thereon, a semiconductor integrated circuit is provided in which disconnection due to corrosion can be prevented.
（＊〉作用
本発明によれば、遮断配線（５）のＡ２表面は通常の条
件下で表面が酸化物被膜で不働態化されており、且つ絶
縁膜（１）との密着力は絶縁膜（１）とパッシベーショ
ン被膜（４）のものより強固である。そのため、主に絶
縁膜（１）表面を流れるリーク電流の導通路に遮断配線
（５）による絶縁物が配置きれたのに等しく、前記リー
ク電流を抑制できるので、腐食反応も抑制できる。(*> Function) According to the present invention, the A2 surface of the cutoff wiring (5) is passivated with an oxide film under normal conditions, and the adhesion with the insulating film (1) is as low as that of the insulating film. It is stronger than the passivation film (1) and the passivation film (4).Therefore, it is equivalent to placing the insulator by the cutoff wiring (5) in the conduction path of the leakage current that mainly flows on the surface of the insulating film (1). Since the leakage current can be suppressed, corrosion reactions can also be suppressed.
〈へ）実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。<Example> An example of the present invention will be described below in detail with reference to the drawings.
第１図と第２図は夫々本発明の配線構造を示す平面図と
断面図である。以下、配線層が多層配線の２層目配線で
ある構造を例にとる。FIG. 1 and FIG. 2 are a plan view and a cross-sectional view, respectively, showing the wiring structure of the present invention. Hereinafter, a structure in which the wiring layer is a second layer wiring of a multilayer wiring will be taken as an example.
図示せぬ半導体チップの表面には選択拡散によって多数
の回路素子（トランジスタ、抵抗等）が作り込まれ、チ
ップ表面を覆う酸化膜を開孔したコンタクトホールを介
して第１層の配線層が不純物拡散領域とフンタクトする
。前記第１層目配線を覆うようにして層間絶縁膜（１）
が形成され、層間絶縁膜（１）上に第２の配線層によっ
て低電位側配線（２）と高電位側配線（３）とが形成き
れる。前記第１の配線層と第２の配線層とは、層間絶縁
膜（１）を開口したスルーホールを介してコンタクトし
、前記回路素子の相互接続をとる。前記第２の配線層の
表面は、パッシベーション被膜（４）で覆われる。A large number of circuit elements (transistors, resistors, etc.) are built into the surface of a semiconductor chip (not shown) by selective diffusion, and the first wiring layer is exposed to impurities through contact holes in the oxide film covering the chip surface. Interact with the diffusion area. An interlayer insulating film (1) covering the first layer wiring
is formed, and a low potential side wiring (2) and a high potential side wiring (3) are completed by the second wiring layer on the interlayer insulating film (1). The first wiring layer and the second wiring layer are in contact with each other via a through hole opened in the interlayer insulating film (1), and the circuit elements are interconnected. The surface of the second wiring layer is covered with a passivation film (4).
前記層間絶縁膜（１）は、ＣＶＤ法によるシリコン酸化
膜を用いる他、スピンオン塗布法によるポリイミド系絶
縁膜を用いることもできる。この場合、アルミとの密着
性を向上する目的で層間絶縁膜（１）表面に粗面化処理
を処す。手法は逆スパッタ等である。そして粗面化いれ
た層間絶縁膜（１）上に蒸着又はスパッタ法により八！
又はＡＮ −５ｉを堆積し、これをバターニングするこ
とで前記第２の配線層を形成する。層間絶縁膜（１）が
ポリイミドであれば、最終パッシベーション被膜（４〉
もボッイミド系絶縁膜とする。The interlayer insulating film (1) may be a silicon oxide film formed by CVD, or may be a polyimide insulating film formed by spin-on coating. In this case, the surface of the interlayer insulating film (1) is roughened in order to improve its adhesion to aluminum. The method is reverse sputtering, etc. Then, on the roughened interlayer insulating film (1), vapor deposition or sputtering is performed.
Alternatively, the second wiring layer is formed by depositing AN-5i and patterning it. If the interlayer insulating film (1) is polyimide, the final passivation film (4)
Also, a boimide insulating film is used.
上記第２の配線による低電位側配線（２）と高電位側配
線（３）は、動作時に夫々接地電位（ＧＮＤ）と電源電
位（ＶｃＣ）の如き電位が印加され、両者間に電位差が
生ずるものである。このように電位差がある配線が近接
配置されることは、半導体チップのパターン設計上比較
的多くみられる。During operation, potentials such as ground potential (GND) and power supply potential (VcC) are applied to the low potential side wiring (2) and high potential side wiring (3) of the second wiring, respectively, and a potential difference occurs between them. It is something. In pattern design of semiconductor chips, it is relatively common for wiring lines with potential differences to be placed close to each other in this manner.
近接配置を全く無くすことは、パターン設計に多大な制
約を与えることになる。Eliminating close placement at all would place significant restrictions on pattern design.
そして、近接配置された低電位側配線（２）と高電位側
配線（３）との間の絶縁膜（１）表面に、前記第２の配
線層のパターニングと同時に遮断配線（５）を形成する
。遮断配線（５）はどこにも結線せず、何の電位も印加
しないフローティング状態とする。線幅は任意である。Then, at the same time as patterning the second wiring layer, a cutoff wiring (5) is formed on the surface of the insulating film (1) between the low potential side wiring (2) and the high potential side wiring (3) arranged in close proximity. do. The cutoff wiring (5) is not connected anywhere and is in a floating state with no potential applied. Line width is arbitrary.
また、低電位側配線（２）と高電位側配線（３）とが近
接した部分にのみ延在させれば良い。Moreover, it is sufficient to extend only the portion where the low potential side wiring (2) and the high potential side wiring (3) are close to each other.
上述した本発明の配線構造においては、低電位側配線（
２）と高電位側配線（３）とのバイアス印加に伴い電解
質溶液中の可動イオン（（Ｊ−、Ｎａ′″等）が夫々に
移動しようとする。移動ルートは絶縁膜（１）表面の界
面が主である。ところが、低電位側配線（２〉と高電位
側配線（３）との間には遮断配線（５）が配置され、遮
断配線（５）はアニール処理によって絶縁膜（１）とパ
ッシベーション被膜（４）との密着より強固に絶縁膜（
１）と密着しているので、前記可動イオンは遮断配線（
５）と絶縁膜（１）との界面を移動できない０分子径が
大き過ぎるのである。又電位的にフローティングされた
遮断配線の表面は、酸化物被膜で不働態化きれているた
め、電気的反応が行なわれにくい。このため、低電位側
配線（２）と高電位側配線（３）の間は、その電解質溶
液中に、不働態ギブサイトに保護された遮断配線で、絶
縁された状態になっている。従って、画電極（２）（３
）間の可動イオンの移動を阻止できるので、（１）（２
）式の電解腐食を抑制し、配線（２）（３）の劣化、断
線を防止できるのである。高温高湿状態で動作試験を行
なうＴＨＢ試験においても、本願発明は優れた効果をも
たらすことが確認された。In the wiring structure of the present invention described above, the low potential side wiring (
2) and the high potential side wiring (3), mobile ions ((J-, Na''', etc.) in the electrolyte solution try to move to each other.The migration route is along the surface of the insulating film (1). However, a cut-off wire (5) is arranged between the low-potential side wire (2) and the high-potential side wire (3), and the cut-off wire (5) is coated with an insulating film (1) by annealing. ) and the passivation film (4), the insulation film (
1), the mobile ions are in close contact with the cutoff wiring (
5) and the insulating film (1), the diameter of the molecule is too large. Furthermore, since the surface of the electrically floating cutoff wiring is completely passivated with an oxide film, electrical reactions are difficult to occur. Therefore, the low potential side wiring (2) and the high potential side wiring (3) are insulated by a cutoff wiring protected by passive gibbsite in the electrolyte solution. Therefore, picture electrodes (2) (3
) can prevent the movement of mobile ions between (1) and (2).
) type electrolytic corrosion can be suppressed, and deterioration and disconnection of wiring (2) and (3) can be prevented. It was confirmed that the present invention has excellent effects also in the THB test, which is an operation test conducted under high temperature and high humidity conditions.
（ト）発明の効果
以上に説明した通り、本発明は遮断配線（５）をダムと
して可動イオンの界面での移動を阻止できるので、腐食
反応を抑制し配、１（２）（３）の劣化、断線を防止で
きる利点を有する。従って、耐湿性の高い半導体装置を
提供できる利点をも有する。また、低電位側配線（２）
と高電位側配線（３）との間を広くする必要がないので
、チップサイズの縮手にも寄与できる利点をも有する。(G) Effects of the Invention As explained above, the present invention can prevent the movement of mobile ions at the interface by using the cutoff wiring (5) as a dam. It has the advantage of preventing deterioration and disconnection. Therefore, it also has the advantage of providing a semiconductor device with high moisture resistance. Also, low potential side wiring (2)
Since there is no need to widen the space between the wire and the high potential side wiring (3), it also has the advantage of contributing to reduction in chip size.
第１図と第２図は夫々本発明を説明する為の平面図と断
面図、第３図は従来例を説明する為の断面図である。1 and 2 are a plan view and a sectional view, respectively, for explaining the present invention, and FIG. 3 is a sectional view for explaining a conventional example.
Claims (3)
った電位が与えられる２つの配線が互いに隣接して絶縁
膜上を延在する半導体集積回路において、 前記２つの配線の高電位側配線と低電位側配線との間の
前記絶縁膜上に、前記導電材料から成り何の電位も印加
しないフローティング状態とした遮断配線を配置したこ
とを特徴とする半導体集積回路。(1) In a semiconductor integrated circuit in which two wirings made of a conductive material mainly made of aluminum and to which different potentials are applied extend adjacent to each other on an insulating film, the high-potential side wiring of the two wirings and A semiconductor integrated circuit characterized in that a cut-off wiring made of the conductive material and placed in a floating state to which no potential is applied is disposed on the insulating film between the wiring on the low potential side.
とする請求項第１項に記載の半導体集積回路。(2) The semiconductor integrated circuit according to claim 1, wherein the insulating film is made of polyimide resin.
粗面化処理が処されていることを特徴とする請求項第１
項に記載の半導体集積回路。(3) The surface of the polyimide resin is roughened by reverse sputtering.
The semiconductor integrated circuit described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13875290A JPH0430531A (en) | 1990-05-28 | 1990-05-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13875290A JPH0430531A (en) | 1990-05-28 | 1990-05-28 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430531A true JPH0430531A (en) | 1992-02-03 |
Family
ID=15229356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13875290A Pending JPH0430531A (en) | 1990-05-28 | 1990-05-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430531A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5472305B2 (en) * | 2009-08-19 | 2014-04-16 | 日本電気株式会社 | Feed line structure, circuit board using the same, and EMI noise reduction method |
-
1990
- 1990-05-28 JP JP13875290A patent/JPH0430531A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5472305B2 (en) * | 2009-08-19 | 2014-04-16 | 日本電気株式会社 | Feed line structure, circuit board using the same, and EMI noise reduction method |
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